README.txt revision 76e7a441cf04798eb183a375870c45bcaeacd9ae 
1
2To-do
3-----
4
5* Keep the address of the constant pool in a register instead of forming its
6  address all of the time.
7* We can fold small constant offsets into the %hi/%lo references to constant
8  pool addresses as well.
9* When in V9 mode, register allocate %icc[0-3].
10* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
11  not clear how to write a pattern for this though:
12
13float %t1(int %a, int* %p) {
14        %C = seteq int %a, 0
15        br bool %C, label %T, label %F
16T:
17        store int 123, int* %p
18        br label %F
19F:
20        ret float undef
21}
22
23codegens to this:
24
25t1:
26        save -96, %o6, %o6
271)      subcc %i0, 0, %l0
281)      bne .LBBt1_2    ! F
29        nop
30.LBBt1_1:       ! T
31        or %g0, 123, %l0
32        st %l0, [%i1]
33.LBBt1_2:       ! F
34        restore %g0, %g0, %g0
35        retl
36        nop
37
381) should be replaced with a brz in V9 mode.
39
40* Same as above, but emit conditional move on register zero (p192) in V9 
41  mode.  Testcase:
42
43int %t1(int %a, int %b) {
44        %C = seteq int %a, 0
45        %D = select bool %C, int %a, int %b
46        ret int %D
47}
48
49* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
50  with the Y register, if they are faster.
51
52* Codegen bswap(load)/store(bswap) -> load/store ASI
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