SparcISelDAGToDAG.cpp revision 27b7db549e4c5bff4579d209304de5628513edeb 
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the SPARC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcTargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/Intrinsics.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/CodeGen/SelectionDAGISel.h"
25#include "llvm/Target/TargetLowering.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include <queue>
29#include <set>
30using namespace llvm;
31
32//===----------------------------------------------------------------------===//
33// TargetLowering Implementation
34//===----------------------------------------------------------------------===//
35
36namespace SPISD {
37  enum {
38    FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
39    CMPICC,      // Compare two GPR operands, set icc.
40    CMPFCC,      // Compare two FP operands, set fcc.
41    BRICC,       // Branch to dest on icc condition
42    BRFCC,       // Branch to dest on fcc condition
43    SELECT_ICC,  // Select between two values using the current ICC flags.
44    SELECT_FCC,  // Select between two values using the current FCC flags.
45
46    Hi, Lo,      // Hi/Lo operations, typically on a global address.
47
48    FTOI,        // FP to Int within a FP register.
49    ITOF,        // Int to FP within a FP register.
50
51    CALL,        // A call instruction.
52    RET_FLAG     // Return with a flag operand.
53  };
54}
55
56/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
57/// condition.
58static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
59  switch (CC) {
60  default: assert(0 && "Unknown integer condition code!");
61  case ISD::SETEQ:  return SPCC::ICC_E;
62  case ISD::SETNE:  return SPCC::ICC_NE;
63  case ISD::SETLT:  return SPCC::ICC_L;
64  case ISD::SETGT:  return SPCC::ICC_G;
65  case ISD::SETLE:  return SPCC::ICC_LE;
66  case ISD::SETGE:  return SPCC::ICC_GE;
67  case ISD::SETULT: return SPCC::ICC_CS;
68  case ISD::SETULE: return SPCC::ICC_LEU;
69  case ISD::SETUGT: return SPCC::ICC_GU;
70  case ISD::SETUGE: return SPCC::ICC_CC;
71  }
72}
73
74/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
75/// FCC condition.
76static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
77  switch (CC) {
78  default: assert(0 && "Unknown fp condition code!");
79  case ISD::SETEQ:
80  case ISD::SETOEQ: return SPCC::FCC_E;
81  case ISD::SETNE:
82  case ISD::SETUNE: return SPCC::FCC_NE;
83  case ISD::SETLT:
84  case ISD::SETOLT: return SPCC::FCC_L;
85  case ISD::SETGT:
86  case ISD::SETOGT: return SPCC::FCC_G;
87  case ISD::SETLE:
88  case ISD::SETOLE: return SPCC::FCC_LE;
89  case ISD::SETGE:
90  case ISD::SETOGE: return SPCC::FCC_GE;
91  case ISD::SETULT: return SPCC::FCC_UL;
92  case ISD::SETULE: return SPCC::FCC_ULE;
93  case ISD::SETUGT: return SPCC::FCC_UG;
94  case ISD::SETUGE: return SPCC::FCC_UGE;
95  case ISD::SETUO:  return SPCC::FCC_U;
96  case ISD::SETO:   return SPCC::FCC_O;
97  case ISD::SETONE: return SPCC::FCC_LG;
98  case ISD::SETUEQ: return SPCC::FCC_UE;
99  }
100}
101
102namespace {
103  class SparcTargetLowering : public TargetLowering {
104    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
105  public:
106    SparcTargetLowering(TargetMachine &TM);
107    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
108
109    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
110    /// in Mask are known to be either zero or one and return them in the
111    /// KnownZero/KnownOne bitsets.
112    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
113                                                const APInt &Mask,
114                                                APInt &KnownZero,
115                                                APInt &KnownOne,
116                                                const SelectionDAG &DAG,
117                                                unsigned Depth = 0) const;
118
119    virtual std::vector<SDOperand>
120      LowerArguments(Function &F, SelectionDAG &DAG);
121    virtual std::pair<SDOperand, SDOperand>
122      LowerCallTo(SDOperand Chain, const Type *RetTy,
123                  bool RetSExt, bool RetZExt, bool isVarArg,
124                  unsigned CC, bool isTailCall, SDOperand Callee,
125                  ArgListTy &Args, SelectionDAG &DAG);
126    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
127                                                        MachineBasicBlock *MBB);
128
129    virtual const char *getTargetNodeName(unsigned Opcode) const;
130  };
131}
132
133SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
134  : TargetLowering(TM) {
135
136  // Set up the register classes.
137  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
138  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
139  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
140
141  // Turn FP extload into load/fextend
142  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
143  // Sparc doesn't have i1 sign extending load
144  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
145  // Turn FP truncstore into trunc + store.
146  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
147
148  // Custom legalize GlobalAddress nodes into LO/HI parts.
149  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
150  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
151  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
152
153  // Sparc doesn't have sext_inreg, replace them with shl/sra
154  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
155  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
156  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
157
158  // Sparc has no REM or DIVREM operations.
159  setOperationAction(ISD::UREM, MVT::i32, Expand);
160  setOperationAction(ISD::SREM, MVT::i32, Expand);
161  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
162  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
163
164  // Custom expand fp<->sint
165  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
166  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
167
168  // Expand fp<->uint
169  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
170  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
171
172  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
173  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
174
175  // Sparc has no select or setcc: expand to SELECT_CC.
176  setOperationAction(ISD::SELECT, MVT::i32, Expand);
177  setOperationAction(ISD::SELECT, MVT::f32, Expand);
178  setOperationAction(ISD::SELECT, MVT::f64, Expand);
179  setOperationAction(ISD::SETCC, MVT::i32, Expand);
180  setOperationAction(ISD::SETCC, MVT::f32, Expand);
181  setOperationAction(ISD::SETCC, MVT::f64, Expand);
182
183  // Sparc doesn't have BRCOND either, it has BR_CC.
184  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
185  setOperationAction(ISD::BRIND, MVT::Other, Expand);
186  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
187  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
188  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
189  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
190
191  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
192  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
193  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
194
195  // SPARC has no intrinsics for these particular operations.
196  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
197  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
198  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
199  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
200  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
201
202  setOperationAction(ISD::FSIN , MVT::f64, Expand);
203  setOperationAction(ISD::FCOS , MVT::f64, Expand);
204  setOperationAction(ISD::FREM , MVT::f64, Expand);
205  setOperationAction(ISD::FSIN , MVT::f32, Expand);
206  setOperationAction(ISD::FCOS , MVT::f32, Expand);
207  setOperationAction(ISD::FREM , MVT::f32, Expand);
208  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
209  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
210  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
211  setOperationAction(ISD::ROTL , MVT::i32, Expand);
212  setOperationAction(ISD::ROTR , MVT::i32, Expand);
213  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
214  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
215  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
216  setOperationAction(ISD::FPOW , MVT::f64, Expand);
217  setOperationAction(ISD::FPOW , MVT::f32, Expand);
218
219  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
220  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
221  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
222
223  // FIXME: Sparc provides these multiplies, but we don't have them yet.
224  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
225
226  // We don't have line number support yet.
227  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
228  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
229  setOperationAction(ISD::LABEL, MVT::Other, Expand);
230
231  // RET must be custom lowered, to meet ABI requirements
232  setOperationAction(ISD::RET               , MVT::Other, Custom);
233
234  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
235  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
236  // VAARG needs to be lowered to not do unaligned accesses for doubles.
237  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
238
239  // Use the default implementation.
240  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
241  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
242  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
243  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
244  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
245
246  // No debug info support yet.
247  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
248  setOperationAction(ISD::LABEL, MVT::Other, Expand);
249  setOperationAction(ISD::DECLARE, MVT::Other, Expand);
250
251  setStackPointerRegisterToSaveRestore(SP::O6);
252
253  if (TM.getSubtarget<SparcSubtarget>().isV9())
254    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
255
256  computeRegisterProperties();
257}
258
259const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
260  switch (Opcode) {
261  default: return 0;
262  case SPISD::CMPICC:     return "SPISD::CMPICC";
263  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
264  case SPISD::BRICC:      return "SPISD::BRICC";
265  case SPISD::BRFCC:      return "SPISD::BRFCC";
266  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
267  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
268  case SPISD::Hi:         return "SPISD::Hi";
269  case SPISD::Lo:         return "SPISD::Lo";
270  case SPISD::FTOI:       return "SPISD::FTOI";
271  case SPISD::ITOF:       return "SPISD::ITOF";
272  case SPISD::CALL:       return "SPISD::CALL";
273  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
274  }
275}
276
277/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
278/// be zero. Op is expected to be a target specific node. Used by DAG
279/// combiner.
280void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
281                                                         const APInt &Mask,
282                                                         APInt &KnownZero,
283                                                         APInt &KnownOne,
284                                                         const SelectionDAG &DAG,
285                                                         unsigned Depth) const {
286  APInt KnownZero2, KnownOne2;
287  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
288
289  switch (Op.getOpcode()) {
290  default: break;
291  case SPISD::SELECT_ICC:
292  case SPISD::SELECT_FCC:
293    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
294                          Depth+1);
295    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
296                          Depth+1);
297    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
298    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
299
300    // Only known if known in both the LHS and RHS.
301    KnownOne &= KnownOne2;
302    KnownZero &= KnownZero2;
303    break;
304  }
305}
306
307/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
308/// either one or two GPRs, including FP values.  TODO: we should pass FP values
309/// in FP registers for fastcc functions.
310std::vector<SDOperand>
311SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
312  MachineFunction &MF = DAG.getMachineFunction();
313  MachineRegisterInfo &RegInfo = MF.getRegInfo();
314  std::vector<SDOperand> ArgValues;
315
316  static const unsigned ArgRegs[] = {
317    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
318  };
319
320  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
321  unsigned ArgOffset = 68;
322
323  SDOperand Root = DAG.getRoot();
324  std::vector<SDOperand> OutChains;
325
326  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
327    MVT::ValueType ObjectVT = getValueType(I->getType());
328
329    switch (ObjectVT) {
330    default: assert(0 && "Unhandled argument type!");
331    case MVT::i1:
332    case MVT::i8:
333    case MVT::i16:
334    case MVT::i32:
335      if (I->use_empty()) {                // Argument is dead.
336        if (CurArgReg < ArgRegEnd) ++CurArgReg;
337        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
338      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
339        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
340        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
341        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
342        if (ObjectVT != MVT::i32) {
343          unsigned AssertOp = ISD::AssertSext;
344          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
345                            DAG.getValueType(ObjectVT));
346          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
347        }
348        ArgValues.push_back(Arg);
349      } else {
350        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
351        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
352        SDOperand Load;
353        if (ObjectVT == MVT::i32) {
354          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
355        } else {
356          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
357
358          // Sparc is big endian, so add an offset based on the ObjectVT.
359          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
360          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
361                              DAG.getConstant(Offset, MVT::i32));
362          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
363                                NULL, 0, ObjectVT);
364          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
365        }
366        ArgValues.push_back(Load);
367      }
368
369      ArgOffset += 4;
370      break;
371    case MVT::f32:
372      if (I->use_empty()) {                // Argument is dead.
373        if (CurArgReg < ArgRegEnd) ++CurArgReg;
374        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
375      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
376        // FP value is passed in an integer register.
377        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
378        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
379        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
380
381        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
382        ArgValues.push_back(Arg);
383      } else {
384        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
385        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
386        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
387        ArgValues.push_back(Load);
388      }
389      ArgOffset += 4;
390      break;
391
392    case MVT::i64:
393    case MVT::f64:
394      if (I->use_empty()) {                // Argument is dead.
395        if (CurArgReg < ArgRegEnd) ++CurArgReg;
396        if (CurArgReg < ArgRegEnd) ++CurArgReg;
397        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
398      } else if (/* FIXME: Apparently this isn't safe?? */
399                 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
400                 ((CurArgReg-ArgRegs) & 1) == 0) {
401        // If this is a double argument and the whole thing lives on the stack,
402        // and the argument is aligned, load the double straight from the stack.
403        // We can't do a load in cases like void foo([6ints], int,double),
404        // because the double wouldn't be aligned!
405        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
406        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
407        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
408      } else {
409        SDOperand HiVal;
410        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
411          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
412          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
413          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
414        } else {
415          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
416          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
417          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
418        }
419
420        SDOperand LoVal;
421        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
422          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
423          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
424          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
425        } else {
426          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
427          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
428          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
429        }
430
431        // Compose the two halves together into an i64 unit.
432        SDOperand WholeValue =
433          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
434
435        // If we want a double, do a bit convert.
436        if (ObjectVT == MVT::f64)
437          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
438
439        ArgValues.push_back(WholeValue);
440      }
441      ArgOffset += 8;
442      break;
443    }
444  }
445
446  // Store remaining ArgRegs to the stack if this is a varargs function.
447  if (F.getFunctionType()->isVarArg()) {
448    // Remember the vararg offset for the va_start implementation.
449    VarArgsFrameOffset = ArgOffset;
450
451    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
452      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
453      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
454      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
455
456      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
457      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
458
459      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
460      ArgOffset += 4;
461    }
462  }
463
464  if (!OutChains.empty())
465    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
466                            &OutChains[0], OutChains.size()));
467
468  // Finally, inform the code generator which regs we return values in.
469  switch (getValueType(F.getReturnType())) {
470  default: assert(0 && "Unknown type!");
471  case MVT::isVoid: break;
472  case MVT::i1:
473  case MVT::i8:
474  case MVT::i16:
475  case MVT::i32:
476    MF.getRegInfo().addLiveOut(SP::I0);
477    break;
478  case MVT::i64:
479    MF.getRegInfo().addLiveOut(SP::I0);
480    MF.getRegInfo().addLiveOut(SP::I1);
481    break;
482  case MVT::f32:
483    MF.getRegInfo().addLiveOut(SP::F0);
484    break;
485  case MVT::f64:
486    MF.getRegInfo().addLiveOut(SP::D0);
487    break;
488  }
489
490  return ArgValues;
491}
492
493std::pair<SDOperand, SDOperand>
494SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
495                                 bool RetSExt, bool RetZExt, bool isVarArg,
496                                 unsigned CC, bool isTailCall, SDOperand Callee,
497                                 ArgListTy &Args, SelectionDAG &DAG) {
498  // Count the size of the outgoing arguments.
499  unsigned ArgsSize = 0;
500  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
501    switch (getValueType(Args[i].Ty)) {
502    default: assert(0 && "Unknown value type!");
503    case MVT::i1:
504    case MVT::i8:
505    case MVT::i16:
506    case MVT::i32:
507    case MVT::f32:
508      ArgsSize += 4;
509      break;
510    case MVT::i64:
511    case MVT::f64:
512      ArgsSize += 8;
513      break;
514    }
515  }
516  if (ArgsSize > 4*6)
517    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
518  else
519    ArgsSize = 0;
520
521  // Keep stack frames 8-byte aligned.
522  ArgsSize = (ArgsSize+7) & ~7;
523
524  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
525
526  SDOperand StackPtr;
527  std::vector<SDOperand> Stores;
528  std::vector<SDOperand> RegValuesToPass;
529  unsigned ArgOffset = 68;
530  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
531    SDOperand Val = Args[i].Node;
532    MVT::ValueType ObjectVT = Val.getValueType();
533    SDOperand ValToStore(0, 0);
534    unsigned ObjSize;
535    switch (ObjectVT) {
536    default: assert(0 && "Unhandled argument type!");
537    case MVT::i1:
538    case MVT::i8:
539    case MVT::i16: {
540      // Promote the integer to 32-bits.  If the input type is signed, use a
541      // sign extend, otherwise use a zero extend.
542      ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
543      if (Args[i].isSExt)
544        ExtendKind = ISD::SIGN_EXTEND;
545      else if (Args[i].isZExt)
546        ExtendKind = ISD::ZERO_EXTEND;
547      Val = DAG.getNode(ExtendKind, MVT::i32, Val);
548      // FALL THROUGH
549    }
550    case MVT::i32:
551      ObjSize = 4;
552
553      if (RegValuesToPass.size() >= 6) {
554        ValToStore = Val;
555      } else {
556        RegValuesToPass.push_back(Val);
557      }
558      break;
559    case MVT::f32:
560      ObjSize = 4;
561      if (RegValuesToPass.size() >= 6) {
562        ValToStore = Val;
563      } else {
564        // Convert this to a FP value in an int reg.
565        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
566        RegValuesToPass.push_back(Val);
567      }
568      break;
569    case MVT::f64:
570      ObjSize = 8;
571      // If we can store this directly into the outgoing slot, do so.  We can
572      // do this when all ArgRegs are used and if the outgoing slot is aligned.
573      // FIXME: McGill/misr fails with this.
574      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
575        ValToStore = Val;
576        break;
577      }
578
579      // Otherwise, convert this to a FP value in int regs.
580      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
581      // FALL THROUGH
582    case MVT::i64:
583      ObjSize = 8;
584      if (RegValuesToPass.size() >= 6) {
585        ValToStore = Val;    // Whole thing is passed in memory.
586        break;
587      }
588
589      // Split the value into top and bottom part.  Top part goes in a reg.
590      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
591                                 DAG.getConstant(1, MVT::i32));
592      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
593                                 DAG.getConstant(0, MVT::i32));
594      RegValuesToPass.push_back(Hi);
595
596      if (RegValuesToPass.size() >= 6) {
597        ValToStore = Lo;
598        ArgOffset += 4;
599        ObjSize = 4;
600      } else {
601        RegValuesToPass.push_back(Lo);
602      }
603      break;
604    }
605
606    if (ValToStore.Val) {
607      if (!StackPtr.Val) {
608        StackPtr = DAG.getRegister(SP::O6, MVT::i32);
609      }
610      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
611      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
612      Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
613    }
614    ArgOffset += ObjSize;
615  }
616
617  // Emit all stores, make sure the occur before any copies into physregs.
618  if (!Stores.empty())
619    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
620
621  static const unsigned ArgRegs[] = {
622    SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
623  };
624
625  // Build a sequence of copy-to-reg nodes chained together with token chain
626  // and flag operands which copy the outgoing args into O[0-5].
627  SDOperand InFlag;
628  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
629    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
630    InFlag = Chain.getValue(1);
631  }
632
633  // If the callee is a GlobalAddress node (quite common, every direct call is)
634  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
635  // Likewise ExternalSymbol -> TargetExternalSymbol.
636  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
637    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
638  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
639    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
640
641  std::vector<MVT::ValueType> NodeTys;
642  NodeTys.push_back(MVT::Other);   // Returns a chain
643  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
644  SDOperand Ops[] = { Chain, Callee, InFlag };
645  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
646  InFlag = Chain.getValue(1);
647
648  MVT::ValueType RetTyVT = getValueType(RetTy);
649  SDOperand RetVal;
650  if (RetTyVT != MVT::isVoid) {
651    switch (RetTyVT) {
652    default: assert(0 && "Unknown value type to return!");
653    case MVT::i1:
654    case MVT::i8:
655    case MVT::i16: {
656      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
657      Chain = RetVal.getValue(1);
658
659      // Add a note to keep track of whether it is sign or zero extended.
660      ISD::NodeType AssertKind = ISD::DELETED_NODE;
661      if (RetSExt)
662        AssertKind = ISD::AssertSext;
663      else if (RetZExt)
664        AssertKind = ISD::AssertZext;
665
666      if (AssertKind != ISD::DELETED_NODE)
667        RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
668                             DAG.getValueType(RetTyVT));
669
670      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
671      break;
672    }
673    case MVT::i32:
674      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
675      Chain = RetVal.getValue(1);
676      break;
677    case MVT::f32:
678      RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
679      Chain = RetVal.getValue(1);
680      break;
681    case MVT::f64:
682      RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
683      Chain = RetVal.getValue(1);
684      break;
685    case MVT::i64:
686      SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
687      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
688                                        Lo.getValue(2));
689      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
690      Chain = Hi.getValue(1);
691      break;
692    }
693  }
694
695  Chain = DAG.getCALLSEQ_END(Chain,
696                             DAG.getConstant(ArgsSize, getPointerTy()),
697                             DAG.getConstant(0, getPointerTy()),
698                             SDOperand());
699  return std::make_pair(RetVal, Chain);
700}
701
702// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
703// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
704static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
705                             ISD::CondCode CC, unsigned &SPCC) {
706  if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
707      CC == ISD::SETNE &&
708      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
709        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
710       (LHS.getOpcode() == SPISD::SELECT_FCC &&
711        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
712      isa<ConstantSDNode>(LHS.getOperand(0)) &&
713      isa<ConstantSDNode>(LHS.getOperand(1)) &&
714      cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
715      cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
716    SDOperand CMPCC = LHS.getOperand(3);
717    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
718    LHS = CMPCC.getOperand(0);
719    RHS = CMPCC.getOperand(1);
720  }
721}
722
723
724SDOperand SparcTargetLowering::
725LowerOperation(SDOperand Op, SelectionDAG &DAG) {
726  switch (Op.getOpcode()) {
727  default: assert(0 && "Should not custom lower this!");
728  case ISD::GlobalTLSAddress:
729    assert(0 && "TLS not implemented for Sparc.");
730  case ISD::GlobalAddress: {
731    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
732    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
733    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
734    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
735    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
736  }
737  case ISD::ConstantPool: {
738    Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
739    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
740                                  cast<ConstantPoolSDNode>(Op)->getAlignment());
741    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
742    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
743    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
744  }
745  case ISD::FP_TO_SINT:
746    // Convert the fp value to integer in an FP register.
747    assert(Op.getValueType() == MVT::i32);
748    Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
749    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
750  case ISD::SINT_TO_FP: {
751    assert(Op.getOperand(0).getValueType() == MVT::i32);
752    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
753    // Convert the int value to FP in an FP register.
754    return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
755  }
756  case ISD::BR_CC: {
757    SDOperand Chain = Op.getOperand(0);
758    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
759    SDOperand LHS = Op.getOperand(2);
760    SDOperand RHS = Op.getOperand(3);
761    SDOperand Dest = Op.getOperand(4);
762    unsigned Opc, SPCC = ~0U;
763
764    // If this is a br_cc of a "setcc", and if the setcc got lowered into
765    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
766    LookThroughSetCC(LHS, RHS, CC, SPCC);
767
768    // Get the condition flag.
769    SDOperand CompareFlag;
770    if (LHS.getValueType() == MVT::i32) {
771      std::vector<MVT::ValueType> VTs;
772      VTs.push_back(MVT::i32);
773      VTs.push_back(MVT::Flag);
774      SDOperand Ops[2] = { LHS, RHS };
775      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
776      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
777      Opc = SPISD::BRICC;
778    } else {
779      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
780      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
781      Opc = SPISD::BRFCC;
782    }
783    return DAG.getNode(Opc, MVT::Other, Chain, Dest,
784                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
785  }
786  case ISD::SELECT_CC: {
787    SDOperand LHS = Op.getOperand(0);
788    SDOperand RHS = Op.getOperand(1);
789    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
790    SDOperand TrueVal = Op.getOperand(2);
791    SDOperand FalseVal = Op.getOperand(3);
792    unsigned Opc, SPCC = ~0U;
793
794    // If this is a select_cc of a "setcc", and if the setcc got lowered into
795    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
796    LookThroughSetCC(LHS, RHS, CC, SPCC);
797
798    SDOperand CompareFlag;
799    if (LHS.getValueType() == MVT::i32) {
800      std::vector<MVT::ValueType> VTs;
801      VTs.push_back(LHS.getValueType());   // subcc returns a value
802      VTs.push_back(MVT::Flag);
803      SDOperand Ops[2] = { LHS, RHS };
804      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
805      Opc = SPISD::SELECT_ICC;
806      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
807    } else {
808      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
809      Opc = SPISD::SELECT_FCC;
810      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
811    }
812    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
813                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
814  }
815  case ISD::VASTART: {
816    // vastart just stores the address of the VarArgsFrameIndex slot into the
817    // memory location argument.
818    SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
819                                   DAG.getRegister(SP::I6, MVT::i32),
820                                DAG.getConstant(VarArgsFrameOffset, MVT::i32));
821    const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
822    return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
823  }
824  case ISD::VAARG: {
825    SDNode *Node = Op.Val;
826    MVT::ValueType VT = Node->getValueType(0);
827    SDOperand InChain = Node->getOperand(0);
828    SDOperand VAListPtr = Node->getOperand(1);
829    const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
830    SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0);
831    // Increment the pointer, VAList, to the next vaarg
832    SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
833                                    DAG.getConstant(MVT::getSizeInBits(VT)/8,
834                                                    getPointerTy()));
835    // Store the incremented VAList to the legalized pointer
836    InChain = DAG.getStore(VAList.getValue(1), NextPtr,
837                           VAListPtr, SV, 0);
838    // Load the actual argument out of the pointer VAList, unless this is an
839    // f64 load.
840    if (VT != MVT::f64) {
841      return DAG.getLoad(VT, InChain, VAList, NULL, 0);
842    } else {
843      // Otherwise, load it as i64, then do a bitconvert.
844      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
845      std::vector<MVT::ValueType> Tys;
846      Tys.push_back(MVT::f64);
847      Tys.push_back(MVT::Other);
848      // Bit-Convert the value to f64.
849      SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
850                           V.getValue(1) };
851      return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
852    }
853  }
854  case ISD::DYNAMIC_STACKALLOC: {
855    SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
856    SDOperand Size  = Op.getOperand(1);  // Legalize the size.
857
858    unsigned SPReg = SP::O6;
859    SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
860    SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
861    Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
862
863    // The resultant pointer is actually 16 words from the bottom of the stack,
864    // to provide a register spill area.
865    SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
866                                   DAG.getConstant(96, MVT::i32));
867    std::vector<MVT::ValueType> Tys;
868    Tys.push_back(MVT::i32);
869    Tys.push_back(MVT::Other);
870    SDOperand Ops[2] = { NewVal, Chain };
871    return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
872  }
873  case ISD::RET: {
874    SDOperand Copy;
875
876    switch(Op.getNumOperands()) {
877    default:
878      assert(0 && "Do not know how to return this many arguments!");
879      abort();
880    case 1:
881      return SDOperand(); // ret void is legal
882    case 3: {
883      unsigned ArgReg;
884      switch(Op.getOperand(1).getValueType()) {
885      default: assert(0 && "Unknown type to return!");
886      case MVT::i32: ArgReg = SP::I0; break;
887      case MVT::f32: ArgReg = SP::F0; break;
888      case MVT::f64: ArgReg = SP::D0; break;
889      }
890      Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
891                              SDOperand());
892      break;
893    }
894    case 5:
895      Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
896                              SDOperand());
897      Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
898      break;
899    }
900    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
901  }
902  // Frame & Return address.  Currently unimplemented
903  case ISD::RETURNADDR:         break;
904  case ISD::FRAMEADDR:          break;
905  }
906  return SDOperand();
907}
908
909MachineBasicBlock *
910SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
911                                                 MachineBasicBlock *BB) {
912  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
913  unsigned BROpcode;
914  unsigned CC;
915  // Figure out the conditional branch opcode to use for this select_cc.
916  switch (MI->getOpcode()) {
917  default: assert(0 && "Unknown SELECT_CC!");
918  case SP::SELECT_CC_Int_ICC:
919  case SP::SELECT_CC_FP_ICC:
920  case SP::SELECT_CC_DFP_ICC:
921    BROpcode = SP::BCOND;
922    break;
923  case SP::SELECT_CC_Int_FCC:
924  case SP::SELECT_CC_FP_FCC:
925  case SP::SELECT_CC_DFP_FCC:
926    BROpcode = SP::FBCOND;
927    break;
928  }
929
930  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
931
932  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
933  // control-flow pattern.  The incoming instruction knows the destination vreg
934  // to set, the condition code register to branch on, the true/false values to
935  // select between, and a branch opcode to use.
936  const BasicBlock *LLVM_BB = BB->getBasicBlock();
937  ilist<MachineBasicBlock>::iterator It = BB;
938  ++It;
939
940  //  thisMBB:
941  //  ...
942  //   TrueVal = ...
943  //   [f]bCC copy1MBB
944  //   fallthrough --> copy0MBB
945  MachineBasicBlock *thisMBB = BB;
946  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
947  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
948  BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
949  MachineFunction *F = BB->getParent();
950  F->getBasicBlockList().insert(It, copy0MBB);
951  F->getBasicBlockList().insert(It, sinkMBB);
952  // Update machine-CFG edges by first adding all successors of the current
953  // block to the new block which will contain the Phi node for the select.
954  for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
955      e = BB->succ_end(); i != e; ++i)
956    sinkMBB->addSuccessor(*i);
957  // Next, remove all successors of the current block, and add the true
958  // and fallthrough blocks as its successors.
959  while(!BB->succ_empty())
960    BB->removeSuccessor(BB->succ_begin());
961  BB->addSuccessor(copy0MBB);
962  BB->addSuccessor(sinkMBB);
963
964  //  copy0MBB:
965  //   %FalseValue = ...
966  //   # fallthrough to sinkMBB
967  BB = copy0MBB;
968
969  // Update machine-CFG edges
970  BB->addSuccessor(sinkMBB);
971
972  //  sinkMBB:
973  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
974  //  ...
975  BB = sinkMBB;
976  BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
977    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
978    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
979
980  delete MI;   // The pseudo instruction is gone now.
981  return BB;
982}
983
984//===----------------------------------------------------------------------===//
985// Instruction Selector Implementation
986//===----------------------------------------------------------------------===//
987
988//===--------------------------------------------------------------------===//
989/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
990/// instructions for SelectionDAG operations.
991///
992namespace {
993class SparcDAGToDAGISel : public SelectionDAGISel {
994  SparcTargetLowering Lowering;
995
996  /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
997  /// make the right decision when generating code for different targets.
998  const SparcSubtarget &Subtarget;
999public:
1000  SparcDAGToDAGISel(TargetMachine &TM)
1001    : SelectionDAGISel(Lowering), Lowering(TM),
1002      Subtarget(TM.getSubtarget<SparcSubtarget>()) {
1003  }
1004
1005  SDNode *Select(SDOperand Op);
1006
1007  // Complex Pattern Selectors.
1008  bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
1009  bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
1010                    SDOperand &Offset);
1011
1012  /// InstructionSelectBasicBlock - This callback is invoked by
1013  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1014  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
1015
1016  virtual const char *getPassName() const {
1017    return "SPARC DAG->DAG Pattern Instruction Selection";
1018  }
1019
1020  // Include the pieces autogenerated from the target description.
1021#include "SparcGenDAGISel.inc"
1022};
1023}  // end anonymous namespace
1024
1025/// InstructionSelectBasicBlock - This callback is invoked by
1026/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1027void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
1028  DEBUG(BB->dump());
1029
1030  // Select target instructions for the DAG.
1031  DAG.setRoot(SelectRoot(DAG.getRoot()));
1032  DAG.RemoveDeadNodes();
1033
1034  // Emit machine code to BB.
1035  ScheduleAndEmitDAG(DAG);
1036}
1037
1038bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1039                                     SDOperand &Base, SDOperand &Offset) {
1040  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1041    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1042    Offset = CurDAG->getTargetConstant(0, MVT::i32);
1043    return true;
1044  }
1045  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1046      Addr.getOpcode() == ISD::TargetGlobalAddress)
1047    return false;  // direct calls.
1048
1049  if (Addr.getOpcode() == ISD::ADD) {
1050    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1051      if (Predicate_simm13(CN)) {
1052        if (FrameIndexSDNode *FIN =
1053                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1054          // Constant offset from frame ref.
1055          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1056        } else {
1057          Base = Addr.getOperand(0);
1058        }
1059        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1060        return true;
1061      }
1062    }
1063    if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1064      Base = Addr.getOperand(1);
1065      Offset = Addr.getOperand(0).getOperand(0);
1066      return true;
1067    }
1068    if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1069      Base = Addr.getOperand(0);
1070      Offset = Addr.getOperand(1).getOperand(0);
1071      return true;
1072    }
1073  }
1074  Base = Addr;
1075  Offset = CurDAG->getTargetConstant(0, MVT::i32);
1076  return true;
1077}
1078
1079bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1080                                     SDOperand &R1,  SDOperand &R2) {
1081  if (Addr.getOpcode() == ISD::FrameIndex) return false;
1082  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1083      Addr.getOpcode() == ISD::TargetGlobalAddress)
1084    return false;  // direct calls.
1085
1086  if (Addr.getOpcode() == ISD::ADD) {
1087    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1088        Predicate_simm13(Addr.getOperand(1).Val))
1089      return false;  // Let the reg+imm pattern catch this!
1090    if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1091        Addr.getOperand(1).getOpcode() == SPISD::Lo)
1092      return false;  // Let the reg+imm pattern catch this!
1093    R1 = Addr.getOperand(0);
1094    R2 = Addr.getOperand(1);
1095    return true;
1096  }
1097
1098  R1 = Addr;
1099  R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1100  return true;
1101}
1102
1103SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1104  SDNode *N = Op.Val;
1105  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1106      N->getOpcode() < SPISD::FIRST_NUMBER)
1107    return NULL;   // Already selected.
1108
1109  switch (N->getOpcode()) {
1110  default: break;
1111  case ISD::SDIV:
1112  case ISD::UDIV: {
1113    // FIXME: should use a custom expander to expose the SRA to the dag.
1114    SDOperand DivLHS = N->getOperand(0);
1115    SDOperand DivRHS = N->getOperand(1);
1116    AddToISelQueue(DivLHS);
1117    AddToISelQueue(DivRHS);
1118
1119    // Set the Y register to the high-part.
1120    SDOperand TopPart;
1121    if (N->getOpcode() == ISD::SDIV) {
1122      TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1123                                   CurDAG->getTargetConstant(31, MVT::i32)), 0);
1124    } else {
1125      TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1126    }
1127    TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1128                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1129
1130    // FIXME: Handle div by immediate.
1131    unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1132    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1133                                TopPart);
1134  }
1135  case ISD::MULHU:
1136  case ISD::MULHS: {
1137    // FIXME: Handle mul by immediate.
1138    SDOperand MulLHS = N->getOperand(0);
1139    SDOperand MulRHS = N->getOperand(1);
1140    AddToISelQueue(MulLHS);
1141    AddToISelQueue(MulRHS);
1142    unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1143    SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1144                                        MulLHS, MulRHS);
1145    // The high part is in the Y register.
1146    return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1147    return NULL;
1148  }
1149  }
1150
1151  return SelectCode(Op);
1152}
1153
1154
1155/// createSparcISelDag - This pass converts a legalized DAG into a
1156/// SPARC-specific DAG, ready for instruction scheduling.
1157///
1158FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1159  return new SparcDAGToDAGISel(TM);
1160}
1161