SparcISelDAGToDAG.cpp revision 334dc1f58d617dcff969a2e107febaae42bbc883
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/CodeGen/SelectionDAGISel.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Debug.h" 27#include <queue> 28#include <set> 29using namespace llvm; 30 31//===----------------------------------------------------------------------===// 32// TargetLowering Implementation 33//===----------------------------------------------------------------------===// 34 35namespace SPISD { 36 enum { 37 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 38 CMPICC, // Compare two GPR operands, set icc. 39 CMPFCC, // Compare two FP operands, set fcc. 40 BRICC, // Branch to dest on icc condition 41 BRFCC, // Branch to dest on fcc condition 42 SELECT_ICC, // Select between two values using the current ICC flags. 43 SELECT_FCC, // Select between two values using the current FCC flags. 44 45 Hi, Lo, // Hi/Lo operations, typically on a global address. 46 47 FTOI, // FP to Int within a FP register. 48 ITOF, // Int to FP within a FP register. 49 50 CALL, // A call instruction. 51 RET_FLAG // Return with a flag operand. 52 }; 53} 54 55/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 56/// condition. 57static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 58 switch (CC) { 59 default: assert(0 && "Unknown integer condition code!"); 60 case ISD::SETEQ: return SPCC::ICC_E; 61 case ISD::SETNE: return SPCC::ICC_NE; 62 case ISD::SETLT: return SPCC::ICC_L; 63 case ISD::SETGT: return SPCC::ICC_G; 64 case ISD::SETLE: return SPCC::ICC_LE; 65 case ISD::SETGE: return SPCC::ICC_GE; 66 case ISD::SETULT: return SPCC::ICC_CS; 67 case ISD::SETULE: return SPCC::ICC_LEU; 68 case ISD::SETUGT: return SPCC::ICC_GU; 69 case ISD::SETUGE: return SPCC::ICC_CC; 70 } 71} 72 73/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 74/// FCC condition. 75static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 76 switch (CC) { 77 default: assert(0 && "Unknown fp condition code!"); 78 case ISD::SETEQ: 79 case ISD::SETOEQ: return SPCC::FCC_E; 80 case ISD::SETNE: 81 case ISD::SETUNE: return SPCC::FCC_NE; 82 case ISD::SETLT: 83 case ISD::SETOLT: return SPCC::FCC_L; 84 case ISD::SETGT: 85 case ISD::SETOGT: return SPCC::FCC_G; 86 case ISD::SETLE: 87 case ISD::SETOLE: return SPCC::FCC_LE; 88 case ISD::SETGE: 89 case ISD::SETOGE: return SPCC::FCC_GE; 90 case ISD::SETULT: return SPCC::FCC_UL; 91 case ISD::SETULE: return SPCC::FCC_ULE; 92 case ISD::SETUGT: return SPCC::FCC_UG; 93 case ISD::SETUGE: return SPCC::FCC_UGE; 94 case ISD::SETUO: return SPCC::FCC_U; 95 case ISD::SETO: return SPCC::FCC_O; 96 case ISD::SETONE: return SPCC::FCC_LG; 97 case ISD::SETUEQ: return SPCC::FCC_UE; 98 } 99} 100 101namespace { 102 class SparcTargetLowering : public TargetLowering { 103 int VarArgsFrameOffset; // Frame offset to start of varargs area. 104 public: 105 SparcTargetLowering(TargetMachine &TM); 106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 107 108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 109 /// in Mask are known to be either zero or one and return them in the 110 /// KnownZero/KnownOne bitsets. 111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 112 uint64_t Mask, 113 uint64_t &KnownZero, 114 uint64_t &KnownOne, 115 const SelectionDAG &DAG, 116 unsigned Depth = 0) const; 117 118 virtual std::vector<SDOperand> 119 LowerArguments(Function &F, SelectionDAG &DAG); 120 virtual std::pair<SDOperand, SDOperand> 121 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 122 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 123 ArgListTy &Args, SelectionDAG &DAG); 124 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 125 MachineBasicBlock *MBB); 126 127 virtual const char *getTargetNodeName(unsigned Opcode) const; 128 }; 129} 130 131SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 132 : TargetLowering(TM) { 133 134 // Set up the register classes. 135 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 136 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 137 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 138 139 // Turn FP extload into load/fextend 140 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 141 142 // Sparc doesn't have i1 sign extending load 143 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 144 145 // Custom legalize GlobalAddress nodes into LO/HI parts. 146 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 147 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 148 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 149 150 // Sparc doesn't have sext_inreg, replace them with shl/sra 151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 154 155 // Sparc has no REM or DIVREM operations. 156 setOperationAction(ISD::UREM, MVT::i32, Expand); 157 setOperationAction(ISD::SREM, MVT::i32, Expand); 158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 159 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 160 161 // Custom expand fp<->sint 162 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 163 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 164 165 // Expand fp<->uint 166 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 167 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 168 169 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 170 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 171 172 // Sparc has no select or setcc: expand to SELECT_CC. 173 setOperationAction(ISD::SELECT, MVT::i32, Expand); 174 setOperationAction(ISD::SELECT, MVT::f32, Expand); 175 setOperationAction(ISD::SELECT, MVT::f64, Expand); 176 setOperationAction(ISD::SETCC, MVT::i32, Expand); 177 setOperationAction(ISD::SETCC, MVT::f32, Expand); 178 setOperationAction(ISD::SETCC, MVT::f64, Expand); 179 180 // Sparc doesn't have BRCOND either, it has BR_CC. 181 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 182 setOperationAction(ISD::BRIND, MVT::Other, Expand); 183 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 184 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 185 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 186 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 187 188 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 189 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 190 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 191 192 // SPARC has no intrinsics for these particular operations. 193 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 194 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 195 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 196 197 setOperationAction(ISD::FSIN , MVT::f64, Expand); 198 setOperationAction(ISD::FCOS , MVT::f64, Expand); 199 setOperationAction(ISD::FREM , MVT::f64, Expand); 200 setOperationAction(ISD::FSIN , MVT::f32, Expand); 201 setOperationAction(ISD::FCOS , MVT::f32, Expand); 202 setOperationAction(ISD::FREM , MVT::f32, Expand); 203 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 204 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 205 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 206 setOperationAction(ISD::ROTL , MVT::i32, Expand); 207 setOperationAction(ISD::ROTR , MVT::i32, Expand); 208 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 209 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 210 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 211 setOperationAction(ISD::FPOW , MVT::f64, Expand); 212 setOperationAction(ISD::FPOW , MVT::f32, Expand); 213 214 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 215 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 216 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 217 218 // We don't have line number support yet. 219 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 220 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 221 setOperationAction(ISD::LABEL, MVT::Other, Expand); 222 223 // RET must be custom lowered, to meet ABI requirements 224 setOperationAction(ISD::RET , MVT::Other, Custom); 225 226 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 227 setOperationAction(ISD::VASTART , MVT::Other, Custom); 228 // VAARG needs to be lowered to not do unaligned accesses for doubles. 229 setOperationAction(ISD::VAARG , MVT::Other, Custom); 230 231 // Use the default implementation. 232 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 233 setOperationAction(ISD::VAEND , MVT::Other, Expand); 234 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 235 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 236 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 237 238 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 239 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 240 241 setStackPointerRegisterToSaveRestore(SP::O6); 242 243 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 244 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 245 } 246 247 computeRegisterProperties(); 248} 249 250const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 251 switch (Opcode) { 252 default: return 0; 253 case SPISD::CMPICC: return "SPISD::CMPICC"; 254 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 255 case SPISD::BRICC: return "SPISD::BRICC"; 256 case SPISD::BRFCC: return "SPISD::BRFCC"; 257 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 258 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 259 case SPISD::Hi: return "SPISD::Hi"; 260 case SPISD::Lo: return "SPISD::Lo"; 261 case SPISD::FTOI: return "SPISD::FTOI"; 262 case SPISD::ITOF: return "SPISD::ITOF"; 263 case SPISD::CALL: return "SPISD::CALL"; 264 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 265 } 266} 267 268/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 269/// be zero. Op is expected to be a target specific node. Used by DAG 270/// combiner. 271void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 272 uint64_t Mask, 273 uint64_t &KnownZero, 274 uint64_t &KnownOne, 275 const SelectionDAG &DAG, 276 unsigned Depth) const { 277 uint64_t KnownZero2, KnownOne2; 278 KnownZero = KnownOne = 0; // Don't know anything. 279 280 switch (Op.getOpcode()) { 281 default: break; 282 case SPISD::SELECT_ICC: 283 case SPISD::SELECT_FCC: 284 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 285 Depth+1); 286 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 287 Depth+1); 288 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 289 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 290 291 // Only known if known in both the LHS and RHS. 292 KnownOne &= KnownOne2; 293 KnownZero &= KnownZero2; 294 break; 295 } 296} 297 298/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 299/// either one or two GPRs, including FP values. TODO: we should pass FP values 300/// in FP registers for fastcc functions. 301std::vector<SDOperand> 302SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 303 MachineFunction &MF = DAG.getMachineFunction(); 304 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 305 std::vector<SDOperand> ArgValues; 306 307 static const unsigned ArgRegs[] = { 308 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 309 }; 310 311 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 312 unsigned ArgOffset = 68; 313 314 SDOperand Root = DAG.getRoot(); 315 std::vector<SDOperand> OutChains; 316 317 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 318 MVT::ValueType ObjectVT = getValueType(I->getType()); 319 320 switch (ObjectVT) { 321 default: assert(0 && "Unhandled argument type!"); 322 case MVT::i1: 323 case MVT::i8: 324 case MVT::i16: 325 case MVT::i32: 326 if (I->use_empty()) { // Argument is dead. 327 if (CurArgReg < ArgRegEnd) ++CurArgReg; 328 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 329 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 330 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 331 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 332 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 333 if (ObjectVT != MVT::i32) { 334 unsigned AssertOp = ISD::AssertSext; 335 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 336 DAG.getValueType(ObjectVT)); 337 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 338 } 339 ArgValues.push_back(Arg); 340 } else { 341 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 342 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 343 SDOperand Load; 344 if (ObjectVT == MVT::i32) { 345 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 346 } else { 347 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 348 349 // Sparc is big endian, so add an offset based on the ObjectVT. 350 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 351 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 352 DAG.getConstant(Offset, MVT::i32)); 353 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 354 NULL, 0, ObjectVT); 355 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 356 } 357 ArgValues.push_back(Load); 358 } 359 360 ArgOffset += 4; 361 break; 362 case MVT::f32: 363 if (I->use_empty()) { // Argument is dead. 364 if (CurArgReg < ArgRegEnd) ++CurArgReg; 365 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 366 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 367 // FP value is passed in an integer register. 368 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 369 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 370 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 371 372 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 373 ArgValues.push_back(Arg); 374 } else { 375 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 376 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 377 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 378 ArgValues.push_back(Load); 379 } 380 ArgOffset += 4; 381 break; 382 383 case MVT::i64: 384 case MVT::f64: 385 if (I->use_empty()) { // Argument is dead. 386 if (CurArgReg < ArgRegEnd) ++CurArgReg; 387 if (CurArgReg < ArgRegEnd) ++CurArgReg; 388 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 389 } else if (/* FIXME: Apparently this isn't safe?? */ 390 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 391 ((CurArgReg-ArgRegs) & 1) == 0) { 392 // If this is a double argument and the whole thing lives on the stack, 393 // and the argument is aligned, load the double straight from the stack. 394 // We can't do a load in cases like void foo([6ints], int,double), 395 // because the double wouldn't be aligned! 396 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 397 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 398 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 399 } else { 400 SDOperand HiVal; 401 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 402 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 403 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 404 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 405 } else { 406 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 407 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 408 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 409 } 410 411 SDOperand LoVal; 412 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 413 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 414 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 415 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 416 } else { 417 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 418 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 419 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 420 } 421 422 // Compose the two halves together into an i64 unit. 423 SDOperand WholeValue = 424 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 425 426 // If we want a double, do a bit convert. 427 if (ObjectVT == MVT::f64) 428 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 429 430 ArgValues.push_back(WholeValue); 431 } 432 ArgOffset += 8; 433 break; 434 } 435 } 436 437 // Store remaining ArgRegs to the stack if this is a varargs function. 438 if (F.getFunctionType()->isVarArg()) { 439 // Remember the vararg offset for the va_start implementation. 440 VarArgsFrameOffset = ArgOffset; 441 442 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 443 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 444 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 445 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 446 447 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 448 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 449 450 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 451 ArgOffset += 4; 452 } 453 } 454 455 if (!OutChains.empty()) 456 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 457 &OutChains[0], OutChains.size())); 458 459 // Finally, inform the code generator which regs we return values in. 460 switch (getValueType(F.getReturnType())) { 461 default: assert(0 && "Unknown type!"); 462 case MVT::isVoid: break; 463 case MVT::i1: 464 case MVT::i8: 465 case MVT::i16: 466 case MVT::i32: 467 MF.getRegInfo().addLiveOut(SP::I0); 468 break; 469 case MVT::i64: 470 MF.getRegInfo().addLiveOut(SP::I0); 471 MF.getRegInfo().addLiveOut(SP::I1); 472 break; 473 case MVT::f32: 474 MF.getRegInfo().addLiveOut(SP::F0); 475 break; 476 case MVT::f64: 477 MF.getRegInfo().addLiveOut(SP::D0); 478 break; 479 } 480 481 return ArgValues; 482} 483 484std::pair<SDOperand, SDOperand> 485SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 486 bool RetTyIsSigned, bool isVarArg, unsigned CC, 487 bool isTailCall, SDOperand Callee, 488 ArgListTy &Args, SelectionDAG &DAG) { 489 // Count the size of the outgoing arguments. 490 unsigned ArgsSize = 0; 491 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 492 switch (getValueType(Args[i].Ty)) { 493 default: assert(0 && "Unknown value type!"); 494 case MVT::i1: 495 case MVT::i8: 496 case MVT::i16: 497 case MVT::i32: 498 case MVT::f32: 499 ArgsSize += 4; 500 break; 501 case MVT::i64: 502 case MVT::f64: 503 ArgsSize += 8; 504 break; 505 } 506 } 507 if (ArgsSize > 4*6) 508 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 509 else 510 ArgsSize = 0; 511 512 // Keep stack frames 8-byte aligned. 513 ArgsSize = (ArgsSize+7) & ~7; 514 515 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 516 517 SDOperand StackPtr; 518 std::vector<SDOperand> Stores; 519 std::vector<SDOperand> RegValuesToPass; 520 unsigned ArgOffset = 68; 521 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 522 SDOperand Val = Args[i].Node; 523 MVT::ValueType ObjectVT = Val.getValueType(); 524 SDOperand ValToStore(0, 0); 525 unsigned ObjSize; 526 switch (ObjectVT) { 527 default: assert(0 && "Unhandled argument type!"); 528 case MVT::i1: 529 case MVT::i8: 530 case MVT::i16: { 531 // Promote the integer to 32-bits. If the input type is signed, use a 532 // sign extend, otherwise use a zero extend. 533 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 534 if (Args[i].isSExt) 535 ExtendKind = ISD::SIGN_EXTEND; 536 else if (Args[i].isZExt) 537 ExtendKind = ISD::ZERO_EXTEND; 538 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 539 // FALL THROUGH 540 } 541 case MVT::i32: 542 ObjSize = 4; 543 544 if (RegValuesToPass.size() >= 6) { 545 ValToStore = Val; 546 } else { 547 RegValuesToPass.push_back(Val); 548 } 549 break; 550 case MVT::f32: 551 ObjSize = 4; 552 if (RegValuesToPass.size() >= 6) { 553 ValToStore = Val; 554 } else { 555 // Convert this to a FP value in an int reg. 556 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 557 RegValuesToPass.push_back(Val); 558 } 559 break; 560 case MVT::f64: 561 ObjSize = 8; 562 // If we can store this directly into the outgoing slot, do so. We can 563 // do this when all ArgRegs are used and if the outgoing slot is aligned. 564 // FIXME: McGill/misr fails with this. 565 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 566 ValToStore = Val; 567 break; 568 } 569 570 // Otherwise, convert this to a FP value in int regs. 571 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 572 // FALL THROUGH 573 case MVT::i64: 574 ObjSize = 8; 575 if (RegValuesToPass.size() >= 6) { 576 ValToStore = Val; // Whole thing is passed in memory. 577 break; 578 } 579 580 // Split the value into top and bottom part. Top part goes in a reg. 581 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 582 DAG.getConstant(1, MVT::i32)); 583 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 584 DAG.getConstant(0, MVT::i32)); 585 RegValuesToPass.push_back(Hi); 586 587 if (RegValuesToPass.size() >= 6) { 588 ValToStore = Lo; 589 ArgOffset += 4; 590 ObjSize = 4; 591 } else { 592 RegValuesToPass.push_back(Lo); 593 } 594 break; 595 } 596 597 if (ValToStore.Val) { 598 if (!StackPtr.Val) { 599 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 600 } 601 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 602 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 603 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 604 } 605 ArgOffset += ObjSize; 606 } 607 608 // Emit all stores, make sure the occur before any copies into physregs. 609 if (!Stores.empty()) 610 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 611 612 static const unsigned ArgRegs[] = { 613 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 614 }; 615 616 // Build a sequence of copy-to-reg nodes chained together with token chain 617 // and flag operands which copy the outgoing args into O[0-5]. 618 SDOperand InFlag; 619 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 620 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 621 InFlag = Chain.getValue(1); 622 } 623 624 // If the callee is a GlobalAddress node (quite common, every direct call is) 625 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 626 // Likewise ExternalSymbol -> TargetExternalSymbol. 627 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 628 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 629 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 630 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 631 632 std::vector<MVT::ValueType> NodeTys; 633 NodeTys.push_back(MVT::Other); // Returns a chain 634 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 635 SDOperand Ops[] = { Chain, Callee, InFlag }; 636 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 637 InFlag = Chain.getValue(1); 638 639 MVT::ValueType RetTyVT = getValueType(RetTy); 640 SDOperand RetVal; 641 if (RetTyVT != MVT::isVoid) { 642 switch (RetTyVT) { 643 default: assert(0 && "Unknown value type to return!"); 644 case MVT::i1: 645 case MVT::i8: 646 case MVT::i16: { 647 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 648 Chain = RetVal.getValue(1); 649 650 // Add a note to keep track of whether it is sign or zero extended. 651 ISD::NodeType AssertKind = ISD::AssertZext; 652 if (RetTyIsSigned) 653 AssertKind = ISD::AssertSext; 654 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 655 DAG.getValueType(RetTyVT)); 656 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 657 break; 658 } 659 case MVT::i32: 660 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 661 Chain = RetVal.getValue(1); 662 break; 663 case MVT::f32: 664 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 665 Chain = RetVal.getValue(1); 666 break; 667 case MVT::f64: 668 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 669 Chain = RetVal.getValue(1); 670 break; 671 case MVT::i64: 672 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 673 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 674 Lo.getValue(2)); 675 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 676 Chain = Hi.getValue(1); 677 break; 678 } 679 } 680 681 Chain = DAG.getCALLSEQ_END(Chain, 682 DAG.getConstant(ArgsSize, getPointerTy()), 683 DAG.getConstant(0, getPointerTy()), 684 SDOperand()); 685 return std::make_pair(RetVal, Chain); 686} 687 688// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 689// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 690static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 691 ISD::CondCode CC, unsigned &SPCC) { 692 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 693 CC == ISD::SETNE && 694 ((LHS.getOpcode() == SPISD::SELECT_ICC && 695 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 696 (LHS.getOpcode() == SPISD::SELECT_FCC && 697 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 698 isa<ConstantSDNode>(LHS.getOperand(0)) && 699 isa<ConstantSDNode>(LHS.getOperand(1)) && 700 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 701 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 702 SDOperand CMPCC = LHS.getOperand(3); 703 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 704 LHS = CMPCC.getOperand(0); 705 RHS = CMPCC.getOperand(1); 706 } 707} 708 709 710SDOperand SparcTargetLowering:: 711LowerOperation(SDOperand Op, SelectionDAG &DAG) { 712 switch (Op.getOpcode()) { 713 default: assert(0 && "Should not custom lower this!"); 714 case ISD::GlobalTLSAddress: 715 assert(0 && "TLS not implemented for Sparc."); 716 case ISD::GlobalAddress: { 717 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 718 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 719 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 720 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 721 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 722 } 723 case ISD::ConstantPool: { 724 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 725 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 726 cast<ConstantPoolSDNode>(Op)->getAlignment()); 727 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 728 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 729 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 730 } 731 case ISD::FP_TO_SINT: 732 // Convert the fp value to integer in an FP register. 733 assert(Op.getValueType() == MVT::i32); 734 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 735 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 736 case ISD::SINT_TO_FP: { 737 assert(Op.getOperand(0).getValueType() == MVT::i32); 738 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 739 // Convert the int value to FP in an FP register. 740 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 741 } 742 case ISD::BR_CC: { 743 SDOperand Chain = Op.getOperand(0); 744 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 745 SDOperand LHS = Op.getOperand(2); 746 SDOperand RHS = Op.getOperand(3); 747 SDOperand Dest = Op.getOperand(4); 748 unsigned Opc, SPCC = ~0U; 749 750 // If this is a br_cc of a "setcc", and if the setcc got lowered into 751 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 752 LookThroughSetCC(LHS, RHS, CC, SPCC); 753 754 // Get the condition flag. 755 SDOperand CompareFlag; 756 if (LHS.getValueType() == MVT::i32) { 757 std::vector<MVT::ValueType> VTs; 758 VTs.push_back(MVT::i32); 759 VTs.push_back(MVT::Flag); 760 SDOperand Ops[2] = { LHS, RHS }; 761 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 762 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 763 Opc = SPISD::BRICC; 764 } else { 765 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 766 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 767 Opc = SPISD::BRFCC; 768 } 769 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 770 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 771 } 772 case ISD::SELECT_CC: { 773 SDOperand LHS = Op.getOperand(0); 774 SDOperand RHS = Op.getOperand(1); 775 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 776 SDOperand TrueVal = Op.getOperand(2); 777 SDOperand FalseVal = Op.getOperand(3); 778 unsigned Opc, SPCC = ~0U; 779 780 // If this is a select_cc of a "setcc", and if the setcc got lowered into 781 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 782 LookThroughSetCC(LHS, RHS, CC, SPCC); 783 784 SDOperand CompareFlag; 785 if (LHS.getValueType() == MVT::i32) { 786 std::vector<MVT::ValueType> VTs; 787 VTs.push_back(LHS.getValueType()); // subcc returns a value 788 VTs.push_back(MVT::Flag); 789 SDOperand Ops[2] = { LHS, RHS }; 790 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 791 Opc = SPISD::SELECT_ICC; 792 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 793 } else { 794 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 795 Opc = SPISD::SELECT_FCC; 796 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 797 } 798 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 799 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 800 } 801 case ISD::VASTART: { 802 // vastart just stores the address of the VarArgsFrameIndex slot into the 803 // memory location argument. 804 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 805 DAG.getRegister(SP::I6, MVT::i32), 806 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 807 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 808 return DAG.getStore(Op.getOperand(0), Offset, 809 Op.getOperand(1), SV->getValue(), SV->getOffset()); 810 } 811 case ISD::VAARG: { 812 SDNode *Node = Op.Val; 813 MVT::ValueType VT = Node->getValueType(0); 814 SDOperand InChain = Node->getOperand(0); 815 SDOperand VAListPtr = Node->getOperand(1); 816 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 817 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 818 SV->getValue(), SV->getOffset()); 819 // Increment the pointer, VAList, to the next vaarg 820 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 821 DAG.getConstant(MVT::getSizeInBits(VT)/8, 822 getPointerTy())); 823 // Store the incremented VAList to the legalized pointer 824 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 825 VAListPtr, SV->getValue(), SV->getOffset()); 826 // Load the actual argument out of the pointer VAList, unless this is an 827 // f64 load. 828 if (VT != MVT::f64) { 829 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 830 } else { 831 // Otherwise, load it as i64, then do a bitconvert. 832 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 833 std::vector<MVT::ValueType> Tys; 834 Tys.push_back(MVT::f64); 835 Tys.push_back(MVT::Other); 836 // Bit-Convert the value to f64. 837 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 838 V.getValue(1) }; 839 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 840 } 841 } 842 case ISD::DYNAMIC_STACKALLOC: { 843 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 844 SDOperand Size = Op.getOperand(1); // Legalize the size. 845 846 unsigned SPReg = SP::O6; 847 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 848 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 849 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 850 851 // The resultant pointer is actually 16 words from the bottom of the stack, 852 // to provide a register spill area. 853 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 854 DAG.getConstant(96, MVT::i32)); 855 std::vector<MVT::ValueType> Tys; 856 Tys.push_back(MVT::i32); 857 Tys.push_back(MVT::Other); 858 SDOperand Ops[2] = { NewVal, Chain }; 859 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 860 } 861 case ISD::RET: { 862 SDOperand Copy; 863 864 switch(Op.getNumOperands()) { 865 default: 866 assert(0 && "Do not know how to return this many arguments!"); 867 abort(); 868 case 1: 869 return SDOperand(); // ret void is legal 870 case 3: { 871 unsigned ArgReg; 872 switch(Op.getOperand(1).getValueType()) { 873 default: assert(0 && "Unknown type to return!"); 874 case MVT::i32: ArgReg = SP::I0; break; 875 case MVT::f32: ArgReg = SP::F0; break; 876 case MVT::f64: ArgReg = SP::D0; break; 877 } 878 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 879 SDOperand()); 880 break; 881 } 882 case 5: 883 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 884 SDOperand()); 885 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 886 break; 887 } 888 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 889 } 890 // Frame & Return address. Currently unimplemented 891 case ISD::RETURNADDR: break; 892 case ISD::FRAMEADDR: break; 893 } 894 return SDOperand(); 895} 896 897MachineBasicBlock * 898SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 899 MachineBasicBlock *BB) { 900 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 901 unsigned BROpcode; 902 unsigned CC; 903 // Figure out the conditional branch opcode to use for this select_cc. 904 switch (MI->getOpcode()) { 905 default: assert(0 && "Unknown SELECT_CC!"); 906 case SP::SELECT_CC_Int_ICC: 907 case SP::SELECT_CC_FP_ICC: 908 case SP::SELECT_CC_DFP_ICC: 909 BROpcode = SP::BCOND; 910 break; 911 case SP::SELECT_CC_Int_FCC: 912 case SP::SELECT_CC_FP_FCC: 913 case SP::SELECT_CC_DFP_FCC: 914 BROpcode = SP::FBCOND; 915 break; 916 } 917 918 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 919 920 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 921 // control-flow pattern. The incoming instruction knows the destination vreg 922 // to set, the condition code register to branch on, the true/false values to 923 // select between, and a branch opcode to use. 924 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 925 ilist<MachineBasicBlock>::iterator It = BB; 926 ++It; 927 928 // thisMBB: 929 // ... 930 // TrueVal = ... 931 // [f]bCC copy1MBB 932 // fallthrough --> copy0MBB 933 MachineBasicBlock *thisMBB = BB; 934 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 935 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 936 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 937 MachineFunction *F = BB->getParent(); 938 F->getBasicBlockList().insert(It, copy0MBB); 939 F->getBasicBlockList().insert(It, sinkMBB); 940 // Update machine-CFG edges by first adding all successors of the current 941 // block to the new block which will contain the Phi node for the select. 942 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 943 e = BB->succ_end(); i != e; ++i) 944 sinkMBB->addSuccessor(*i); 945 // Next, remove all successors of the current block, and add the true 946 // and fallthrough blocks as its successors. 947 while(!BB->succ_empty()) 948 BB->removeSuccessor(BB->succ_begin()); 949 BB->addSuccessor(copy0MBB); 950 BB->addSuccessor(sinkMBB); 951 952 // copy0MBB: 953 // %FalseValue = ... 954 // # fallthrough to sinkMBB 955 BB = copy0MBB; 956 957 // Update machine-CFG edges 958 BB->addSuccessor(sinkMBB); 959 960 // sinkMBB: 961 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 962 // ... 963 BB = sinkMBB; 964 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 965 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 966 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 967 968 delete MI; // The pseudo instruction is gone now. 969 return BB; 970} 971 972//===----------------------------------------------------------------------===// 973// Instruction Selector Implementation 974//===----------------------------------------------------------------------===// 975 976//===--------------------------------------------------------------------===// 977/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 978/// instructions for SelectionDAG operations. 979/// 980namespace { 981class SparcDAGToDAGISel : public SelectionDAGISel { 982 SparcTargetLowering Lowering; 983 984 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 985 /// make the right decision when generating code for different targets. 986 const SparcSubtarget &Subtarget; 987public: 988 SparcDAGToDAGISel(TargetMachine &TM) 989 : SelectionDAGISel(Lowering), Lowering(TM), 990 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 991 } 992 993 SDNode *Select(SDOperand Op); 994 995 // Complex Pattern Selectors. 996 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); 997 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, 998 SDOperand &Offset); 999 1000 /// InstructionSelectBasicBlock - This callback is invoked by 1001 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1002 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 1003 1004 virtual const char *getPassName() const { 1005 return "SPARC DAG->DAG Pattern Instruction Selection"; 1006 } 1007 1008 // Include the pieces autogenerated from the target description. 1009#include "SparcGenDAGISel.inc" 1010}; 1011} // end anonymous namespace 1012 1013/// InstructionSelectBasicBlock - This callback is invoked by 1014/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1015void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 1016 DEBUG(BB->dump()); 1017 1018 // Select target instructions for the DAG. 1019 DAG.setRoot(SelectRoot(DAG.getRoot())); 1020 DAG.RemoveDeadNodes(); 1021 1022 // Emit machine code to BB. 1023 ScheduleAndEmitDAG(DAG); 1024} 1025 1026bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, 1027 SDOperand &Base, SDOperand &Offset) { 1028 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1029 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1030 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1031 return true; 1032 } 1033 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1034 Addr.getOpcode() == ISD::TargetGlobalAddress) 1035 return false; // direct calls. 1036 1037 if (Addr.getOpcode() == ISD::ADD) { 1038 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1039 if (Predicate_simm13(CN)) { 1040 if (FrameIndexSDNode *FIN = 1041 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1042 // Constant offset from frame ref. 1043 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1044 } else { 1045 Base = Addr.getOperand(0); 1046 } 1047 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1048 return true; 1049 } 1050 } 1051 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1052 Base = Addr.getOperand(1); 1053 Offset = Addr.getOperand(0).getOperand(0); 1054 return true; 1055 } 1056 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1057 Base = Addr.getOperand(0); 1058 Offset = Addr.getOperand(1).getOperand(0); 1059 return true; 1060 } 1061 } 1062 Base = Addr; 1063 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1064 return true; 1065} 1066 1067bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, 1068 SDOperand &R1, SDOperand &R2) { 1069 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1070 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1071 Addr.getOpcode() == ISD::TargetGlobalAddress) 1072 return false; // direct calls. 1073 1074 if (Addr.getOpcode() == ISD::ADD) { 1075 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1076 Predicate_simm13(Addr.getOperand(1).Val)) 1077 return false; // Let the reg+imm pattern catch this! 1078 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1079 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1080 return false; // Let the reg+imm pattern catch this! 1081 R1 = Addr.getOperand(0); 1082 R2 = Addr.getOperand(1); 1083 return true; 1084 } 1085 1086 R1 = Addr; 1087 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1088 return true; 1089} 1090 1091SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1092 SDNode *N = Op.Val; 1093 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1094 N->getOpcode() < SPISD::FIRST_NUMBER) 1095 return NULL; // Already selected. 1096 1097 switch (N->getOpcode()) { 1098 default: break; 1099 case ISD::SDIV: 1100 case ISD::UDIV: { 1101 // FIXME: should use a custom expander to expose the SRA to the dag. 1102 SDOperand DivLHS = N->getOperand(0); 1103 SDOperand DivRHS = N->getOperand(1); 1104 AddToISelQueue(DivLHS); 1105 AddToISelQueue(DivRHS); 1106 1107 // Set the Y register to the high-part. 1108 SDOperand TopPart; 1109 if (N->getOpcode() == ISD::SDIV) { 1110 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1111 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1112 } else { 1113 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1114 } 1115 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1116 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1117 1118 // FIXME: Handle div by immediate. 1119 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1120 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1121 TopPart); 1122 } 1123 case ISD::MULHU: 1124 case ISD::MULHS: { 1125 // FIXME: Handle mul by immediate. 1126 SDOperand MulLHS = N->getOperand(0); 1127 SDOperand MulRHS = N->getOperand(1); 1128 AddToISelQueue(MulLHS); 1129 AddToISelQueue(MulRHS); 1130 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1131 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1132 MulLHS, MulRHS); 1133 // The high part is in the Y register. 1134 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1135 return NULL; 1136 } 1137 } 1138 1139 return SelectCode(Op); 1140} 1141 1142 1143/// createSparcISelDag - This pass converts a legalized DAG into a 1144/// SPARC-specific DAG, ready for instruction scheduling. 1145/// 1146FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1147 return new SparcDAGToDAGISel(TM); 1148} 1149