SparcISelDAGToDAG.cpp revision 44ea7b1a6cc96121f9a558902742e19fa876d847
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 CALL, // A V8 call instruction. 50 RET_FLAG, // Return with a flag operand. 51 }; 52} 53 54namespace { 55 class SparcV8TargetLowering : public TargetLowering { 56 int VarArgsFrameOffset; // Frame offset to start of varargs area. 57 public: 58 SparcV8TargetLowering(TargetMachine &TM); 59 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 60 virtual std::vector<SDOperand> 61 LowerArguments(Function &F, SelectionDAG &DAG); 62 virtual std::pair<SDOperand, SDOperand> 63 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 64 unsigned CC, 65 bool isTailCall, SDOperand Callee, ArgListTy &Args, 66 SelectionDAG &DAG); 67 virtual std::pair<SDOperand, SDOperand> 68 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 69 SelectionDAG &DAG); 70 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 71 MachineBasicBlock *MBB); 72 73 virtual const char *getTargetNodeName(unsigned Opcode) const; 74 }; 75} 76 77SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 78 : TargetLowering(TM) { 79 80 // Set up the register classes. 81 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 82 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 83 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 84 85 // Custom legalize GlobalAddress nodes into LO/HI parts. 86 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 87 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 88 89 // Sparc doesn't have sext_inreg, replace them with shl/sra 90 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 91 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 93 94 // Sparc has no REM operation. 95 setOperationAction(ISD::UREM, MVT::i32, Expand); 96 setOperationAction(ISD::SREM, MVT::i32, Expand); 97 98 // Custom expand fp<->sint 99 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 100 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 101 102 // Expand fp<->uint 103 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 104 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 105 106 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 107 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 108 109 // Turn FP extload into load/fextend 110 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 111 112 // Sparc has no select or setcc: expand to SELECT_CC. 113 setOperationAction(ISD::SELECT, MVT::i32, Expand); 114 setOperationAction(ISD::SELECT, MVT::f32, Expand); 115 setOperationAction(ISD::SELECT, MVT::f64, Expand); 116 setOperationAction(ISD::SETCC, MVT::i32, Expand); 117 setOperationAction(ISD::SETCC, MVT::f32, Expand); 118 setOperationAction(ISD::SETCC, MVT::f64, Expand); 119 120 // Sparc doesn't have BRCOND either, it has BR_CC. 121 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 122 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 123 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 124 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 125 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 126 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 127 128 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 131 132 // V8 has no intrinsics for these particular operations. 133 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 134 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 135 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 136 137 setOperationAction(ISD::FSIN , MVT::f64, Expand); 138 setOperationAction(ISD::FCOS , MVT::f64, Expand); 139 setOperationAction(ISD::FSIN , MVT::f32, Expand); 140 setOperationAction(ISD::FCOS , MVT::f32, Expand); 141 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 142 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 143 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 144 setOperationAction(ISD::ROTL , MVT::i32, Expand); 145 setOperationAction(ISD::ROTR , MVT::i32, Expand); 146 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 147 148 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 149 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 150 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 151 152 // We don't have line number support yet. 153 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 154 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 155 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 156 157 // RET must be custom lowered, to meet ABI requirements 158 setOperationAction(ISD::RET , MVT::Other, Custom); 159 160 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 161 setOperationAction(ISD::VASTART , MVT::Other, Custom); 162 163 // Use the default implementation. 164 setOperationAction(ISD::VAARG , MVT::Other, Expand); 165 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 166 setOperationAction(ISD::VAEND , MVT::Other, Expand); 167 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 168 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 169 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 170 171 setStackPointerRegisterToSaveRestore(V8::O6); 172 173 computeRegisterProperties(); 174} 175 176const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { 177 switch (Opcode) { 178 default: return 0; 179 case V8ISD::CMPICC: return "V8ISD::CMPICC"; 180 case V8ISD::CMPFCC: return "V8ISD::CMPFCC"; 181 case V8ISD::BRICC: return "V8ISD::BRICC"; 182 case V8ISD::BRFCC: return "V8ISD::BRFCC"; 183 case V8ISD::Hi: return "V8ISD::Hi"; 184 case V8ISD::Lo: return "V8ISD::Lo"; 185 case V8ISD::FTOI: return "V8ISD::FTOI"; 186 case V8ISD::ITOF: return "V8ISD::ITOF"; 187 case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC"; 188 case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC"; 189 case V8ISD::CALL: return "V8ISD::CALL"; 190 case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG"; 191 } 192} 193 194/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 195/// either one or two GPRs, including FP values. TODO: we should pass FP values 196/// in FP registers for fastcc functions. 197std::vector<SDOperand> 198SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 199 MachineFunction &MF = DAG.getMachineFunction(); 200 SSARegMap *RegMap = MF.getSSARegMap(); 201 std::vector<SDOperand> ArgValues; 202 203 static const unsigned ArgRegs[] = { 204 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 205 }; 206 207 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 208 unsigned ArgOffset = 68; 209 210 SDOperand Root = DAG.getRoot(); 211 std::vector<SDOperand> OutChains; 212 213 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 214 MVT::ValueType ObjectVT = getValueType(I->getType()); 215 216 switch (ObjectVT) { 217 default: assert(0 && "Unhandled argument type!"); 218 case MVT::i1: 219 case MVT::i8: 220 case MVT::i16: 221 case MVT::i32: 222 if (I->use_empty()) { // Argument is dead. 223 if (CurArgReg < ArgRegEnd) ++CurArgReg; 224 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 225 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 226 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 227 MF.addLiveIn(*CurArgReg++, VReg); 228 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 229 if (ObjectVT != MVT::i32) { 230 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 231 : ISD::AssertZext; 232 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 233 DAG.getValueType(ObjectVT)); 234 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 235 } 236 ArgValues.push_back(Arg); 237 } else { 238 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 239 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 240 SDOperand Load; 241 if (ObjectVT == MVT::i32) { 242 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 243 } else { 244 unsigned LoadOp = 245 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 246 247 // Sparc is big endian, so add an offset based on the ObjectVT. 248 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 249 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 250 DAG.getConstant(Offset, MVT::i32)); 251 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 252 DAG.getSrcValue(0), ObjectVT); 253 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 254 } 255 ArgValues.push_back(Load); 256 } 257 258 ArgOffset += 4; 259 break; 260 case MVT::f32: 261 if (I->use_empty()) { // Argument is dead. 262 if (CurArgReg < ArgRegEnd) ++CurArgReg; 263 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 264 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 265 // FP value is passed in an integer register. 266 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 267 MF.addLiveIn(*CurArgReg++, VReg); 268 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 269 270 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 271 ArgValues.push_back(Arg); 272 } else { 273 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 274 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 275 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); 276 ArgValues.push_back(Load); 277 } 278 ArgOffset += 4; 279 break; 280 281 case MVT::i64: 282 case MVT::f64: 283 if (I->use_empty()) { // Argument is dead. 284 if (CurArgReg < ArgRegEnd) ++CurArgReg; 285 if (CurArgReg < ArgRegEnd) ++CurArgReg; 286 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 287 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 288 ((CurArgReg-ArgRegs) & 1) == 0) { 289 // If this is a double argument and the whole thing lives on the stack, 290 // and the argument is aligned, load the double straight from the stack. 291 // We can't do a load in cases like void foo([6ints], int,double), 292 // because the double wouldn't be aligned! 293 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 294 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 295 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 296 DAG.getSrcValue(0))); 297 } else { 298 SDOperand HiVal; 299 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 300 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 301 MF.addLiveIn(*CurArgReg++, VRegHi); 302 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 303 } else { 304 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 305 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 306 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 307 } 308 309 SDOperand LoVal; 310 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 311 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 312 MF.addLiveIn(*CurArgReg++, VRegLo); 313 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 314 } else { 315 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 316 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 317 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 318 } 319 320 // Compose the two halves together into an i64 unit. 321 SDOperand WholeValue = 322 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 323 324 // If we want a double, do a bit convert. 325 if (ObjectVT == MVT::f64) 326 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 327 328 ArgValues.push_back(WholeValue); 329 } 330 ArgOffset += 8; 331 break; 332 } 333 } 334 335 // Store remaining ArgRegs to the stack if this is a varargs function. 336 if (F.getFunctionType()->isVarArg()) { 337 // Remember the vararg offset for the va_start implementation. 338 VarArgsFrameOffset = ArgOffset; 339 340 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 341 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 342 MF.addLiveIn(*CurArgReg, VReg); 343 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 344 345 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 346 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 347 348 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 349 Arg, FIPtr, DAG.getSrcValue(0))); 350 ArgOffset += 4; 351 } 352 } 353 354 if (!OutChains.empty()) 355 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 356 357 // Finally, inform the code generator which regs we return values in. 358 switch (getValueType(F.getReturnType())) { 359 default: assert(0 && "Unknown type!"); 360 case MVT::isVoid: break; 361 case MVT::i1: 362 case MVT::i8: 363 case MVT::i16: 364 case MVT::i32: 365 MF.addLiveOut(V8::I0); 366 break; 367 case MVT::i64: 368 MF.addLiveOut(V8::I0); 369 MF.addLiveOut(V8::I1); 370 break; 371 case MVT::f32: 372 MF.addLiveOut(V8::F0); 373 break; 374 case MVT::f64: 375 MF.addLiveOut(V8::D0); 376 break; 377 } 378 379 return ArgValues; 380} 381 382std::pair<SDOperand, SDOperand> 383SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 384 bool isVarArg, unsigned CC, 385 bool isTailCall, SDOperand Callee, 386 ArgListTy &Args, SelectionDAG &DAG) { 387 MachineFunction &MF = DAG.getMachineFunction(); 388 // Count the size of the outgoing arguments. 389 unsigned ArgsSize = 0; 390 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 391 switch (getValueType(Args[i].second)) { 392 default: assert(0 && "Unknown value type!"); 393 case MVT::i1: 394 case MVT::i8: 395 case MVT::i16: 396 case MVT::i32: 397 case MVT::f32: 398 ArgsSize += 4; 399 break; 400 case MVT::i64: 401 case MVT::f64: 402 ArgsSize += 8; 403 break; 404 } 405 } 406 if (ArgsSize > 4*6) 407 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 408 else 409 ArgsSize = 0; 410 411 // Keep stack frames 8-byte aligned. 412 ArgsSize = (ArgsSize+7) & ~7; 413 414 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 415 DAG.getConstant(ArgsSize, getPointerTy())); 416 417 SDOperand StackPtr, NullSV; 418 std::vector<SDOperand> Stores; 419 std::vector<SDOperand> RegValuesToPass; 420 unsigned ArgOffset = 68; 421 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 422 SDOperand Val = Args[i].first; 423 MVT::ValueType ObjectVT = Val.getValueType(); 424 SDOperand ValToStore(0, 0); 425 unsigned ObjSize; 426 switch (ObjectVT) { 427 default: assert(0 && "Unhandled argument type!"); 428 case MVT::i1: 429 case MVT::i8: 430 case MVT::i16: 431 // Promote the integer to 32-bits. If the input type is signed, use a 432 // sign extend, otherwise use a zero extend. 433 if (Args[i].second->isSigned()) 434 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 435 else 436 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 437 // FALL THROUGH 438 case MVT::i32: 439 ObjSize = 4; 440 441 if (RegValuesToPass.size() >= 6) { 442 ValToStore = Val; 443 } else { 444 RegValuesToPass.push_back(Val); 445 } 446 break; 447 case MVT::f32: 448 ObjSize = 4; 449 if (RegValuesToPass.size() >= 6) { 450 ValToStore = Val; 451 } else { 452 // Convert this to a FP value in an int reg. 453 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 454 RegValuesToPass.push_back(Val); 455 } 456 break; 457 case MVT::f64: 458 ObjSize = 8; 459 // If we can store this directly into the outgoing slot, do so. We can 460 // do this when all ArgRegs are used and if the outgoing slot is aligned. 461 // FIXME: McGill/misr fails with this. 462 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 463 ValToStore = Val; 464 break; 465 } 466 467 // Otherwise, convert this to a FP value in int regs. 468 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 469 // FALL THROUGH 470 case MVT::i64: 471 ObjSize = 8; 472 if (RegValuesToPass.size() >= 6) { 473 ValToStore = Val; // Whole thing is passed in memory. 474 break; 475 } 476 477 // Split the value into top and bottom part. Top part goes in a reg. 478 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 479 DAG.getConstant(1, MVT::i32)); 480 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 481 DAG.getConstant(0, MVT::i32)); 482 RegValuesToPass.push_back(Hi); 483 484 if (RegValuesToPass.size() >= 6) { 485 ValToStore = Lo; 486 ArgOffset += 4; 487 ObjSize = 4; 488 } else { 489 RegValuesToPass.push_back(Lo); 490 } 491 break; 492 } 493 494 if (ValToStore.Val) { 495 if (!StackPtr.Val) { 496 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 497 NullSV = DAG.getSrcValue(NULL); 498 } 499 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 500 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 501 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 502 ValToStore, PtrOff, NullSV)); 503 } 504 ArgOffset += ObjSize; 505 } 506 507 // Emit all stores, make sure the occur before any copies into physregs. 508 if (!Stores.empty()) 509 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 510 511 static const unsigned ArgRegs[] = { 512 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 513 }; 514 515 // Build a sequence of copy-to-reg nodes chained together with token chain 516 // and flag operands which copy the outgoing args into O[0-5]. 517 SDOperand InFlag; 518 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 519 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 520 InFlag = Chain.getValue(1); 521 } 522 523 // If the callee is a GlobalAddress node (quite common, every direct call is) 524 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 525 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 526 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 527 528 std::vector<MVT::ValueType> NodeTys; 529 NodeTys.push_back(MVT::Other); // Returns a chain 530 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 531 std::vector<SDOperand> Ops; 532 Ops.push_back(Chain); 533 Ops.push_back(Callee); 534 if (InFlag.Val) 535 Ops.push_back(InFlag); 536 Chain = DAG.getNode(V8ISD::CALL, NodeTys, Ops); 537 InFlag = Chain.getValue(1); 538 539 MVT::ValueType RetTyVT = getValueType(RetTy); 540 SDOperand RetVal; 541 if (RetTyVT != MVT::isVoid) { 542 switch (RetTyVT) { 543 default: assert(0 && "Unknown value type to return!"); 544 case MVT::i1: 545 case MVT::i8: 546 case MVT::i16: 547 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 548 Chain = RetVal.getValue(1); 549 550 // Add a note to keep track of whether it is sign or zero extended. 551 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 552 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 553 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 554 break; 555 case MVT::i32: 556 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 557 Chain = RetVal.getValue(1); 558 break; 559 case MVT::f32: 560 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 561 Chain = RetVal.getValue(1); 562 break; 563 case MVT::f64: 564 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 565 Chain = RetVal.getValue(1); 566 break; 567 case MVT::i64: 568 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 569 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 570 Lo.getValue(2)); 571 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 572 Chain = Hi.getValue(1); 573 break; 574 } 575 } 576 577 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 578 DAG.getConstant(ArgsSize, getPointerTy())); 579 580 return std::make_pair(RetVal, Chain); 581} 582 583std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 584LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 585 SelectionDAG &DAG) { 586 assert(0 && "Unimp"); 587 abort(); 588} 589 590SDOperand SparcV8TargetLowering:: 591LowerOperation(SDOperand Op, SelectionDAG &DAG) { 592 switch (Op.getOpcode()) { 593 default: assert(0 && "Should not custom lower this!"); 594 case ISD::GlobalAddress: { 595 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 596 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 597 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 598 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 599 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 600 } 601 case ISD::ConstantPool: { 602 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 603 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 604 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 605 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 606 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 607 } 608 case ISD::FP_TO_SINT: 609 // Convert the fp value to integer in an FP register. 610 assert(Op.getValueType() == MVT::i32); 611 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 612 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 613 case ISD::SINT_TO_FP: { 614 assert(Op.getOperand(0).getValueType() == MVT::i32); 615 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 616 // Convert the int value to FP in an FP register. 617 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp); 618 } 619 case ISD::BR_CC: { 620 SDOperand Chain = Op.getOperand(0); 621 SDOperand CC = Op.getOperand(1); 622 SDOperand LHS = Op.getOperand(2); 623 SDOperand RHS = Op.getOperand(3); 624 SDOperand Dest = Op.getOperand(4); 625 626 // Get the condition flag. 627 if (LHS.getValueType() == MVT::i32) { 628 std::vector<MVT::ValueType> VTs; 629 VTs.push_back(MVT::i32); 630 VTs.push_back(MVT::Flag); 631 std::vector<SDOperand> Ops; 632 Ops.push_back(LHS); 633 Ops.push_back(RHS); 634 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 635 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 636 } else { 637 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 638 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 639 } 640 } 641 case ISD::SELECT_CC: { 642 SDOperand LHS = Op.getOperand(0); 643 SDOperand RHS = Op.getOperand(1); 644 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 645 SDOperand TrueVal = Op.getOperand(2); 646 SDOperand FalseVal = Op.getOperand(3); 647 648 SDOperand CompareFlag; 649 unsigned Opc; 650 if (LHS.getValueType() == MVT::i32) { 651 std::vector<MVT::ValueType> VTs; 652 VTs.push_back(LHS.getValueType()); // subcc returns a value 653 VTs.push_back(MVT::Flag); 654 std::vector<SDOperand> Ops; 655 Ops.push_back(LHS); 656 Ops.push_back(RHS); 657 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 658 Opc = V8ISD::SELECT_ICC; 659 } else { 660 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 661 Opc = V8ISD::SELECT_FCC; 662 } 663 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 664 DAG.getConstant(CC, MVT::i32), CompareFlag); 665 } 666 case ISD::VASTART: { 667 // vastart just stores the address of the VarArgsFrameIndex slot into the 668 // memory location argument. 669 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 670 DAG.getRegister(V8::I6, MVT::i32), 671 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 672 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 673 Op.getOperand(1), Op.getOperand(2)); 674 } 675 case ISD::RET: { 676 SDOperand Copy; 677 678 switch(Op.getNumOperands()) { 679 default: 680 assert(0 && "Do not know how to return this many arguments!"); 681 abort(); 682 case 1: 683 return SDOperand(); // ret void is legal 684 case 2: { 685 unsigned ArgReg; 686 switch(Op.getOperand(1).getValueType()) { 687 default: assert(0 && "Unknown type to return!"); 688 case MVT::i32: ArgReg = V8::I0; break; 689 case MVT::f32: ArgReg = V8::F0; break; 690 case MVT::f64: ArgReg = V8::D0; break; 691 } 692 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 693 SDOperand()); 694 break; 695 } 696 case 3: 697 Copy = DAG.getCopyToReg(Op.getOperand(0), V8::I0, Op.getOperand(2), 698 SDOperand()); 699 Copy = DAG.getCopyToReg(Copy, V8::I1, Op.getOperand(1), Copy.getValue(1)); 700 break; 701 } 702 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 703 } 704 } 705} 706 707MachineBasicBlock * 708SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 709 MachineBasicBlock *BB) { 710 unsigned BROpcode; 711 // Figure out the conditional branch opcode to use for this select_cc. 712 switch (MI->getOpcode()) { 713 default: assert(0 && "Unknown SELECT_CC!"); 714 case V8::SELECT_CC_Int_ICC: 715 case V8::SELECT_CC_FP_ICC: 716 case V8::SELECT_CC_DFP_ICC: 717 // Integer compare. 718 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 719 default: assert(0 && "Unknown integer condition code!"); 720 case ISD::SETEQ: BROpcode = V8::BE; break; 721 case ISD::SETNE: BROpcode = V8::BNE; break; 722 case ISD::SETLT: BROpcode = V8::BL; break; 723 case ISD::SETGT: BROpcode = V8::BG; break; 724 case ISD::SETLE: BROpcode = V8::BLE; break; 725 case ISD::SETGE: BROpcode = V8::BGE; break; 726 case ISD::SETULT: BROpcode = V8::BCS; break; 727 case ISD::SETULE: BROpcode = V8::BLEU; break; 728 case ISD::SETUGT: BROpcode = V8::BGU; break; 729 case ISD::SETUGE: BROpcode = V8::BCC; break; 730 } 731 break; 732 case V8::SELECT_CC_Int_FCC: 733 case V8::SELECT_CC_FP_FCC: 734 case V8::SELECT_CC_DFP_FCC: 735 // FP compare. 736 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 737 default: assert(0 && "Unknown fp condition code!"); 738 case ISD::SETEQ: BROpcode = V8::FBE; break; 739 case ISD::SETNE: BROpcode = V8::FBNE; break; 740 case ISD::SETLT: BROpcode = V8::FBL; break; 741 case ISD::SETGT: BROpcode = V8::FBG; break; 742 case ISD::SETLE: BROpcode = V8::FBLE; break; 743 case ISD::SETGE: BROpcode = V8::FBGE; break; 744 case ISD::SETULT: BROpcode = V8::FBUL; break; 745 case ISD::SETULE: BROpcode = V8::FBULE; break; 746 case ISD::SETUGT: BROpcode = V8::FBUG; break; 747 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 748 case ISD::SETUO: BROpcode = V8::FBU; break; 749 case ISD::SETO: BROpcode = V8::FBO; break; 750 case ISD::SETONE: BROpcode = V8::FBLG; break; 751 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 752 } 753 break; 754 } 755 756 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 757 // control-flow pattern. The incoming instruction knows the destination vreg 758 // to set, the condition code register to branch on, the true/false values to 759 // select between, and a branch opcode to use. 760 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 761 ilist<MachineBasicBlock>::iterator It = BB; 762 ++It; 763 764 // thisMBB: 765 // ... 766 // TrueVal = ... 767 // [f]bCC copy1MBB 768 // fallthrough --> copy0MBB 769 MachineBasicBlock *thisMBB = BB; 770 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 771 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 772 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 773 MachineFunction *F = BB->getParent(); 774 F->getBasicBlockList().insert(It, copy0MBB); 775 F->getBasicBlockList().insert(It, sinkMBB); 776 // Update machine-CFG edges 777 BB->addSuccessor(copy0MBB); 778 BB->addSuccessor(sinkMBB); 779 780 // copy0MBB: 781 // %FalseValue = ... 782 // # fallthrough to sinkMBB 783 BB = copy0MBB; 784 785 // Update machine-CFG edges 786 BB->addSuccessor(sinkMBB); 787 788 // sinkMBB: 789 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 790 // ... 791 BB = sinkMBB; 792 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 793 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 794 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 795 796 delete MI; // The pseudo instruction is gone now. 797 return BB; 798} 799 800//===----------------------------------------------------------------------===// 801// Instruction Selector Implementation 802//===----------------------------------------------------------------------===// 803 804//===--------------------------------------------------------------------===// 805/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine 806/// instructions for SelectionDAG operations. 807/// 808namespace { 809class SparcV8DAGToDAGISel : public SelectionDAGISel { 810 SparcV8TargetLowering V8Lowering; 811public: 812 SparcV8DAGToDAGISel(TargetMachine &TM) 813 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 814 815 SDOperand Select(SDOperand Op); 816 817 // Complex Pattern Selectors. 818 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 819 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 820 821 /// InstructionSelectBasicBlock - This callback is invoked by 822 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 823 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 824 825 virtual const char *getPassName() const { 826 return "SparcV8 DAG->DAG Pattern Instruction Selection"; 827 } 828 829 // Include the pieces autogenerated from the target description. 830#include "SparcV8GenDAGISel.inc" 831}; 832} // end anonymous namespace 833 834/// InstructionSelectBasicBlock - This callback is invoked by 835/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 836void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 837 DEBUG(BB->dump()); 838 839 // Select target instructions for the DAG. 840 DAG.setRoot(Select(DAG.getRoot())); 841 CodeGenMap.clear(); 842 DAG.RemoveDeadNodes(); 843 844 // Emit machine code to BB. 845 ScheduleAndEmitDAG(DAG); 846} 847 848bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 849 SDOperand &Offset) { 850 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 851 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 852 Offset = CurDAG->getTargetConstant(0, MVT::i32); 853 return true; 854 } 855 856 if (Addr.getOpcode() == ISD::ADD) { 857 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 858 if (Predicate_simm13(CN)) { 859 if (FrameIndexSDNode *FIN = 860 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 861 // Constant offset from frame ref. 862 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 863 } else { 864 Base = Select(Addr.getOperand(0)); 865 } 866 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 867 return true; 868 } 869 } 870 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 871 Base = Select(Addr.getOperand(1)); 872 Offset = Addr.getOperand(0).getOperand(0); 873 return true; 874 } 875 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 876 Base = Select(Addr.getOperand(0)); 877 Offset = Addr.getOperand(1).getOperand(0); 878 return true; 879 } 880 } 881 Base = Select(Addr); 882 Offset = CurDAG->getTargetConstant(0, MVT::i32); 883 return true; 884} 885 886bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 887 SDOperand &R2) { 888 if (Addr.getOpcode() == ISD::FrameIndex) return false; 889 if (Addr.getOpcode() == ISD::ADD) { 890 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 891 Predicate_simm13(Addr.getOperand(1).Val)) 892 return false; // Let the reg+imm pattern catch this! 893 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 894 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 895 return false; // Let the reg+imm pattern catch this! 896 R1 = Select(Addr.getOperand(0)); 897 R2 = Select(Addr.getOperand(1)); 898 return true; 899 } 900 901 R1 = Select(Addr); 902 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 903 return true; 904} 905 906SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 907 SDNode *N = Op.Val; 908 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 909 N->getOpcode() < V8ISD::FIRST_NUMBER) 910 return Op; // Already selected. 911 // If this has already been converted, use it. 912 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 913 if (CGMI != CodeGenMap.end()) return CGMI->second; 914 915 switch (N->getOpcode()) { 916 default: break; 917 case ISD::FrameIndex: { 918 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 919 if (N->hasOneUse()) 920 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 921 CurDAG->getTargetFrameIndex(FI, MVT::i32), 922 CurDAG->getTargetConstant(0, MVT::i32)); 923 return CodeGenMap[Op] = 924 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 925 CurDAG->getTargetFrameIndex(FI, MVT::i32), 926 CurDAG->getTargetConstant(0, MVT::i32)); 927 } 928 case ISD::ADD_PARTS: { 929 SDOperand LHSL = Select(N->getOperand(0)); 930 SDOperand LHSH = Select(N->getOperand(1)); 931 SDOperand RHSL = Select(N->getOperand(2)); 932 SDOperand RHSH = Select(N->getOperand(3)); 933 // FIXME, handle immediate RHS. 934 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 935 LHSL, RHSL); 936 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 937 Low.getValue(1)); 938 CodeGenMap[SDOperand(N, 0)] = Low; 939 CodeGenMap[SDOperand(N, 1)] = Hi; 940 return Op.ResNo ? Hi : Low; 941 } 942 case ISD::SUB_PARTS: { 943 SDOperand LHSL = Select(N->getOperand(0)); 944 SDOperand LHSH = Select(N->getOperand(1)); 945 SDOperand RHSL = Select(N->getOperand(2)); 946 SDOperand RHSH = Select(N->getOperand(3)); 947 // FIXME, handle immediate RHS. 948 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 949 LHSL, RHSL); 950 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 951 Low.getValue(1)); 952 CodeGenMap[SDOperand(N, 0)] = Low; 953 CodeGenMap[SDOperand(N, 1)] = Hi; 954 return Op.ResNo ? Hi : Low; 955 } 956 case ISD::SDIV: 957 case ISD::UDIV: { 958 // FIXME: should use a custom expander to expose the SRA to the dag. 959 SDOperand DivLHS = Select(N->getOperand(0)); 960 SDOperand DivRHS = Select(N->getOperand(1)); 961 962 // Set the Y register to the high-part. 963 SDOperand TopPart; 964 if (N->getOpcode() == ISD::SDIV) { 965 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 966 CurDAG->getTargetConstant(31, MVT::i32)); 967 } else { 968 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 969 } 970 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 971 CurDAG->getRegister(V8::G0, MVT::i32)); 972 973 // FIXME: Handle div by immediate. 974 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 975 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 976 } 977 case ISD::MULHU: 978 case ISD::MULHS: { 979 // FIXME: Handle mul by immediate. 980 SDOperand MulLHS = Select(N->getOperand(0)); 981 SDOperand MulRHS = Select(N->getOperand(1)); 982 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 983 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 984 MulLHS, MulRHS); 985 // The high part is in the Y register. 986 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 987 } 988 case V8ISD::CALL: 989 // FIXME: This is a workaround for a bug in tblgen. 990 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 991 // Emits: (CALL:void (tglobaladdr:i32):$dst) 992 // Pattern complexity = 2 cost = 1 993 SDOperand N1 = N->getOperand(1); 994 if (N1.getOpcode() != ISD::TargetGlobalAddress && 995 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 996 SDOperand InFlag = SDOperand(0, 0); 997 SDOperand Chain = N->getOperand(0); 998 SDOperand Tmp0 = N1; 999 Chain = Select(Chain); 1000 SDOperand Result; 1001 if (N->getNumOperands() == 3) { 1002 InFlag = Select(N->getOperand(2)); 1003 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1004 Chain, InFlag); 1005 } else { 1006 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1007 Chain); 1008 } 1009 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1010 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1011 return Result.getValue(Op.ResNo); 1012 } 1013 P47Fail:; 1014 1015 } 1016 1017 return SelectCode(Op); 1018} 1019 1020 1021/// createSparcV8ISelDag - This pass converts a legalized DAG into a 1022/// SPARC-specific DAG, ready for instruction scheduling. 1023/// 1024FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1025 return new SparcV8DAGToDAGISel(TM); 1026} 1027