SparcISelDAGToDAG.cpp revision 4bb91024ac2dcdff363488617ffcfb3b5c99fc49 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Support/Debug.h"
26#include <iostream>
27using namespace llvm;
28
29//===----------------------------------------------------------------------===//
30// TargetLowering Implementation
31//===----------------------------------------------------------------------===//
32
33namespace V8ISD {
34  enum {
35    FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36    CMPICC,   // Compare two GPR operands, set icc.
37    CMPFCC,   // Compare two FP operands, set fcc.
38    BRICC,    // Branch to dest on icc condition
39    BRFCC,    // Branch to dest on fcc condition
40
41    Hi, Lo,   // Hi/Lo operations, typically on a global address.
42
43    FTOI,     // FP to Int within a FP register.
44    ITOF,     // Int to FP within a FP register.
45
46    SELECT_ICC, // Select between two values using the current ICC flags.
47    SELECT_FCC, // Select between two values using the current FCC flags.
48
49    RET_FLAG,   // Return with a flag operand.
50  };
51}
52
53namespace {
54  class SparcV8TargetLowering : public TargetLowering {
55    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
56  public:
57    SparcV8TargetLowering(TargetMachine &TM);
58    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59    virtual std::vector<SDOperand>
60      LowerArguments(Function &F, SelectionDAG &DAG);
61    virtual std::pair<SDOperand, SDOperand>
62      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
63                  unsigned CC,
64                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
65                  SelectionDAG &DAG);
66
67    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
68                                    SelectionDAG &DAG);
69    virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
70                                   Value *VAListV, SelectionDAG &DAG);
71    virtual std::pair<SDOperand,SDOperand>
72      LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
73                 const Type *ArgTy, SelectionDAG &DAG);
74    virtual std::pair<SDOperand, SDOperand>
75      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
76                              SelectionDAG &DAG);
77    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
78                                                       MachineBasicBlock *MBB);
79
80    virtual const char *getTargetNodeName(unsigned Opcode) const;
81  };
82}
83
84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
85  : TargetLowering(TM) {
86
87  // Set up the register classes.
88  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
89  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
90  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
91
92  // Custom legalize GlobalAddress nodes into LO/HI parts.
93  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
95
96  // Sparc doesn't have sext_inreg, replace them with shl/sra
97  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
98  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
99  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
100
101  // Sparc has no REM operation.
102  setOperationAction(ISD::UREM, MVT::i32, Expand);
103  setOperationAction(ISD::SREM, MVT::i32, Expand);
104
105  // Custom expand fp<->sint
106  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
107  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
108
109  // Expand fp<->uint
110  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
111  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
112
113  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
114  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
115
116  // Turn FP extload into load/fextend
117  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
118
119  // Sparc has no select or setcc: expand to SELECT_CC.
120  setOperationAction(ISD::SELECT, MVT::i32, Expand);
121  setOperationAction(ISD::SELECT, MVT::f32, Expand);
122  setOperationAction(ISD::SELECT, MVT::f64, Expand);
123  setOperationAction(ISD::SETCC, MVT::i32, Expand);
124  setOperationAction(ISD::SETCC, MVT::f32, Expand);
125  setOperationAction(ISD::SETCC, MVT::f64, Expand);
126
127  // Sparc doesn't have BRCOND either, it has BR_CC.
128  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
130  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
131  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
132  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
133  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
134
135  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
136  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
138
139  // V8 has no intrinsics for these particular operations.
140  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
141  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
142  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
143
144  setOperationAction(ISD::FSIN , MVT::f64, Expand);
145  setOperationAction(ISD::FCOS , MVT::f64, Expand);
146  setOperationAction(ISD::FSIN , MVT::f32, Expand);
147  setOperationAction(ISD::FCOS , MVT::f32, Expand);
148  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
149  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
150  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
151  setOperationAction(ISD::ROTL , MVT::i32, Expand);
152  setOperationAction(ISD::ROTR , MVT::i32, Expand);
153
154  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
155  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
156  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
157
158  // We don't have line number support yet.
159  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
160  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
161  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
162
163  computeRegisterProperties();
164}
165
166const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
167  switch (Opcode) {
168  default: return 0;
169  case V8ISD::CMPICC:     return "V8ISD::CMPICC";
170  case V8ISD::CMPFCC:     return "V8ISD::CMPFCC";
171  case V8ISD::BRICC:      return "V8ISD::BRICC";
172  case V8ISD::BRFCC:      return "V8ISD::BRFCC";
173  case V8ISD::Hi:         return "V8ISD::Hi";
174  case V8ISD::Lo:         return "V8ISD::Lo";
175  case V8ISD::FTOI:       return "V8ISD::FTOI";
176  case V8ISD::ITOF:       return "V8ISD::ITOF";
177  case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
178  case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
179  case V8ISD::RET_FLAG:   return "V8ISD::RET_FLAG";
180  }
181}
182
183/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
184/// either one or two GPRs, including FP values.  TODO: we should pass FP values
185/// in FP registers for fastcc functions.
186std::vector<SDOperand>
187SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
188  MachineFunction &MF = DAG.getMachineFunction();
189  SSARegMap *RegMap = MF.getSSARegMap();
190  std::vector<SDOperand> ArgValues;
191
192  static const unsigned ArgRegs[] = {
193    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
194  };
195
196  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
197  unsigned ArgOffset = 68;
198
199  SDOperand Root = DAG.getRoot();
200  std::vector<SDOperand> OutChains;
201
202  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
203    MVT::ValueType ObjectVT = getValueType(I->getType());
204
205    switch (ObjectVT) {
206    default: assert(0 && "Unhandled argument type!");
207    case MVT::i1:
208    case MVT::i8:
209    case MVT::i16:
210    case MVT::i32:
211      if (I->use_empty()) {                // Argument is dead.
212        if (CurArgReg < ArgRegEnd) ++CurArgReg;
213        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
214      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
215        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
216        MF.addLiveIn(*CurArgReg++, VReg);
217        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
218        if (ObjectVT != MVT::i32) {
219          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
220                                                       : ISD::AssertZext;
221          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
222                            DAG.getValueType(ObjectVT));
223          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
224        }
225        ArgValues.push_back(Arg);
226      } else {
227        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
228        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
229        SDOperand Load;
230        if (ObjectVT == MVT::i32) {
231          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
232        } else {
233          unsigned LoadOp =
234            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
235
236          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
237                                DAG.getSrcValue(0), ObjectVT);
238        }
239        ArgValues.push_back(Load);
240      }
241
242      ArgOffset += 4;
243      break;
244    case MVT::f32:
245      if (I->use_empty()) {                // Argument is dead.
246        if (CurArgReg < ArgRegEnd) ++CurArgReg;
247        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
248      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
249        // FP value is passed in an integer register.
250        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
251        MF.addLiveIn(*CurArgReg++, VReg);
252        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
253
254        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
255        ArgValues.push_back(Arg);
256      }
257      ArgOffset += 4;
258      break;
259
260    case MVT::i64:
261    case MVT::f64:
262      if (I->use_empty()) {                // Argument is dead.
263        if (CurArgReg < ArgRegEnd) ++CurArgReg;
264        if (CurArgReg < ArgRegEnd) ++CurArgReg;
265        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
266      } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
267                 ((CurArgReg-ArgRegs) & 1) == 0) {
268        // If this is a double argument and the whole thing lives on the stack,
269        // and the argument is aligned, load the double straight from the stack.
270        // We can't do a load in cases like void foo([6ints], int,double),
271        // because the double wouldn't be aligned!
272        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
273        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
274        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
275                                        DAG.getSrcValue(0)));
276      } else {
277        SDOperand HiVal;
278        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
279          unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
280          MF.addLiveIn(*CurArgReg++, VRegHi);
281          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
282        } else {
283          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
284          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
285          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
286        }
287
288        SDOperand LoVal;
289        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
290          unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
291          MF.addLiveIn(*CurArgReg++, VRegLo);
292          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
293        } else {
294          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
295          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
296          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
297        }
298
299        // Compose the two halves together into an i64 unit.
300        SDOperand WholeValue =
301          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
302
303        // If we want a double, do a bit convert.
304        if (ObjectVT == MVT::f64)
305          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
306
307        ArgValues.push_back(WholeValue);
308      }
309      ArgOffset += 8;
310      break;
311    }
312  }
313
314  // Store remaining ArgRegs to the stack if this is a varargs function.
315  if (F.getFunctionType()->isVarArg()) {
316    // Remember the vararg offset for the va_start implementation.
317    VarArgsFrameOffset = ArgOffset;
318
319    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
320      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
321      MF.addLiveIn(*CurArgReg, VReg);
322      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
323
324      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
325      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
326
327      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
328                                      Arg, FIPtr, DAG.getSrcValue(0)));
329      ArgOffset += 4;
330    }
331  }
332
333  if (!OutChains.empty())
334    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
335
336  // Finally, inform the code generator which regs we return values in.
337  switch (getValueType(F.getReturnType())) {
338  default: assert(0 && "Unknown type!");
339  case MVT::isVoid: break;
340  case MVT::i1:
341  case MVT::i8:
342  case MVT::i16:
343  case MVT::i32:
344    MF.addLiveOut(V8::I0);
345    break;
346  case MVT::i64:
347    MF.addLiveOut(V8::I0);
348    MF.addLiveOut(V8::I1);
349    break;
350  case MVT::f32:
351    MF.addLiveOut(V8::F0);
352    break;
353  case MVT::f64:
354    MF.addLiveOut(V8::D0);
355    break;
356  }
357
358  return ArgValues;
359}
360
361std::pair<SDOperand, SDOperand>
362SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
363                                   bool isVarArg, unsigned CC,
364                                   bool isTailCall, SDOperand Callee,
365                                   ArgListTy &Args, SelectionDAG &DAG) {
366  MachineFunction &MF = DAG.getMachineFunction();
367  // Count the size of the outgoing arguments.
368  unsigned ArgsSize = 0;
369  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
370    switch (getValueType(Args[i].second)) {
371    default: assert(0 && "Unknown value type!");
372    case MVT::i1:
373    case MVT::i8:
374    case MVT::i16:
375    case MVT::i32:
376    case MVT::f32:
377      ArgsSize += 4;
378      break;
379    case MVT::i64:
380    case MVT::f64:
381      ArgsSize += 8;
382      break;
383    }
384  }
385  if (ArgsSize > 4*6)
386    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
387  else
388    ArgsSize = 0;
389
390  // Keep stack frames 8-byte aligned.
391  ArgsSize = (ArgsSize+7) & ~7;
392
393  Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
394                      DAG.getConstant(ArgsSize, getPointerTy()));
395
396  SDOperand StackPtr, NullSV;
397  std::vector<SDOperand> Stores;
398  std::vector<SDOperand> RegValuesToPass;
399  unsigned ArgOffset = 68;
400  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
401    SDOperand Val = Args[i].first;
402    MVT::ValueType ObjectVT = Val.getValueType();
403    SDOperand ValToStore(0, 0);
404    unsigned ObjSize;
405    switch (ObjectVT) {
406    default: assert(0 && "Unhandled argument type!");
407    case MVT::i1:
408    case MVT::i8:
409    case MVT::i16:
410      // Promote the integer to 32-bits.  If the input type is signed, use a
411      // sign extend, otherwise use a zero extend.
412      if (Args[i].second->isSigned())
413        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
414      else
415        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
416      // FALL THROUGH
417    case MVT::i32:
418      ObjSize = 4;
419
420      if (RegValuesToPass.size() >= 6) {
421        ValToStore = Val;
422      } else {
423        RegValuesToPass.push_back(Val);
424      }
425      break;
426    case MVT::f32:
427      ObjSize = 4;
428      if (RegValuesToPass.size() >= 6) {
429        ValToStore = Val;
430      } else {
431        // Convert this to a FP value in an int reg.
432        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
433        RegValuesToPass.push_back(Val);
434      }
435      break;
436    case MVT::f64:
437      ObjSize = 8;
438      // If we can store this directly into the outgoing slot, do so.  We can
439      // do this when all ArgRegs are used and if the outgoing slot is aligned.
440      if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
441        ValToStore = Val;
442        break;
443      }
444
445      // Otherwise, convert this to a FP value in int regs.
446      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
447      // FALL THROUGH
448    case MVT::i64:
449      ObjSize = 8;
450      if (RegValuesToPass.size() >= 6) {
451        ValToStore = Val;    // Whole thing is passed in memory.
452        break;
453      }
454
455      // Split the value into top and bottom part.  Top part goes in a reg.
456      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
457                                 DAG.getConstant(1, MVT::i32));
458      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
459                                 DAG.getConstant(0, MVT::i32));
460      RegValuesToPass.push_back(Hi);
461
462      if (RegValuesToPass.size() >= 6) {
463        ValToStore = Lo;
464        ArgOffset += 4;
465        ObjSize = 4;
466      } else {
467        RegValuesToPass.push_back(Lo);
468      }
469      break;
470    }
471
472    if (ValToStore.Val) {
473      if (!StackPtr.Val) {
474        StackPtr = DAG.getRegister(V8::O6, MVT::i32);
475        NullSV = DAG.getSrcValue(NULL);
476      }
477      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
478      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
479      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
480                                   ValToStore, PtrOff, NullSV));
481    }
482    ArgOffset += ObjSize;
483  }
484
485  // Emit all stores, make sure the occur before any copies into physregs.
486  if (!Stores.empty())
487    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
488
489  static const unsigned ArgRegs[] = {
490    V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
491  };
492
493  // Build a sequence of copy-to-reg nodes chained together with token chain
494  // and flag operands which copy the outgoing args into O[0-5].
495  SDOperand InFlag;
496  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
497    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
498    InFlag = Chain.getValue(1);
499  }
500
501  // If the callee is a GlobalAddress node (quite common, every direct call is)
502  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
503  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
504    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
505
506  std::vector<MVT::ValueType> NodeTys;
507  NodeTys.push_back(MVT::Other);   // Returns a chain
508  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
509  if (InFlag.Val)
510    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
511  else
512    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
513  InFlag = Chain.getValue(1);
514
515  MVT::ValueType RetTyVT = getValueType(RetTy);
516  SDOperand RetVal;
517  if (RetTyVT != MVT::isVoid) {
518    switch (RetTyVT) {
519    default: assert(0 && "Unknown value type to return!");
520    case MVT::i1:
521    case MVT::i8:
522    case MVT::i16:
523      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
524      Chain = RetVal.getValue(1);
525
526      // Add a note to keep track of whether it is sign or zero extended.
527      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
528                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
529      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
530      break;
531    case MVT::i32:
532      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
533      Chain = RetVal.getValue(1);
534      break;
535    case MVT::f32:
536      RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
537      Chain = RetVal.getValue(1);
538      break;
539    case MVT::f64:
540      RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
541      Chain = RetVal.getValue(1);
542      break;
543    case MVT::i64:
544      SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
545      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
546                                        Lo.getValue(2));
547      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
548      Chain = Hi.getValue(1);
549      break;
550    }
551  }
552
553  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
554                      DAG.getConstant(ArgsSize, getPointerTy()));
555
556  return std::make_pair(RetVal, Chain);
557}
558
559SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
560                                               SelectionDAG &DAG) {
561  SDOperand Copy;
562  switch (Op.getValueType()) {
563  default: assert(0 && "Unknown type to return!");
564  case MVT::i32:
565    Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
566    break;
567  case MVT::f32:
568    Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
569    break;
570  case MVT::f64:
571    Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
572    break;
573  case MVT::i64:
574    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
575                               DAG.getConstant(1, MVT::i32));
576    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
577                               DAG.getConstant(0, MVT::i32));
578    Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
579    Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
580    break;
581  }
582  return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
583}
584
585SDOperand SparcV8TargetLowering::
586LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
587             SelectionDAG &DAG) {
588
589  SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
590                                 DAG.getRegister(V8::I6, MVT::i32),
591                                 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
592  return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
593                     VAListP, DAG.getSrcValue(VAListV));
594}
595
596std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
597LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
598           const Type *ArgTy, SelectionDAG &DAG) {
599  // Load the pointer out of the valist.
600  SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
601                              VAListP, DAG.getSrcValue(VAListV));
602  MVT::ValueType ArgVT = getValueType(ArgTy);
603  SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
604                              Ptr, DAG.getSrcValue(NULL));
605  // Increment the pointer.
606  Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
607                    DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
608  // Store it back to the valist.
609  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
610                      VAListP, DAG.getSrcValue(VAListV));
611  return std::make_pair(Val, Chain);
612}
613
614std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
615LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
616                        SelectionDAG &DAG) {
617  assert(0 && "Unimp");
618  abort();
619}
620
621SDOperand SparcV8TargetLowering::
622LowerOperation(SDOperand Op, SelectionDAG &DAG) {
623  switch (Op.getOpcode()) {
624  default: assert(0 && "Should not custom lower this!");
625  case ISD::GlobalAddress: {
626    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
627    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
628    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
629    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
630    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
631  }
632  case ISD::ConstantPool: {
633    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
634    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
635    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
636    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
637    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
638  }
639  case ISD::FP_TO_SINT:
640    // Convert the fp value to integer in an FP register.
641    assert(Op.getValueType() == MVT::i32);
642    Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
643    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
644  case ISD::SINT_TO_FP: {
645    assert(Op.getOperand(0).getValueType() == MVT::i32);
646    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
647    // Convert the int value to FP in an FP register.
648    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
649  }
650  case ISD::BR_CC: {
651    SDOperand Chain = Op.getOperand(0);
652    SDOperand CC = Op.getOperand(1);
653    SDOperand LHS = Op.getOperand(2);
654    SDOperand RHS = Op.getOperand(3);
655    SDOperand Dest = Op.getOperand(4);
656
657    // Get the condition flag.
658    if (LHS.getValueType() == MVT::i32) {
659      std::vector<MVT::ValueType> VTs;
660      VTs.push_back(MVT::i32);
661      VTs.push_back(MVT::Flag);
662      std::vector<SDOperand> Ops;
663      Ops.push_back(LHS);
664      Ops.push_back(RHS);
665      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
666      return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
667    } else {
668      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
669      return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
670    }
671  }
672  case ISD::SELECT_CC: {
673    SDOperand LHS = Op.getOperand(0);
674    SDOperand RHS = Op.getOperand(1);
675    unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
676    SDOperand TrueVal = Op.getOperand(2);
677    SDOperand FalseVal = Op.getOperand(3);
678
679    SDOperand CompareFlag;
680    unsigned Opc;
681    if (LHS.getValueType() == MVT::i32) {
682      std::vector<MVT::ValueType> VTs;
683      VTs.push_back(LHS.getValueType());   // subcc returns a value
684      VTs.push_back(MVT::Flag);
685      std::vector<SDOperand> Ops;
686      Ops.push_back(LHS);
687      Ops.push_back(RHS);
688      CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
689      Opc = V8ISD::SELECT_ICC;
690    } else {
691      CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
692      Opc = V8ISD::SELECT_FCC;
693    }
694    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
695                       DAG.getConstant(CC, MVT::i32), CompareFlag);
696  }
697  }
698}
699
700MachineBasicBlock *
701SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
702                                               MachineBasicBlock *BB) {
703  unsigned BROpcode;
704  // Figure out the conditional branch opcode to use for this select_cc.
705  switch (MI->getOpcode()) {
706  default: assert(0 && "Unknown SELECT_CC!");
707  case V8::SELECT_CC_Int_ICC:
708  case V8::SELECT_CC_FP_ICC:
709  case V8::SELECT_CC_DFP_ICC:
710    // Integer compare.
711    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
712    default: assert(0 && "Unknown integer condition code!");
713    case ISD::SETEQ:  BROpcode = V8::BE; break;
714    case ISD::SETNE:  BROpcode = V8::BNE; break;
715    case ISD::SETLT:  BROpcode = V8::BL; break;
716    case ISD::SETGT:  BROpcode = V8::BG; break;
717    case ISD::SETLE:  BROpcode = V8::BLE; break;
718    case ISD::SETGE:  BROpcode = V8::BGE; break;
719    case ISD::SETULT: BROpcode = V8::BCS; break;
720    case ISD::SETULE: BROpcode = V8::BLEU; break;
721    case ISD::SETUGT: BROpcode = V8::BGU; break;
722    case ISD::SETUGE: BROpcode = V8::BCC; break;
723    }
724    break;
725  case V8::SELECT_CC_Int_FCC:
726  case V8::SELECT_CC_FP_FCC:
727  case V8::SELECT_CC_DFP_FCC:
728    // FP compare.
729    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
730    default: assert(0 && "Unknown fp condition code!");
731    case ISD::SETEQ:  BROpcode = V8::FBE; break;
732    case ISD::SETNE:  BROpcode = V8::FBNE; break;
733    case ISD::SETLT:  BROpcode = V8::FBL; break;
734    case ISD::SETGT:  BROpcode = V8::FBG; break;
735    case ISD::SETLE:  BROpcode = V8::FBLE; break;
736    case ISD::SETGE:  BROpcode = V8::FBGE; break;
737    case ISD::SETULT: BROpcode = V8::FBUL; break;
738    case ISD::SETULE: BROpcode = V8::FBULE; break;
739    case ISD::SETUGT: BROpcode = V8::FBUG; break;
740    case ISD::SETUGE: BROpcode = V8::FBUGE; break;
741    case ISD::SETUO:  BROpcode = V8::FBU; break;
742    case ISD::SETO:   BROpcode = V8::FBO; break;
743    case ISD::SETONE: BROpcode = V8::FBLG; break;
744    case ISD::SETUEQ: BROpcode = V8::FBUE; break;
745    }
746    break;
747  }
748
749  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
750  // control-flow pattern.  The incoming instruction knows the destination vreg
751  // to set, the condition code register to branch on, the true/false values to
752  // select between, and a branch opcode to use.
753  const BasicBlock *LLVM_BB = BB->getBasicBlock();
754  ilist<MachineBasicBlock>::iterator It = BB;
755  ++It;
756
757  //  thisMBB:
758  //  ...
759  //   TrueVal = ...
760  //   [f]bCC copy1MBB
761  //   fallthrough --> copy0MBB
762  MachineBasicBlock *thisMBB = BB;
763  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
764  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
765  BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
766  MachineFunction *F = BB->getParent();
767  F->getBasicBlockList().insert(It, copy0MBB);
768  F->getBasicBlockList().insert(It, sinkMBB);
769  // Update machine-CFG edges
770  BB->addSuccessor(copy0MBB);
771  BB->addSuccessor(sinkMBB);
772
773  //  copy0MBB:
774  //   %FalseValue = ...
775  //   # fallthrough to sinkMBB
776  BB = copy0MBB;
777
778  // Update machine-CFG edges
779  BB->addSuccessor(sinkMBB);
780
781  //  sinkMBB:
782  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
783  //  ...
784  BB = sinkMBB;
785  BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
786    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
787    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
788
789  delete MI;   // The pseudo instruction is gone now.
790  return BB;
791}
792
793//===----------------------------------------------------------------------===//
794// Instruction Selector Implementation
795//===----------------------------------------------------------------------===//
796
797//===--------------------------------------------------------------------===//
798/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
799/// instructions for SelectionDAG operations.
800///
801namespace {
802class SparcV8DAGToDAGISel : public SelectionDAGISel {
803  SparcV8TargetLowering V8Lowering;
804public:
805  SparcV8DAGToDAGISel(TargetMachine &TM)
806    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
807
808  SDOperand Select(SDOperand Op);
809
810  // Complex Pattern Selectors.
811  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
812  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
813
814  /// InstructionSelectBasicBlock - This callback is invoked by
815  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
816  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
817
818  virtual const char *getPassName() const {
819    return "PowerPC DAG->DAG Pattern Instruction Selection";
820  }
821
822  // Include the pieces autogenerated from the target description.
823#include "SparcV8GenDAGISel.inc"
824};
825}  // end anonymous namespace
826
827/// InstructionSelectBasicBlock - This callback is invoked by
828/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
829void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
830  DEBUG(BB->dump());
831
832  // Select target instructions for the DAG.
833  DAG.setRoot(Select(DAG.getRoot()));
834  CodeGenMap.clear();
835  DAG.RemoveDeadNodes();
836
837  // Emit machine code to BB.
838  ScheduleAndEmitDAG(DAG);
839}
840
841bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
842                                       SDOperand &Offset) {
843  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
844    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
845    Offset = CurDAG->getTargetConstant(0, MVT::i32);
846    return true;
847  }
848
849  if (Addr.getOpcode() == ISD::ADD) {
850    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
851      if (Predicate_simm13(CN)) {
852        if (FrameIndexSDNode *FIN =
853                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
854          // Constant offset from frame ref.
855          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
856        } else {
857          Base = Select(Addr.getOperand(0));
858        }
859        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
860        return true;
861      }
862    }
863    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
864      Base = Select(Addr.getOperand(1));
865      Offset = Addr.getOperand(0).getOperand(0);
866      return true;
867    }
868    if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
869      Base = Select(Addr.getOperand(0));
870      Offset = Addr.getOperand(1).getOperand(0);
871      return true;
872    }
873  }
874  Base = Select(Addr);
875  Offset = CurDAG->getTargetConstant(0, MVT::i32);
876  return true;
877}
878
879bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
880                                       SDOperand &R2) {
881  if (Addr.getOpcode() == ISD::FrameIndex) return false;
882  if (Addr.getOpcode() == ISD::ADD) {
883    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
884        Predicate_simm13(Addr.getOperand(1).Val))
885      return false;  // Let the reg+imm pattern catch this!
886    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
887        Addr.getOperand(1).getOpcode() == V8ISD::Lo)
888      return false;  // Let the reg+imm pattern catch this!
889    R1 = Select(Addr.getOperand(0));
890    R2 = Select(Addr.getOperand(1));
891    return true;
892  }
893
894  R1 = Select(Addr);
895  R2 = CurDAG->getRegister(V8::G0, MVT::i32);
896  return true;
897}
898
899SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
900  SDNode *N = Op.Val;
901  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
902      N->getOpcode() < V8ISD::FIRST_NUMBER)
903    return Op;   // Already selected.
904                 // If this has already been converted, use it.
905  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
906  if (CGMI != CodeGenMap.end()) return CGMI->second;
907
908  switch (N->getOpcode()) {
909  default: break;
910  case ISD::FrameIndex: {
911    int FI = cast<FrameIndexSDNode>(N)->getIndex();
912    if (N->hasOneUse())
913      return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
914                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
915                                  CurDAG->getTargetConstant(0, MVT::i32));
916    return CodeGenMap[Op] =
917      CurDAG->getTargetNode(V8::ADDri, MVT::i32,
918                            CurDAG->getTargetFrameIndex(FI, MVT::i32),
919                            CurDAG->getTargetConstant(0, MVT::i32));
920  }
921  case ISD::ADD_PARTS: {
922    SDOperand LHSL = Select(N->getOperand(0));
923    SDOperand LHSH = Select(N->getOperand(1));
924    SDOperand RHSL = Select(N->getOperand(2));
925    SDOperand RHSH = Select(N->getOperand(3));
926    // FIXME, handle immediate RHS.
927    SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
928                                          LHSL, RHSL);
929    SDOperand Hi  = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
930                                          Low.getValue(1));
931    CodeGenMap[SDOperand(N, 0)] = Low;
932    CodeGenMap[SDOperand(N, 1)] = Hi;
933    return Op.ResNo ? Hi : Low;
934  }
935  case ISD::SUB_PARTS: {
936    SDOperand LHSL = Select(N->getOperand(0));
937    SDOperand LHSH = Select(N->getOperand(1));
938    SDOperand RHSL = Select(N->getOperand(2));
939    SDOperand RHSH = Select(N->getOperand(3));
940    // FIXME, handle immediate RHS.
941    SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
942                                          LHSL, RHSL);
943    SDOperand Hi  = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
944                                          Low.getValue(1));
945    CodeGenMap[SDOperand(N, 0)] = Low;
946    CodeGenMap[SDOperand(N, 1)] = Hi;
947    return Op.ResNo ? Hi : Low;
948  }
949  case ISD::SDIV:
950  case ISD::UDIV: {
951    // FIXME: should use a custom expander to expose the SRA to the dag.
952    SDOperand DivLHS = Select(N->getOperand(0));
953    SDOperand DivRHS = Select(N->getOperand(1));
954
955    // Set the Y register to the high-part.
956    SDOperand TopPart;
957    if (N->getOpcode() == ISD::SDIV) {
958      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
959                                      CurDAG->getTargetConstant(31, MVT::i32));
960    } else {
961      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
962    }
963    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
964                                    CurDAG->getRegister(V8::G0, MVT::i32));
965
966    // FIXME: Handle div by immediate.
967    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
968    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
969  }
970  case ISD::MULHU:
971  case ISD::MULHS: {
972    // FIXME: Handle mul by immediate.
973    SDOperand MulLHS = Select(N->getOperand(0));
974    SDOperand MulRHS = Select(N->getOperand(1));
975    unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
976    SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
977                                          MulLHS, MulRHS);
978    // The high part is in the Y register.
979    return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
980  }
981  case ISD::CALL:
982    // FIXME: This is a workaround for a bug in tblgen.
983  { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
984    // Emits: (CALL:void (tglobaladdr:i32):$dst)
985    // Pattern complexity = 2  cost = 1
986    SDOperand N1 = N->getOperand(1);
987    if (N1.getOpcode() != ISD::TargetGlobalAddress &&
988        N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
989    SDOperand InFlag = SDOperand(0, 0);
990    SDOperand Chain = N->getOperand(0);
991    SDOperand Tmp0 = N1;
992    Chain = Select(Chain);
993    SDOperand Result;
994    if (N->getNumOperands() == 3) {
995      InFlag = Select(N->getOperand(2));
996      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
997                                     Chain, InFlag);
998    } else {
999      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1000                                     Chain);
1001    }
1002    Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
1003     CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
1004    return Result.getValue(Op.ResNo);
1005  }
1006    P47Fail:;
1007
1008  }
1009
1010  return SelectCode(Op);
1011}
1012
1013
1014/// createPPCISelDag - This pass converts a legalized DAG into a
1015/// PowerPC-specific DAG, ready for instruction scheduling.
1016///
1017FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1018  return new SparcV8DAGToDAGISel(TM);
1019}
1020