SparcISelDAGToDAG.cpp revision 4ee451de366474b9c228b4e5fa573795a715216d
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/CodeGen/SSARegMap.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Debug.h" 27#include <queue> 28#include <set> 29using namespace llvm; 30 31//===----------------------------------------------------------------------===// 32// TargetLowering Implementation 33//===----------------------------------------------------------------------===// 34 35namespace SPISD { 36 enum { 37 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 38 CMPICC, // Compare two GPR operands, set icc. 39 CMPFCC, // Compare two FP operands, set fcc. 40 BRICC, // Branch to dest on icc condition 41 BRFCC, // Branch to dest on fcc condition 42 SELECT_ICC, // Select between two values using the current ICC flags. 43 SELECT_FCC, // Select between two values using the current FCC flags. 44 45 Hi, Lo, // Hi/Lo operations, typically on a global address. 46 47 FTOI, // FP to Int within a FP register. 48 ITOF, // Int to FP within a FP register. 49 50 CALL, // A call instruction. 51 RET_FLAG // Return with a flag operand. 52 }; 53} 54 55/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 56/// condition. 57static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 58 switch (CC) { 59 default: assert(0 && "Unknown integer condition code!"); 60 case ISD::SETEQ: return SPCC::ICC_E; 61 case ISD::SETNE: return SPCC::ICC_NE; 62 case ISD::SETLT: return SPCC::ICC_L; 63 case ISD::SETGT: return SPCC::ICC_G; 64 case ISD::SETLE: return SPCC::ICC_LE; 65 case ISD::SETGE: return SPCC::ICC_GE; 66 case ISD::SETULT: return SPCC::ICC_CS; 67 case ISD::SETULE: return SPCC::ICC_LEU; 68 case ISD::SETUGT: return SPCC::ICC_GU; 69 case ISD::SETUGE: return SPCC::ICC_CC; 70 } 71} 72 73/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 74/// FCC condition. 75static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 76 switch (CC) { 77 default: assert(0 && "Unknown fp condition code!"); 78 case ISD::SETEQ: 79 case ISD::SETOEQ: return SPCC::FCC_E; 80 case ISD::SETNE: 81 case ISD::SETUNE: return SPCC::FCC_NE; 82 case ISD::SETLT: 83 case ISD::SETOLT: return SPCC::FCC_L; 84 case ISD::SETGT: 85 case ISD::SETOGT: return SPCC::FCC_G; 86 case ISD::SETLE: 87 case ISD::SETOLE: return SPCC::FCC_LE; 88 case ISD::SETGE: 89 case ISD::SETOGE: return SPCC::FCC_GE; 90 case ISD::SETULT: return SPCC::FCC_UL; 91 case ISD::SETULE: return SPCC::FCC_ULE; 92 case ISD::SETUGT: return SPCC::FCC_UG; 93 case ISD::SETUGE: return SPCC::FCC_UGE; 94 case ISD::SETUO: return SPCC::FCC_U; 95 case ISD::SETO: return SPCC::FCC_O; 96 case ISD::SETONE: return SPCC::FCC_LG; 97 case ISD::SETUEQ: return SPCC::FCC_UE; 98 } 99} 100 101namespace { 102 class SparcTargetLowering : public TargetLowering { 103 int VarArgsFrameOffset; // Frame offset to start of varargs area. 104 public: 105 SparcTargetLowering(TargetMachine &TM); 106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 107 108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 109 /// in Mask are known to be either zero or one and return them in the 110 /// KnownZero/KnownOne bitsets. 111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 112 uint64_t Mask, 113 uint64_t &KnownZero, 114 uint64_t &KnownOne, 115 const SelectionDAG &DAG, 116 unsigned Depth = 0) const; 117 118 virtual std::vector<SDOperand> 119 LowerArguments(Function &F, SelectionDAG &DAG); 120 virtual std::pair<SDOperand, SDOperand> 121 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 122 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 123 ArgListTy &Args, SelectionDAG &DAG); 124 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 125 MachineBasicBlock *MBB); 126 127 virtual const char *getTargetNodeName(unsigned Opcode) const; 128 }; 129} 130 131SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 132 : TargetLowering(TM) { 133 134 // Set up the register classes. 135 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 136 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 137 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 138 139 // Turn FP extload into load/fextend 140 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 141 142 // Custom legalize GlobalAddress nodes into LO/HI parts. 143 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 144 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 145 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 146 147 // Sparc doesn't have sext_inreg, replace them with shl/sra 148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 151 152 // Sparc has no REM or DIVREM operations. 153 setOperationAction(ISD::UREM, MVT::i32, Expand); 154 setOperationAction(ISD::SREM, MVT::i32, Expand); 155 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 157 158 // Custom expand fp<->sint 159 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 160 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 161 162 // Expand fp<->uint 163 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 164 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 165 166 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 167 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 168 169 // Sparc has no select or setcc: expand to SELECT_CC. 170 setOperationAction(ISD::SELECT, MVT::i32, Expand); 171 setOperationAction(ISD::SELECT, MVT::f32, Expand); 172 setOperationAction(ISD::SELECT, MVT::f64, Expand); 173 setOperationAction(ISD::SETCC, MVT::i32, Expand); 174 setOperationAction(ISD::SETCC, MVT::f32, Expand); 175 setOperationAction(ISD::SETCC, MVT::f64, Expand); 176 177 // Sparc doesn't have BRCOND either, it has BR_CC. 178 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 179 setOperationAction(ISD::BRIND, MVT::Other, Expand); 180 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 181 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 182 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 183 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 184 185 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 186 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 187 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 188 189 // SPARC has no intrinsics for these particular operations. 190 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 191 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 192 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 193 194 setOperationAction(ISD::FSIN , MVT::f64, Expand); 195 setOperationAction(ISD::FCOS , MVT::f64, Expand); 196 setOperationAction(ISD::FREM , MVT::f64, Expand); 197 setOperationAction(ISD::FSIN , MVT::f32, Expand); 198 setOperationAction(ISD::FCOS , MVT::f32, Expand); 199 setOperationAction(ISD::FREM , MVT::f32, Expand); 200 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 201 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 202 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 203 setOperationAction(ISD::ROTL , MVT::i32, Expand); 204 setOperationAction(ISD::ROTR , MVT::i32, Expand); 205 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 206 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 207 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 208 setOperationAction(ISD::FPOW , MVT::f64, Expand); 209 setOperationAction(ISD::FPOW , MVT::f32, Expand); 210 211 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 212 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 213 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 214 215 // We don't have line number support yet. 216 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 217 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 218 setOperationAction(ISD::LABEL, MVT::Other, Expand); 219 220 // RET must be custom lowered, to meet ABI requirements 221 setOperationAction(ISD::RET , MVT::Other, Custom); 222 223 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 224 setOperationAction(ISD::VASTART , MVT::Other, Custom); 225 // VAARG needs to be lowered to not do unaligned accesses for doubles. 226 setOperationAction(ISD::VAARG , MVT::Other, Custom); 227 228 // Use the default implementation. 229 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 230 setOperationAction(ISD::VAEND , MVT::Other, Expand); 231 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 232 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 233 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 234 235 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 236 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 237 238 setStackPointerRegisterToSaveRestore(SP::O6); 239 240 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 241 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 242 } 243 244 computeRegisterProperties(); 245} 246 247const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 248 switch (Opcode) { 249 default: return 0; 250 case SPISD::CMPICC: return "SPISD::CMPICC"; 251 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 252 case SPISD::BRICC: return "SPISD::BRICC"; 253 case SPISD::BRFCC: return "SPISD::BRFCC"; 254 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 255 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 256 case SPISD::Hi: return "SPISD::Hi"; 257 case SPISD::Lo: return "SPISD::Lo"; 258 case SPISD::FTOI: return "SPISD::FTOI"; 259 case SPISD::ITOF: return "SPISD::ITOF"; 260 case SPISD::CALL: return "SPISD::CALL"; 261 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 262 } 263} 264 265/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 266/// be zero. Op is expected to be a target specific node. Used by DAG 267/// combiner. 268void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 269 uint64_t Mask, 270 uint64_t &KnownZero, 271 uint64_t &KnownOne, 272 const SelectionDAG &DAG, 273 unsigned Depth) const { 274 uint64_t KnownZero2, KnownOne2; 275 KnownZero = KnownOne = 0; // Don't know anything. 276 277 switch (Op.getOpcode()) { 278 default: break; 279 case SPISD::SELECT_ICC: 280 case SPISD::SELECT_FCC: 281 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 282 Depth+1); 283 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 284 Depth+1); 285 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 286 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 287 288 // Only known if known in both the LHS and RHS. 289 KnownOne &= KnownOne2; 290 KnownZero &= KnownZero2; 291 break; 292 } 293} 294 295/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 296/// either one or two GPRs, including FP values. TODO: we should pass FP values 297/// in FP registers for fastcc functions. 298std::vector<SDOperand> 299SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 300 MachineFunction &MF = DAG.getMachineFunction(); 301 SSARegMap *RegMap = MF.getSSARegMap(); 302 std::vector<SDOperand> ArgValues; 303 304 static const unsigned ArgRegs[] = { 305 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 306 }; 307 308 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 309 unsigned ArgOffset = 68; 310 311 SDOperand Root = DAG.getRoot(); 312 std::vector<SDOperand> OutChains; 313 314 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 315 MVT::ValueType ObjectVT = getValueType(I->getType()); 316 317 switch (ObjectVT) { 318 default: assert(0 && "Unhandled argument type!"); 319 case MVT::i1: 320 case MVT::i8: 321 case MVT::i16: 322 case MVT::i32: 323 if (I->use_empty()) { // Argument is dead. 324 if (CurArgReg < ArgRegEnd) ++CurArgReg; 325 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 326 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 327 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 328 MF.addLiveIn(*CurArgReg++, VReg); 329 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 330 if (ObjectVT != MVT::i32) { 331 unsigned AssertOp = ISD::AssertSext; 332 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 333 DAG.getValueType(ObjectVT)); 334 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 335 } 336 ArgValues.push_back(Arg); 337 } else { 338 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 339 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 340 SDOperand Load; 341 if (ObjectVT == MVT::i32) { 342 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 343 } else { 344 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 345 346 // Sparc is big endian, so add an offset based on the ObjectVT. 347 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 348 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 349 DAG.getConstant(Offset, MVT::i32)); 350 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 351 NULL, 0, ObjectVT); 352 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 353 } 354 ArgValues.push_back(Load); 355 } 356 357 ArgOffset += 4; 358 break; 359 case MVT::f32: 360 if (I->use_empty()) { // Argument is dead. 361 if (CurArgReg < ArgRegEnd) ++CurArgReg; 362 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 363 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 364 // FP value is passed in an integer register. 365 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 366 MF.addLiveIn(*CurArgReg++, VReg); 367 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 368 369 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 370 ArgValues.push_back(Arg); 371 } else { 372 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 373 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 374 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 375 ArgValues.push_back(Load); 376 } 377 ArgOffset += 4; 378 break; 379 380 case MVT::i64: 381 case MVT::f64: 382 if (I->use_empty()) { // Argument is dead. 383 if (CurArgReg < ArgRegEnd) ++CurArgReg; 384 if (CurArgReg < ArgRegEnd) ++CurArgReg; 385 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 386 } else if (/* FIXME: Apparently this isn't safe?? */ 387 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 388 ((CurArgReg-ArgRegs) & 1) == 0) { 389 // If this is a double argument and the whole thing lives on the stack, 390 // and the argument is aligned, load the double straight from the stack. 391 // We can't do a load in cases like void foo([6ints], int,double), 392 // because the double wouldn't be aligned! 393 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 394 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 395 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 396 } else { 397 SDOperand HiVal; 398 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 399 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 400 MF.addLiveIn(*CurArgReg++, VRegHi); 401 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 402 } else { 403 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 404 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 405 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 406 } 407 408 SDOperand LoVal; 409 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 410 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 411 MF.addLiveIn(*CurArgReg++, VRegLo); 412 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 413 } else { 414 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 415 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 416 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 417 } 418 419 // Compose the two halves together into an i64 unit. 420 SDOperand WholeValue = 421 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 422 423 // If we want a double, do a bit convert. 424 if (ObjectVT == MVT::f64) 425 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 426 427 ArgValues.push_back(WholeValue); 428 } 429 ArgOffset += 8; 430 break; 431 } 432 } 433 434 // Store remaining ArgRegs to the stack if this is a varargs function. 435 if (F.getFunctionType()->isVarArg()) { 436 // Remember the vararg offset for the va_start implementation. 437 VarArgsFrameOffset = ArgOffset; 438 439 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 440 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 441 MF.addLiveIn(*CurArgReg, VReg); 442 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 443 444 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 445 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 446 447 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 448 ArgOffset += 4; 449 } 450 } 451 452 if (!OutChains.empty()) 453 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 454 &OutChains[0], OutChains.size())); 455 456 // Finally, inform the code generator which regs we return values in. 457 switch (getValueType(F.getReturnType())) { 458 default: assert(0 && "Unknown type!"); 459 case MVT::isVoid: break; 460 case MVT::i1: 461 case MVT::i8: 462 case MVT::i16: 463 case MVT::i32: 464 MF.addLiveOut(SP::I0); 465 break; 466 case MVT::i64: 467 MF.addLiveOut(SP::I0); 468 MF.addLiveOut(SP::I1); 469 break; 470 case MVT::f32: 471 MF.addLiveOut(SP::F0); 472 break; 473 case MVT::f64: 474 MF.addLiveOut(SP::D0); 475 break; 476 } 477 478 return ArgValues; 479} 480 481std::pair<SDOperand, SDOperand> 482SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 483 bool RetTyIsSigned, bool isVarArg, unsigned CC, 484 bool isTailCall, SDOperand Callee, 485 ArgListTy &Args, SelectionDAG &DAG) { 486 // Count the size of the outgoing arguments. 487 unsigned ArgsSize = 0; 488 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 489 switch (getValueType(Args[i].Ty)) { 490 default: assert(0 && "Unknown value type!"); 491 case MVT::i1: 492 case MVT::i8: 493 case MVT::i16: 494 case MVT::i32: 495 case MVT::f32: 496 ArgsSize += 4; 497 break; 498 case MVT::i64: 499 case MVT::f64: 500 ArgsSize += 8; 501 break; 502 } 503 } 504 if (ArgsSize > 4*6) 505 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 506 else 507 ArgsSize = 0; 508 509 // Keep stack frames 8-byte aligned. 510 ArgsSize = (ArgsSize+7) & ~7; 511 512 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 513 514 SDOperand StackPtr; 515 std::vector<SDOperand> Stores; 516 std::vector<SDOperand> RegValuesToPass; 517 unsigned ArgOffset = 68; 518 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 519 SDOperand Val = Args[i].Node; 520 MVT::ValueType ObjectVT = Val.getValueType(); 521 SDOperand ValToStore(0, 0); 522 unsigned ObjSize; 523 switch (ObjectVT) { 524 default: assert(0 && "Unhandled argument type!"); 525 case MVT::i1: 526 case MVT::i8: 527 case MVT::i16: { 528 // Promote the integer to 32-bits. If the input type is signed, use a 529 // sign extend, otherwise use a zero extend. 530 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 531 if (Args[i].isSExt) 532 ExtendKind = ISD::SIGN_EXTEND; 533 else if (Args[i].isZExt) 534 ExtendKind = ISD::ZERO_EXTEND; 535 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 536 // FALL THROUGH 537 } 538 case MVT::i32: 539 ObjSize = 4; 540 541 if (RegValuesToPass.size() >= 6) { 542 ValToStore = Val; 543 } else { 544 RegValuesToPass.push_back(Val); 545 } 546 break; 547 case MVT::f32: 548 ObjSize = 4; 549 if (RegValuesToPass.size() >= 6) { 550 ValToStore = Val; 551 } else { 552 // Convert this to a FP value in an int reg. 553 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 554 RegValuesToPass.push_back(Val); 555 } 556 break; 557 case MVT::f64: 558 ObjSize = 8; 559 // If we can store this directly into the outgoing slot, do so. We can 560 // do this when all ArgRegs are used and if the outgoing slot is aligned. 561 // FIXME: McGill/misr fails with this. 562 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 563 ValToStore = Val; 564 break; 565 } 566 567 // Otherwise, convert this to a FP value in int regs. 568 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 569 // FALL THROUGH 570 case MVT::i64: 571 ObjSize = 8; 572 if (RegValuesToPass.size() >= 6) { 573 ValToStore = Val; // Whole thing is passed in memory. 574 break; 575 } 576 577 // Split the value into top and bottom part. Top part goes in a reg. 578 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 579 DAG.getConstant(1, MVT::i32)); 580 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 581 DAG.getConstant(0, MVT::i32)); 582 RegValuesToPass.push_back(Hi); 583 584 if (RegValuesToPass.size() >= 6) { 585 ValToStore = Lo; 586 ArgOffset += 4; 587 ObjSize = 4; 588 } else { 589 RegValuesToPass.push_back(Lo); 590 } 591 break; 592 } 593 594 if (ValToStore.Val) { 595 if (!StackPtr.Val) { 596 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 597 } 598 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 599 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 600 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 601 } 602 ArgOffset += ObjSize; 603 } 604 605 // Emit all stores, make sure the occur before any copies into physregs. 606 if (!Stores.empty()) 607 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 608 609 static const unsigned ArgRegs[] = { 610 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 611 }; 612 613 // Build a sequence of copy-to-reg nodes chained together with token chain 614 // and flag operands which copy the outgoing args into O[0-5]. 615 SDOperand InFlag; 616 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 617 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 618 InFlag = Chain.getValue(1); 619 } 620 621 // If the callee is a GlobalAddress node (quite common, every direct call is) 622 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 623 // Likewise ExternalSymbol -> TargetExternalSymbol. 624 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 625 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 626 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 627 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 628 629 std::vector<MVT::ValueType> NodeTys; 630 NodeTys.push_back(MVT::Other); // Returns a chain 631 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 632 SDOperand Ops[] = { Chain, Callee, InFlag }; 633 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 634 InFlag = Chain.getValue(1); 635 636 MVT::ValueType RetTyVT = getValueType(RetTy); 637 SDOperand RetVal; 638 if (RetTyVT != MVT::isVoid) { 639 switch (RetTyVT) { 640 default: assert(0 && "Unknown value type to return!"); 641 case MVT::i1: 642 case MVT::i8: 643 case MVT::i16: { 644 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 645 Chain = RetVal.getValue(1); 646 647 // Add a note to keep track of whether it is sign or zero extended. 648 ISD::NodeType AssertKind = ISD::AssertZext; 649 if (RetTyIsSigned) 650 AssertKind = ISD::AssertSext; 651 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 652 DAG.getValueType(RetTyVT)); 653 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 654 break; 655 } 656 case MVT::i32: 657 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 658 Chain = RetVal.getValue(1); 659 break; 660 case MVT::f32: 661 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 662 Chain = RetVal.getValue(1); 663 break; 664 case MVT::f64: 665 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 666 Chain = RetVal.getValue(1); 667 break; 668 case MVT::i64: 669 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 670 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 671 Lo.getValue(2)); 672 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 673 Chain = Hi.getValue(1); 674 break; 675 } 676 } 677 678 Chain = DAG.getCALLSEQ_END(Chain, 679 DAG.getConstant(ArgsSize, getPointerTy()), 680 DAG.getConstant(0, getPointerTy()), 681 SDOperand()); 682 return std::make_pair(RetVal, Chain); 683} 684 685// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 686// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 687static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 688 ISD::CondCode CC, unsigned &SPCC) { 689 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 690 CC == ISD::SETNE && 691 ((LHS.getOpcode() == SPISD::SELECT_ICC && 692 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 693 (LHS.getOpcode() == SPISD::SELECT_FCC && 694 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 695 isa<ConstantSDNode>(LHS.getOperand(0)) && 696 isa<ConstantSDNode>(LHS.getOperand(1)) && 697 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 698 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 699 SDOperand CMPCC = LHS.getOperand(3); 700 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 701 LHS = CMPCC.getOperand(0); 702 RHS = CMPCC.getOperand(1); 703 } 704} 705 706 707SDOperand SparcTargetLowering:: 708LowerOperation(SDOperand Op, SelectionDAG &DAG) { 709 switch (Op.getOpcode()) { 710 default: assert(0 && "Should not custom lower this!"); 711 case ISD::GlobalTLSAddress: 712 assert(0 && "TLS not implemented for Sparc."); 713 case ISD::GlobalAddress: { 714 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 715 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 716 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 717 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 718 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 719 } 720 case ISD::ConstantPool: { 721 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 722 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 723 cast<ConstantPoolSDNode>(Op)->getAlignment()); 724 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 725 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 726 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 727 } 728 case ISD::FP_TO_SINT: 729 // Convert the fp value to integer in an FP register. 730 assert(Op.getValueType() == MVT::i32); 731 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 732 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 733 case ISD::SINT_TO_FP: { 734 assert(Op.getOperand(0).getValueType() == MVT::i32); 735 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 736 // Convert the int value to FP in an FP register. 737 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 738 } 739 case ISD::BR_CC: { 740 SDOperand Chain = Op.getOperand(0); 741 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 742 SDOperand LHS = Op.getOperand(2); 743 SDOperand RHS = Op.getOperand(3); 744 SDOperand Dest = Op.getOperand(4); 745 unsigned Opc, SPCC = ~0U; 746 747 // If this is a br_cc of a "setcc", and if the setcc got lowered into 748 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 749 LookThroughSetCC(LHS, RHS, CC, SPCC); 750 751 // Get the condition flag. 752 SDOperand CompareFlag; 753 if (LHS.getValueType() == MVT::i32) { 754 std::vector<MVT::ValueType> VTs; 755 VTs.push_back(MVT::i32); 756 VTs.push_back(MVT::Flag); 757 SDOperand Ops[2] = { LHS, RHS }; 758 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 759 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 760 Opc = SPISD::BRICC; 761 } else { 762 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 763 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 764 Opc = SPISD::BRFCC; 765 } 766 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 767 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 768 } 769 case ISD::SELECT_CC: { 770 SDOperand LHS = Op.getOperand(0); 771 SDOperand RHS = Op.getOperand(1); 772 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 773 SDOperand TrueVal = Op.getOperand(2); 774 SDOperand FalseVal = Op.getOperand(3); 775 unsigned Opc, SPCC = ~0U; 776 777 // If this is a select_cc of a "setcc", and if the setcc got lowered into 778 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 779 LookThroughSetCC(LHS, RHS, CC, SPCC); 780 781 SDOperand CompareFlag; 782 if (LHS.getValueType() == MVT::i32) { 783 std::vector<MVT::ValueType> VTs; 784 VTs.push_back(LHS.getValueType()); // subcc returns a value 785 VTs.push_back(MVT::Flag); 786 SDOperand Ops[2] = { LHS, RHS }; 787 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 788 Opc = SPISD::SELECT_ICC; 789 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 790 } else { 791 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 792 Opc = SPISD::SELECT_FCC; 793 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 794 } 795 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 796 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 797 } 798 case ISD::VASTART: { 799 // vastart just stores the address of the VarArgsFrameIndex slot into the 800 // memory location argument. 801 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 802 DAG.getRegister(SP::I6, MVT::i32), 803 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 804 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 805 return DAG.getStore(Op.getOperand(0), Offset, 806 Op.getOperand(1), SV->getValue(), SV->getOffset()); 807 } 808 case ISD::VAARG: { 809 SDNode *Node = Op.Val; 810 MVT::ValueType VT = Node->getValueType(0); 811 SDOperand InChain = Node->getOperand(0); 812 SDOperand VAListPtr = Node->getOperand(1); 813 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 814 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 815 SV->getValue(), SV->getOffset()); 816 // Increment the pointer, VAList, to the next vaarg 817 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 818 DAG.getConstant(MVT::getSizeInBits(VT)/8, 819 getPointerTy())); 820 // Store the incremented VAList to the legalized pointer 821 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 822 VAListPtr, SV->getValue(), SV->getOffset()); 823 // Load the actual argument out of the pointer VAList, unless this is an 824 // f64 load. 825 if (VT != MVT::f64) { 826 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 827 } else { 828 // Otherwise, load it as i64, then do a bitconvert. 829 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 830 std::vector<MVT::ValueType> Tys; 831 Tys.push_back(MVT::f64); 832 Tys.push_back(MVT::Other); 833 // Bit-Convert the value to f64. 834 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 835 V.getValue(1) }; 836 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 837 } 838 } 839 case ISD::DYNAMIC_STACKALLOC: { 840 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 841 SDOperand Size = Op.getOperand(1); // Legalize the size. 842 843 unsigned SPReg = SP::O6; 844 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 845 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 846 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 847 848 // The resultant pointer is actually 16 words from the bottom of the stack, 849 // to provide a register spill area. 850 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 851 DAG.getConstant(96, MVT::i32)); 852 std::vector<MVT::ValueType> Tys; 853 Tys.push_back(MVT::i32); 854 Tys.push_back(MVT::Other); 855 SDOperand Ops[2] = { NewVal, Chain }; 856 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 857 } 858 case ISD::RET: { 859 SDOperand Copy; 860 861 switch(Op.getNumOperands()) { 862 default: 863 assert(0 && "Do not know how to return this many arguments!"); 864 abort(); 865 case 1: 866 return SDOperand(); // ret void is legal 867 case 3: { 868 unsigned ArgReg; 869 switch(Op.getOperand(1).getValueType()) { 870 default: assert(0 && "Unknown type to return!"); 871 case MVT::i32: ArgReg = SP::I0; break; 872 case MVT::f32: ArgReg = SP::F0; break; 873 case MVT::f64: ArgReg = SP::D0; break; 874 } 875 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 876 SDOperand()); 877 break; 878 } 879 case 5: 880 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 881 SDOperand()); 882 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 883 break; 884 } 885 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 886 } 887 // Frame & Return address. Currently unimplemented 888 case ISD::RETURNADDR: break; 889 case ISD::FRAMEADDR: break; 890 } 891 return SDOperand(); 892} 893 894MachineBasicBlock * 895SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 896 MachineBasicBlock *BB) { 897 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 898 unsigned BROpcode; 899 unsigned CC; 900 // Figure out the conditional branch opcode to use for this select_cc. 901 switch (MI->getOpcode()) { 902 default: assert(0 && "Unknown SELECT_CC!"); 903 case SP::SELECT_CC_Int_ICC: 904 case SP::SELECT_CC_FP_ICC: 905 case SP::SELECT_CC_DFP_ICC: 906 BROpcode = SP::BCOND; 907 break; 908 case SP::SELECT_CC_Int_FCC: 909 case SP::SELECT_CC_FP_FCC: 910 case SP::SELECT_CC_DFP_FCC: 911 BROpcode = SP::FBCOND; 912 break; 913 } 914 915 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 916 917 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 918 // control-flow pattern. The incoming instruction knows the destination vreg 919 // to set, the condition code register to branch on, the true/false values to 920 // select between, and a branch opcode to use. 921 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 922 ilist<MachineBasicBlock>::iterator It = BB; 923 ++It; 924 925 // thisMBB: 926 // ... 927 // TrueVal = ... 928 // [f]bCC copy1MBB 929 // fallthrough --> copy0MBB 930 MachineBasicBlock *thisMBB = BB; 931 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 932 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 933 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 934 MachineFunction *F = BB->getParent(); 935 F->getBasicBlockList().insert(It, copy0MBB); 936 F->getBasicBlockList().insert(It, sinkMBB); 937 // Update machine-CFG edges by first adding all successors of the current 938 // block to the new block which will contain the Phi node for the select. 939 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 940 e = BB->succ_end(); i != e; ++i) 941 sinkMBB->addSuccessor(*i); 942 // Next, remove all successors of the current block, and add the true 943 // and fallthrough blocks as its successors. 944 while(!BB->succ_empty()) 945 BB->removeSuccessor(BB->succ_begin()); 946 BB->addSuccessor(copy0MBB); 947 BB->addSuccessor(sinkMBB); 948 949 // copy0MBB: 950 // %FalseValue = ... 951 // # fallthrough to sinkMBB 952 BB = copy0MBB; 953 954 // Update machine-CFG edges 955 BB->addSuccessor(sinkMBB); 956 957 // sinkMBB: 958 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 959 // ... 960 BB = sinkMBB; 961 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 962 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 963 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 964 965 delete MI; // The pseudo instruction is gone now. 966 return BB; 967} 968 969//===----------------------------------------------------------------------===// 970// Instruction Selector Implementation 971//===----------------------------------------------------------------------===// 972 973//===--------------------------------------------------------------------===// 974/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 975/// instructions for SelectionDAG operations. 976/// 977namespace { 978class SparcDAGToDAGISel : public SelectionDAGISel { 979 SparcTargetLowering Lowering; 980 981 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 982 /// make the right decision when generating code for different targets. 983 const SparcSubtarget &Subtarget; 984public: 985 SparcDAGToDAGISel(TargetMachine &TM) 986 : SelectionDAGISel(Lowering), Lowering(TM), 987 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 988 } 989 990 SDNode *Select(SDOperand Op); 991 992 // Complex Pattern Selectors. 993 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); 994 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, 995 SDOperand &Offset); 996 997 /// InstructionSelectBasicBlock - This callback is invoked by 998 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 999 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 1000 1001 virtual const char *getPassName() const { 1002 return "SPARC DAG->DAG Pattern Instruction Selection"; 1003 } 1004 1005 // Include the pieces autogenerated from the target description. 1006#include "SparcGenDAGISel.inc" 1007}; 1008} // end anonymous namespace 1009 1010/// InstructionSelectBasicBlock - This callback is invoked by 1011/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1012void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 1013 DEBUG(BB->dump()); 1014 1015 // Select target instructions for the DAG. 1016 DAG.setRoot(SelectRoot(DAG.getRoot())); 1017 DAG.RemoveDeadNodes(); 1018 1019 // Emit machine code to BB. 1020 ScheduleAndEmitDAG(DAG); 1021} 1022 1023bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, 1024 SDOperand &Base, SDOperand &Offset) { 1025 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1026 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1027 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1028 return true; 1029 } 1030 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1031 Addr.getOpcode() == ISD::TargetGlobalAddress) 1032 return false; // direct calls. 1033 1034 if (Addr.getOpcode() == ISD::ADD) { 1035 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1036 if (Predicate_simm13(CN)) { 1037 if (FrameIndexSDNode *FIN = 1038 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1039 // Constant offset from frame ref. 1040 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1041 } else { 1042 Base = Addr.getOperand(0); 1043 } 1044 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1045 return true; 1046 } 1047 } 1048 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1049 Base = Addr.getOperand(1); 1050 Offset = Addr.getOperand(0).getOperand(0); 1051 return true; 1052 } 1053 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1054 Base = Addr.getOperand(0); 1055 Offset = Addr.getOperand(1).getOperand(0); 1056 return true; 1057 } 1058 } 1059 Base = Addr; 1060 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1061 return true; 1062} 1063 1064bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, 1065 SDOperand &R1, SDOperand &R2) { 1066 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1067 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1068 Addr.getOpcode() == ISD::TargetGlobalAddress) 1069 return false; // direct calls. 1070 1071 if (Addr.getOpcode() == ISD::ADD) { 1072 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1073 Predicate_simm13(Addr.getOperand(1).Val)) 1074 return false; // Let the reg+imm pattern catch this! 1075 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1076 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1077 return false; // Let the reg+imm pattern catch this! 1078 R1 = Addr.getOperand(0); 1079 R2 = Addr.getOperand(1); 1080 return true; 1081 } 1082 1083 R1 = Addr; 1084 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1085 return true; 1086} 1087 1088SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1089 SDNode *N = Op.Val; 1090 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1091 N->getOpcode() < SPISD::FIRST_NUMBER) 1092 return NULL; // Already selected. 1093 1094 switch (N->getOpcode()) { 1095 default: break; 1096 case ISD::SDIV: 1097 case ISD::UDIV: { 1098 // FIXME: should use a custom expander to expose the SRA to the dag. 1099 SDOperand DivLHS = N->getOperand(0); 1100 SDOperand DivRHS = N->getOperand(1); 1101 AddToISelQueue(DivLHS); 1102 AddToISelQueue(DivRHS); 1103 1104 // Set the Y register to the high-part. 1105 SDOperand TopPart; 1106 if (N->getOpcode() == ISD::SDIV) { 1107 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1108 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1109 } else { 1110 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1111 } 1112 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1113 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1114 1115 // FIXME: Handle div by immediate. 1116 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1117 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1118 TopPart); 1119 } 1120 case ISD::MULHU: 1121 case ISD::MULHS: { 1122 // FIXME: Handle mul by immediate. 1123 SDOperand MulLHS = N->getOperand(0); 1124 SDOperand MulRHS = N->getOperand(1); 1125 AddToISelQueue(MulLHS); 1126 AddToISelQueue(MulRHS); 1127 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1128 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1129 MulLHS, MulRHS); 1130 // The high part is in the Y register. 1131 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1132 return NULL; 1133 } 1134 } 1135 1136 return SelectCode(Op); 1137} 1138 1139 1140/// createSparcISelDag - This pass converts a legalized DAG into a 1141/// SPARC-specific DAG, ready for instruction scheduling. 1142/// 1143FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1144 return new SparcDAGToDAGISel(TM); 1145} 1146