SparcISelDAGToDAG.cpp revision 53e884587bd4b56c14dc39600eb655e77ae7b905
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 112 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 113 114 // Turn FP extload into load/fextend 115 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 116 117 // Sparc has no select or setcc: expand to SELECT_CC. 118 setOperationAction(ISD::SELECT, MVT::i32, Expand); 119 setOperationAction(ISD::SELECT, MVT::f32, Expand); 120 setOperationAction(ISD::SELECT, MVT::f64, Expand); 121 setOperationAction(ISD::SETCC, MVT::i32, Expand); 122 setOperationAction(ISD::SETCC, MVT::f32, Expand); 123 setOperationAction(ISD::SETCC, MVT::f64, Expand); 124 125 // Sparc doesn't have BRCOND either, it has BR_CC. 126 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 127 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 128 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 129 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 130 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 131 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 132 133 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 134 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 135 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 136 137 // V8 has no intrinsics for these particular operations. 138 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 139 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 140 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 141 142 setOperationAction(ISD::FSIN , MVT::f64, Expand); 143 setOperationAction(ISD::FCOS , MVT::f64, Expand); 144 setOperationAction(ISD::FSIN , MVT::f32, Expand); 145 setOperationAction(ISD::FCOS , MVT::f32, Expand); 146 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 147 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 148 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 149 150 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 151 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 152 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 153 154 // We don't have line number support yet. 155 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 156 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 157 158 computeRegisterProperties(); 159} 160 161/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 162/// either one or two GPRs, including FP values. TODO: we should pass FP values 163/// in FP registers for fastcc functions. 164std::vector<SDOperand> 165SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 166 MachineFunction &MF = DAG.getMachineFunction(); 167 SSARegMap *RegMap = MF.getSSARegMap(); 168 std::vector<SDOperand> ArgValues; 169 170 static const unsigned ArgRegs[] = { 171 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 172 }; 173 174 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 175 unsigned ArgOffset = 68; 176 177 SDOperand Root = DAG.getRoot(); 178 std::vector<SDOperand> OutChains; 179 180 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 181 MVT::ValueType ObjectVT = getValueType(I->getType()); 182 183 switch (ObjectVT) { 184 default: assert(0 && "Unhandled argument type!"); 185 case MVT::i1: 186 case MVT::i8: 187 case MVT::i16: 188 case MVT::i32: 189 if (I->use_empty()) { // Argument is dead. 190 if (CurArgReg < ArgRegEnd) ++CurArgReg; 191 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 192 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 193 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 194 MF.addLiveIn(*CurArgReg++, VReg); 195 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 196 if (ObjectVT != MVT::i32) { 197 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 198 : ISD::AssertZext; 199 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 200 DAG.getValueType(ObjectVT)); 201 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 202 } 203 ArgValues.push_back(Arg); 204 } else { 205 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 206 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 207 SDOperand Load; 208 if (ObjectVT == MVT::i32) { 209 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 210 } else { 211 unsigned LoadOp = 212 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 213 214 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 215 DAG.getSrcValue(0), ObjectVT); 216 } 217 ArgValues.push_back(Load); 218 } 219 220 ArgOffset += 4; 221 break; 222 case MVT::f32: 223 if (I->use_empty()) { // Argument is dead. 224 if (CurArgReg < ArgRegEnd) ++CurArgReg; 225 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 226 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 227 // FP value is passed in an integer register. 228 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 229 MF.addLiveIn(*CurArgReg++, VReg); 230 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 231 232 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 233 ArgValues.push_back(Arg); 234 } 235 ArgOffset += 4; 236 break; 237 238 case MVT::i64: 239 case MVT::f64: 240 if (I->use_empty()) { // Argument is dead. 241 if (CurArgReg < ArgRegEnd) ++CurArgReg; 242 if (CurArgReg < ArgRegEnd) ++CurArgReg; 243 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 244 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 245 ((CurArgReg-ArgRegs) & 1) == 0) { 246 // If this is a double argument and the whole thing lives on the stack, 247 // and the argument is aligned, load the double straight from the stack. 248 // We can't do a load in cases like void foo([6ints], int,double), 249 // because the double wouldn't be aligned! 250 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 251 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 252 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 253 DAG.getSrcValue(0))); 254 } else { 255 SDOperand HiVal; 256 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 257 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 258 MF.addLiveIn(*CurArgReg++, VRegHi); 259 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 260 } else { 261 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 262 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 263 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 264 } 265 266 SDOperand LoVal; 267 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 268 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 269 MF.addLiveIn(*CurArgReg++, VRegLo); 270 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 271 } else { 272 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 273 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 274 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 275 } 276 277 // Compose the two halves together into an i64 unit. 278 SDOperand WholeValue = 279 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 280 281 // If we want a double, do a bit convert. 282 if (ObjectVT == MVT::f64) 283 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 284 285 ArgValues.push_back(WholeValue); 286 } 287 ArgOffset += 8; 288 break; 289 } 290 } 291 292 // Store remaining ArgRegs to the stack if this is a varargs function. 293 if (F.getFunctionType()->isVarArg()) { 294 // Remember the vararg offset for the va_start implementation. 295 VarArgsFrameOffset = ArgOffset; 296 297 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 298 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 299 MF.addLiveIn(*CurArgReg, VReg); 300 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 301 302 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 303 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 304 305 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 306 Arg, FIPtr, DAG.getSrcValue(0))); 307 ArgOffset += 4; 308 } 309 } 310 311 if (!OutChains.empty()) 312 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 313 314 // Finally, inform the code generator which regs we return values in. 315 switch (getValueType(F.getReturnType())) { 316 default: assert(0 && "Unknown type!"); 317 case MVT::isVoid: break; 318 case MVT::i1: 319 case MVT::i8: 320 case MVT::i16: 321 case MVT::i32: 322 MF.addLiveOut(V8::I0); 323 break; 324 case MVT::i64: 325 MF.addLiveOut(V8::I0); 326 MF.addLiveOut(V8::I1); 327 break; 328 case MVT::f32: 329 MF.addLiveOut(V8::F0); 330 break; 331 case MVT::f64: 332 MF.addLiveOut(V8::D0); 333 break; 334 } 335 336 return ArgValues; 337} 338 339std::pair<SDOperand, SDOperand> 340SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 341 bool isVarArg, unsigned CC, 342 bool isTailCall, SDOperand Callee, 343 ArgListTy &Args, SelectionDAG &DAG) { 344 MachineFunction &MF = DAG.getMachineFunction(); 345 // Count the size of the outgoing arguments. 346 unsigned ArgsSize = 0; 347 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 348 switch (getValueType(Args[i].second)) { 349 default: assert(0 && "Unknown value type!"); 350 case MVT::i1: 351 case MVT::i8: 352 case MVT::i16: 353 case MVT::i32: 354 case MVT::f32: 355 ArgsSize += 4; 356 break; 357 case MVT::i64: 358 case MVT::f64: 359 ArgsSize += 8; 360 break; 361 } 362 } 363 if (ArgsSize > 4*6) 364 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 365 else 366 ArgsSize = 0; 367 368 // Keep stack frames 8-byte aligned. 369 ArgsSize = (ArgsSize+7) & ~7; 370 371 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 372 DAG.getConstant(ArgsSize, getPointerTy())); 373 374 SDOperand StackPtr, NullSV; 375 std::vector<SDOperand> Stores; 376 std::vector<SDOperand> RegValuesToPass; 377 unsigned ArgOffset = 68; 378 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 379 SDOperand Val = Args[i].first; 380 MVT::ValueType ObjectVT = Val.getValueType(); 381 SDOperand ValToStore; 382 unsigned ObjSize; 383 switch (ObjectVT) { 384 default: assert(0 && "Unhandled argument type!"); 385 case MVT::i1: 386 case MVT::i8: 387 case MVT::i16: 388 // Promote the integer to 32-bits. If the input type is signed, use a 389 // sign extend, otherwise use a zero extend. 390 if (Args[i].second->isSigned()) 391 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 392 else 393 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 394 // FALL THROUGH 395 case MVT::i32: 396 ObjSize = 4; 397 398 if (RegValuesToPass.size() >= 6) { 399 ValToStore = Val; 400 } else { 401 RegValuesToPass.push_back(Val); 402 } 403 break; 404 case MVT::f32: 405 ObjSize = 4; 406 if (RegValuesToPass.size() >= 6) { 407 ValToStore = Val; 408 } else { 409 // Convert this to a FP value in an int reg. 410 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 411 RegValuesToPass.push_back(Val); 412 } 413 break; 414 case MVT::f64: 415 ObjSize = 8; 416 // If we can store this directly into the outgoing slot, do so. We can 417 // do this when all ArgRegs are used and if the outgoing slot is aligned. 418 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 419 ValToStore = Val; 420 break; 421 } 422 423 // Otherwise, convert this to a FP value in int regs. 424 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 425 // FALL THROUGH 426 case MVT::i64: 427 ObjSize = 8; 428 if (RegValuesToPass.size() >= 6) { 429 ValToStore = Val; // Whole thing is passed in memory. 430 break; 431 } 432 433 // Split the value into top and bottom part. Top part goes in a reg. 434 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 435 DAG.getConstant(1, MVT::i32)); 436 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 437 DAG.getConstant(0, MVT::i32)); 438 RegValuesToPass.push_back(Hi); 439 440 if (RegValuesToPass.size() >= 6) { 441 ValToStore = Lo; 442 ArgOffset += 4; 443 ObjSize = 4; 444 } else { 445 RegValuesToPass.push_back(Lo); 446 } 447 break; 448 } 449 450 if (ValToStore.Val) { 451 if (!StackPtr.Val) { 452 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 453 NullSV = DAG.getSrcValue(NULL); 454 } 455 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 456 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 457 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 458 ValToStore, PtrOff, NullSV)); 459 } 460 ArgOffset += ObjSize; 461 } 462 463 // Emit all stores, make sure the occur before any copies into physregs. 464 if (!Stores.empty()) 465 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 466 467 static const unsigned ArgRegs[] = { 468 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 469 }; 470 471 // Build a sequence of copy-to-reg nodes chained together with token chain 472 // and flag operands which copy the outgoing args into O[0-5]. 473 SDOperand InFlag; 474 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 475 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 476 InFlag = Chain.getValue(1); 477 } 478 479 std::vector<MVT::ValueType> RetVals; 480 RetVals.push_back(MVT::Other); 481 RetVals.push_back(MVT::Flag); 482 483 // If the callee is a GlobalAddress node (quite common, every direct call is) 484 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 485 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 486 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 487 488 std::vector<MVT::ValueType> NodeTys; 489 NodeTys.push_back(MVT::Other); // Returns a chain 490 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 491 if (InFlag.Val) 492 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 493 else 494 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 495 InFlag = Chain.getValue(1); 496 497 MVT::ValueType RetTyVT = getValueType(RetTy); 498 SDOperand RetVal; 499 if (RetTyVT != MVT::isVoid) { 500 switch (RetTyVT) { 501 default: assert(0 && "Unknown value type to return!"); 502 case MVT::i1: 503 case MVT::i8: 504 case MVT::i16: 505 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 506 Chain = RetVal.getValue(1); 507 508 // Add a note to keep track of whether it is sign or zero extended. 509 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 510 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 511 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 512 break; 513 case MVT::i32: 514 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 515 Chain = RetVal.getValue(1); 516 break; 517 case MVT::f32: 518 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 519 Chain = RetVal.getValue(1); 520 break; 521 case MVT::f64: 522 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 523 Chain = RetVal.getValue(1); 524 break; 525 case MVT::i64: 526 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 527 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 528 Lo.getValue(2)); 529 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 530 Chain = Hi.getValue(1); 531 break; 532 } 533 } 534 535 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 536 DAG.getConstant(ArgsSize, getPointerTy())); 537 538 return std::make_pair(RetVal, Chain); 539} 540 541SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 542 SelectionDAG &DAG) { 543 SDOperand Copy; 544 switch (Op.getValueType()) { 545 default: assert(0 && "Unknown type to return!"); 546 case MVT::i32: 547 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 548 break; 549 case MVT::f32: 550 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 551 break; 552 case MVT::f64: 553 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 554 break; 555 case MVT::i64: 556 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 557 DAG.getConstant(1, MVT::i32)); 558 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 559 DAG.getConstant(0, MVT::i32)); 560 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 561 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 562 break; 563 } 564 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 565} 566 567SDOperand SparcV8TargetLowering:: 568LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 569 SelectionDAG &DAG) { 570 571 assert(0 && "Unimp"); 572 abort(); 573} 574 575std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 576LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 577 const Type *ArgTy, SelectionDAG &DAG) { 578 assert(0 && "Unimp"); 579 abort(); 580} 581 582std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 583LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 584 SelectionDAG &DAG) { 585 assert(0 && "Unimp"); 586 abort(); 587} 588 589SDOperand SparcV8TargetLowering:: 590LowerOperation(SDOperand Op, SelectionDAG &DAG) { 591 switch (Op.getOpcode()) { 592 default: assert(0 && "Should not custom lower this!"); 593 case ISD::GlobalAddress: { 594 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 595 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 596 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 597 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 598 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 599 } 600 case ISD::ConstantPool: { 601 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 602 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 603 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 604 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 605 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 606 } 607 case ISD::FP_TO_SINT: 608 // Convert the fp value to integer in an FP register. 609 assert(Op.getValueType() == MVT::i32); 610 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 611 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 612 case ISD::SINT_TO_FP: { 613 assert(Op.getOperand(0).getValueType() == MVT::i32); 614 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op); 615 // Convert the int value to FP in an FP register. 616 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op); 617 } 618 case ISD::BR_CC: { 619 SDOperand Chain = Op.getOperand(0); 620 SDOperand CC = Op.getOperand(1); 621 SDOperand LHS = Op.getOperand(2); 622 SDOperand RHS = Op.getOperand(3); 623 SDOperand Dest = Op.getOperand(4); 624 625 // Get the condition flag. 626 if (LHS.getValueType() == MVT::i32) { 627 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); 628 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 629 } else { 630 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 631 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 632 } 633 } 634 case ISD::SELECT_CC: { 635 SDOperand LHS = Op.getOperand(0); 636 SDOperand RHS = Op.getOperand(1); 637 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 638 SDOperand TrueVal = Op.getOperand(2); 639 SDOperand FalseVal = Op.getOperand(3); 640 641 unsigned Opc; 642 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 643 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); 644 645 Opc = LHS.getValueType() == MVT::i32 ? 646 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 647 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 648 DAG.getConstant(CC, MVT::i32), CompareFlag); 649 } 650 } 651} 652 653MachineBasicBlock * 654SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 655 MachineBasicBlock *BB) { 656 unsigned BROpcode; 657 // Figure out the conditional branch opcode to use for this select_cc. 658 switch (MI->getOpcode()) { 659 default: assert(0 && "Unknown SELECT_CC!"); 660 case V8::SELECT_CC_Int_ICC: 661 case V8::SELECT_CC_FP_ICC: 662 case V8::SELECT_CC_DFP_ICC: 663 // Integer compare. 664 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 665 default: assert(0 && "Unknown integer condition code!"); 666 case ISD::SETEQ: BROpcode = V8::BE; break; 667 case ISD::SETNE: BROpcode = V8::BNE; break; 668 case ISD::SETLT: BROpcode = V8::BL; break; 669 case ISD::SETGT: BROpcode = V8::BG; break; 670 case ISD::SETLE: BROpcode = V8::BLE; break; 671 case ISD::SETGE: BROpcode = V8::BGE; break; 672 case ISD::SETULT: BROpcode = V8::BCS; break; 673 case ISD::SETULE: BROpcode = V8::BLEU; break; 674 case ISD::SETUGT: BROpcode = V8::BGU; break; 675 case ISD::SETUGE: BROpcode = V8::BCC; break; 676 } 677 break; 678 case V8::SELECT_CC_Int_FCC: 679 case V8::SELECT_CC_FP_FCC: 680 case V8::SELECT_CC_DFP_FCC: 681 // FP compare. 682 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 683 default: assert(0 && "Unknown fp condition code!"); 684 case ISD::SETEQ: BROpcode = V8::FBE; break; 685 case ISD::SETNE: BROpcode = V8::FBNE; break; 686 case ISD::SETLT: BROpcode = V8::FBL; break; 687 case ISD::SETGT: BROpcode = V8::FBG; break; 688 case ISD::SETLE: BROpcode = V8::FBLE; break; 689 case ISD::SETGE: BROpcode = V8::FBGE; break; 690 case ISD::SETULT: BROpcode = V8::FBUL; break; 691 case ISD::SETULE: BROpcode = V8::FBULE; break; 692 case ISD::SETUGT: BROpcode = V8::FBUG; break; 693 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 694 case ISD::SETUO: BROpcode = V8::FBU; break; 695 case ISD::SETO: BROpcode = V8::FBO; break; 696 case ISD::SETONE: BROpcode = V8::FBLG; break; 697 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 698 } 699 break; 700 } 701 702 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 703 // control-flow pattern. The incoming instruction knows the destination vreg 704 // to set, the condition code register to branch on, the true/false values to 705 // select between, and a branch opcode to use. 706 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 707 ilist<MachineBasicBlock>::iterator It = BB; 708 ++It; 709 710 // thisMBB: 711 // ... 712 // TrueVal = ... 713 // [f]bCC copy1MBB 714 // fallthrough --> copy0MBB 715 MachineBasicBlock *thisMBB = BB; 716 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 717 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 718 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 719 MachineFunction *F = BB->getParent(); 720 F->getBasicBlockList().insert(It, copy0MBB); 721 F->getBasicBlockList().insert(It, sinkMBB); 722 // Update machine-CFG edges 723 BB->addSuccessor(copy0MBB); 724 BB->addSuccessor(sinkMBB); 725 726 // copy0MBB: 727 // %FalseValue = ... 728 // # fallthrough to sinkMBB 729 BB = copy0MBB; 730 731 // Update machine-CFG edges 732 BB->addSuccessor(sinkMBB); 733 734 // sinkMBB: 735 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 736 // ... 737 BB = sinkMBB; 738 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 739 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 740 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 741 742 delete MI; // The pseudo instruction is gone now. 743 return BB; 744} 745 746//===----------------------------------------------------------------------===// 747// Instruction Selector Implementation 748//===----------------------------------------------------------------------===// 749 750//===--------------------------------------------------------------------===// 751/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 752/// instructions for SelectionDAG operations. 753/// 754namespace { 755class SparcV8DAGToDAGISel : public SelectionDAGISel { 756 SparcV8TargetLowering V8Lowering; 757public: 758 SparcV8DAGToDAGISel(TargetMachine &TM) 759 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 760 761 SDOperand Select(SDOperand Op); 762 763 // Complex Pattern Selectors. 764 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 765 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 766 767 /// InstructionSelectBasicBlock - This callback is invoked by 768 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 769 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 770 771 virtual const char *getPassName() const { 772 return "PowerPC DAG->DAG Pattern Instruction Selection"; 773 } 774 775 // Include the pieces autogenerated from the target description. 776#include "SparcV8GenDAGISel.inc" 777}; 778} // end anonymous namespace 779 780/// InstructionSelectBasicBlock - This callback is invoked by 781/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 782void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 783 DEBUG(BB->dump()); 784 785 // Select target instructions for the DAG. 786 DAG.setRoot(Select(DAG.getRoot())); 787 CodeGenMap.clear(); 788 DAG.RemoveDeadNodes(); 789 790 // Emit machine code to BB. 791 ScheduleAndEmitDAG(DAG); 792} 793 794bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 795 SDOperand &Offset) { 796 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 797 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 798 Offset = CurDAG->getTargetConstant(0, MVT::i32); 799 return true; 800 } 801 802 if (Addr.getOpcode() == ISD::ADD) { 803 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 804 if (Predicate_simm13(CN)) { 805 if (FrameIndexSDNode *FIN = 806 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 807 // Constant offset from frame ref. 808 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 809 } else { 810 Base = Select(Addr.getOperand(0)); 811 } 812 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 813 return true; 814 } 815 } 816 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 817 Base = Select(Addr.getOperand(1)); 818 Offset = Addr.getOperand(0).getOperand(0); 819 return true; 820 } 821 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 822 Base = Select(Addr.getOperand(0)); 823 Offset = Addr.getOperand(1).getOperand(0); 824 return true; 825 } 826 } 827 Base = Select(Addr); 828 Offset = CurDAG->getTargetConstant(0, MVT::i32); 829 return true; 830} 831 832bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 833 SDOperand &R2) { 834 if (Addr.getOpcode() == ISD::FrameIndex) return false; 835 if (Addr.getOpcode() == ISD::ADD) { 836 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 837 Predicate_simm13(Addr.getOperand(1).Val)) 838 return false; // Let the reg+imm pattern catch this! 839 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 840 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 841 return false; // Let the reg+imm pattern catch this! 842 R1 = Select(Addr.getOperand(0)); 843 R2 = Select(Addr.getOperand(1)); 844 return true; 845 } 846 847 R1 = Select(Addr); 848 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 849 return true; 850} 851 852SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 853 SDNode *N = Op.Val; 854 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 855 N->getOpcode() < V8ISD::FIRST_NUMBER) 856 return Op; // Already selected. 857 // If this has already been converted, use it. 858 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 859 if (CGMI != CodeGenMap.end()) return CGMI->second; 860 861 switch (N->getOpcode()) { 862 default: break; 863 case ISD::Register: return Op; 864 case ISD::FrameIndex: { 865 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 866 if (N->hasOneUse()) 867 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 868 CurDAG->getTargetFrameIndex(FI, MVT::i32), 869 CurDAG->getTargetConstant(0, MVT::i32)); 870 return CodeGenMap[Op] = 871 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 872 CurDAG->getTargetFrameIndex(FI, MVT::i32), 873 CurDAG->getTargetConstant(0, MVT::i32)); 874 } 875 case V8ISD::CMPICC: { 876 // FIXME: Handle compare with immediate. 877 SDOperand LHS = Select(N->getOperand(0)); 878 SDOperand RHS = Select(N->getOperand(1)); 879 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 880 LHS, RHS); 881 return CodeGenMap[Op] = Result.getValue(1); 882 } 883 case ISD::ADD_PARTS: { 884 SDOperand LHSL = Select(N->getOperand(0)); 885 SDOperand LHSH = Select(N->getOperand(1)); 886 SDOperand RHSL = Select(N->getOperand(2)); 887 SDOperand RHSH = Select(N->getOperand(3)); 888 // FIXME, handle immediate RHS. 889 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 890 LHSL, RHSL); 891 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 892 Low.getValue(1)); 893 CodeGenMap[SDOperand(N, 0)] = Low; 894 CodeGenMap[SDOperand(N, 1)] = Hi; 895 return Op.ResNo ? Hi : Low; 896 } 897 case ISD::SUB_PARTS: { 898 SDOperand LHSL = Select(N->getOperand(0)); 899 SDOperand LHSH = Select(N->getOperand(1)); 900 SDOperand RHSL = Select(N->getOperand(2)); 901 SDOperand RHSH = Select(N->getOperand(3)); 902 // FIXME, handle immediate RHS. 903 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 904 LHSL, RHSL); 905 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 906 Low.getValue(1)); 907 CodeGenMap[SDOperand(N, 0)] = Low; 908 CodeGenMap[SDOperand(N, 1)] = Hi; 909 return Op.ResNo ? Hi : Low; 910 } 911 case ISD::SDIV: 912 case ISD::UDIV: { 913 // FIXME: should use a custom expander to expose the SRA to the dag. 914 SDOperand DivLHS = Select(N->getOperand(0)); 915 SDOperand DivRHS = Select(N->getOperand(1)); 916 917 // Set the Y register to the high-part. 918 SDOperand TopPart; 919 if (N->getOpcode() == ISD::SDIV) { 920 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 921 CurDAG->getTargetConstant(31, MVT::i32)); 922 } else { 923 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 924 } 925 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 926 CurDAG->getRegister(V8::G0, MVT::i32)); 927 928 // FIXME: Handle div by immediate. 929 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 930 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 931 } 932 case ISD::MULHU: 933 case ISD::MULHS: { 934 // FIXME: Handle mul by immediate. 935 SDOperand MulLHS = Select(N->getOperand(0)); 936 SDOperand MulRHS = Select(N->getOperand(1)); 937 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 938 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 939 MulLHS, MulRHS); 940 // The high part is in the Y register. 941 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 942 } 943 case ISD::CALL: 944 // FIXME: This is a workaround for a bug in tblgen. 945 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 946 // Emits: (CALL:void (tglobaladdr:i32):$dst) 947 // Pattern complexity = 2 cost = 1 948 SDOperand N1 = N->getOperand(1); 949 if (N1.getOpcode() != ISD::TargetGlobalAddress && 950 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 951 SDOperand InFlag = SDOperand(0, 0); 952 SDOperand Chain = N->getOperand(0); 953 SDOperand Tmp0 = N1; 954 Chain = Select(Chain); 955 SDOperand Result; 956 if (N->getNumOperands() == 3) { 957 InFlag = Select(N->getOperand(2)); 958 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 959 Chain, InFlag); 960 } else { 961 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 962 Chain); 963 } 964 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 965 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 966 return Result.getValue(Op.ResNo); 967 } 968 P47Fail:; 969 970 } 971 972 return SelectCode(Op); 973} 974 975 976/// createPPCISelDag - This pass converts a legalized DAG into a 977/// PowerPC-specific DAG, ready for instruction scheduling. 978/// 979FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 980 return new SparcV8DAGToDAGISel(TM); 981} 982