SparcISelDAGToDAG.cpp revision 6a2e7ac0b6647a409394e58b385e579ea62b5cba 
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the SPARC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcTargetMachine.h"
15#include "llvm/CodeGen/SelectionDAGISel.h"
16#include "llvm/IR/Intrinsics.h"
17#include "llvm/Support/Compiler.h"
18#include "llvm/Support/Debug.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/raw_ostream.h"
21using namespace llvm;
22
23//===----------------------------------------------------------------------===//
24// Instruction Selector Implementation
25//===----------------------------------------------------------------------===//
26
27//===--------------------------------------------------------------------===//
28/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
29/// instructions for SelectionDAG operations.
30///
31namespace {
32class SparcDAGToDAGISel : public SelectionDAGISel {
33  /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
34  /// make the right decision when generating code for different targets.
35  const SparcSubtarget &Subtarget;
36  SparcTargetMachine& TM;
37public:
38  explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
39    : SelectionDAGISel(tm),
40      Subtarget(tm.getSubtarget<SparcSubtarget>()),
41      TM(tm) {
42  }
43
44  SDNode *Select(SDNode *N);
45
46  // Complex Pattern Selectors.
47  bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
48  bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
49
50  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
51  /// inline asm expressions.
52  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
53                                            char ConstraintCode,
54                                            std::vector<SDValue> &OutOps);
55
56  virtual const char *getPassName() const {
57    return "SPARC DAG->DAG Pattern Instruction Selection";
58  }
59
60  // Include the pieces autogenerated from the target description.
61#include "SparcGenDAGISel.inc"
62
63private:
64  SDNode* getGlobalBaseReg();
65};
66}  // end anonymous namespace
67
68SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
69  unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
70  return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
71}
72
73bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
74                                     SDValue &Base, SDValue &Offset) {
75  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
76    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy());
77    Offset = CurDAG->getTargetConstant(0, MVT::i32);
78    return true;
79  }
80  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
81      Addr.getOpcode() == ISD::TargetGlobalAddress)
82    return false;  // direct calls.
83
84  if (Addr.getOpcode() == ISD::ADD) {
85    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
86      if (isInt<13>(CN->getSExtValue())) {
87        if (FrameIndexSDNode *FIN =
88                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
89          // Constant offset from frame ref.
90          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
91                                             TLI->getPointerTy());
92        } else {
93          Base = Addr.getOperand(0);
94        }
95        Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
96        return true;
97      }
98    }
99    if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
100      Base = Addr.getOperand(1);
101      Offset = Addr.getOperand(0).getOperand(0);
102      return true;
103    }
104    if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
105      Base = Addr.getOperand(0);
106      Offset = Addr.getOperand(1).getOperand(0);
107      return true;
108    }
109  }
110  Base = Addr;
111  Offset = CurDAG->getTargetConstant(0, MVT::i32);
112  return true;
113}
114
115bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
116  if (Addr.getOpcode() == ISD::FrameIndex) return false;
117  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
118      Addr.getOpcode() == ISD::TargetGlobalAddress)
119    return false;  // direct calls.
120
121  if (Addr.getOpcode() == ISD::ADD) {
122    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
123      if (isInt<13>(CN->getSExtValue()))
124        return false;  // Let the reg+imm pattern catch this!
125    if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
126        Addr.getOperand(1).getOpcode() == SPISD::Lo)
127      return false;  // Let the reg+imm pattern catch this!
128    R1 = Addr.getOperand(0);
129    R2 = Addr.getOperand(1);
130    return true;
131  }
132
133  R1 = Addr;
134  R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy());
135  return true;
136}
137
138SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
139  SDLoc dl(N);
140  if (N->isMachineOpcode())
141    return NULL;   // Already selected.
142
143  switch (N->getOpcode()) {
144  default: break;
145  case SPISD::GLOBAL_BASE_REG:
146    return getGlobalBaseReg();
147
148  case ISD::SDIV:
149  case ISD::UDIV: {
150    // sdivx / udivx handle 64-bit divides.
151    if (N->getValueType(0) == MVT::i64)
152      break;
153    // FIXME: should use a custom expander to expose the SRA to the dag.
154    SDValue DivLHS = N->getOperand(0);
155    SDValue DivRHS = N->getOperand(1);
156
157    // Set the Y register to the high-part.
158    SDValue TopPart;
159    if (N->getOpcode() == ISD::SDIV) {
160      TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
161                                   CurDAG->getTargetConstant(31, MVT::i32)), 0);
162    } else {
163      TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
164    }
165    TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
166                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
167
168    // FIXME: Handle div by immediate.
169    unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
170    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
171                                TopPart);
172  }
173  case ISD::MULHU:
174  case ISD::MULHS: {
175    // FIXME: Handle mul by immediate.
176    SDValue MulLHS = N->getOperand(0);
177    SDValue MulRHS = N->getOperand(1);
178    unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
179    SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
180                                         MulLHS, MulRHS);
181    // The high part is in the Y register.
182    return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
183  }
184  }
185
186  return SelectCode(N);
187}
188
189
190/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
191/// inline asm expressions.
192bool
193SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
194                                                char ConstraintCode,
195                                                std::vector<SDValue> &OutOps) {
196  SDValue Op0, Op1;
197  switch (ConstraintCode) {
198  default: return true;
199  case 'm':   // memory
200   if (!SelectADDRrr(Op, Op0, Op1))
201     SelectADDRri(Op, Op0, Op1);
202   break;
203  }
204
205  OutOps.push_back(Op0);
206  OutOps.push_back(Op1);
207  return false;
208}
209
210/// createSparcISelDag - This pass converts a legalized DAG into a
211/// SPARC-specific DAG, ready for instruction scheduling.
212///
213FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
214  return new SparcDAGToDAGISel(TM);
215}
216