SparcISelDAGToDAG.cpp revision 7558b0e80c058c148ef9f45220bbbe6bc8a146dd 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Support/Debug.h"
26#include <iostream>
27using namespace llvm;
28
29//===----------------------------------------------------------------------===//
30// TargetLowering Implementation
31//===----------------------------------------------------------------------===//
32
33namespace V8ISD {
34  enum {
35    FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36    CMPICC,   // Compare two GPR operands, set icc.
37    CMPFCC,   // Compare two FP operands, set fcc.
38    BRICC,    // Branch to dest on icc condition
39    BRFCC,    // Branch to dest on fcc condition
40
41    Hi, Lo,   // Hi/Lo operations, typically on a global address.
42
43    FTOI,     // FP to Int within a FP register.
44    ITOF,     // Int to FP within a FP register.
45
46    SELECT_ICC, // Select between two values using the current ICC flags.
47    SELECT_FCC, // Select between two values using the current FCC flags.
48
49    RET_FLAG,   // Return with a flag operand.
50  };
51}
52
53namespace {
54  class SparcV8TargetLowering : public TargetLowering {
55    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
56  public:
57    SparcV8TargetLowering(TargetMachine &TM);
58    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59    virtual std::vector<SDOperand>
60      LowerArguments(Function &F, SelectionDAG &DAG);
61    virtual std::pair<SDOperand, SDOperand>
62      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
63                  unsigned CC,
64                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
65                  SelectionDAG &DAG);
66
67    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
68                                    SelectionDAG &DAG);
69    virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
70                                   Value *VAListV, SelectionDAG &DAG);
71    virtual std::pair<SDOperand,SDOperand>
72      LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
73                 const Type *ArgTy, SelectionDAG &DAG);
74    virtual std::pair<SDOperand, SDOperand>
75      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
76                              SelectionDAG &DAG);
77    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
78                                                       MachineBasicBlock *MBB);
79
80    virtual const char *getTargetNodeName(unsigned Opcode) const;
81  };
82}
83
84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
85  : TargetLowering(TM) {
86
87  // Set up the register classes.
88  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
89  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
90  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
91
92  // Custom legalize GlobalAddress nodes into LO/HI parts.
93  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
95
96  // Sparc doesn't have sext_inreg, replace them with shl/sra
97  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
98  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
99  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
100
101  // Sparc has no REM operation.
102  setOperationAction(ISD::UREM, MVT::i32, Expand);
103  setOperationAction(ISD::SREM, MVT::i32, Expand);
104
105  // Custom expand fp<->sint
106  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
107  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
108
109  // Expand fp<->uint
110  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
111  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
112
113  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
114  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
115
116  // Turn FP extload into load/fextend
117  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
118
119  // Sparc has no select or setcc: expand to SELECT_CC.
120  setOperationAction(ISD::SELECT, MVT::i32, Expand);
121  setOperationAction(ISD::SELECT, MVT::f32, Expand);
122  setOperationAction(ISD::SELECT, MVT::f64, Expand);
123  setOperationAction(ISD::SETCC, MVT::i32, Expand);
124  setOperationAction(ISD::SETCC, MVT::f32, Expand);
125  setOperationAction(ISD::SETCC, MVT::f64, Expand);
126
127  // Sparc doesn't have BRCOND either, it has BR_CC.
128  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
130  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
131  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
132  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
133  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
134
135  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
136  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
138
139  // V8 has no intrinsics for these particular operations.
140  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
141  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
142  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
143
144  setOperationAction(ISD::FSIN , MVT::f64, Expand);
145  setOperationAction(ISD::FCOS , MVT::f64, Expand);
146  setOperationAction(ISD::FSIN , MVT::f32, Expand);
147  setOperationAction(ISD::FCOS , MVT::f32, Expand);
148  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
149  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
150  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
151  setOperationAction(ISD::ROTL , MVT::i32, Expand);
152  setOperationAction(ISD::ROTR , MVT::i32, Expand);
153  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
154
155  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
156  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
157  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
158
159  // We don't have line number support yet.
160  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
161  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
162  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
163
164  // Expand these to their default code.
165  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
166  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
167  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
168
169  setSchedulingPreference(SchedulingForLatency);
170  setStackPointerRegisterToSaveRestore(V8::O6);
171
172  computeRegisterProperties();
173}
174
175const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
176  switch (Opcode) {
177  default: return 0;
178  case V8ISD::CMPICC:     return "V8ISD::CMPICC";
179  case V8ISD::CMPFCC:     return "V8ISD::CMPFCC";
180  case V8ISD::BRICC:      return "V8ISD::BRICC";
181  case V8ISD::BRFCC:      return "V8ISD::BRFCC";
182  case V8ISD::Hi:         return "V8ISD::Hi";
183  case V8ISD::Lo:         return "V8ISD::Lo";
184  case V8ISD::FTOI:       return "V8ISD::FTOI";
185  case V8ISD::ITOF:       return "V8ISD::ITOF";
186  case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
187  case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
188  case V8ISD::RET_FLAG:   return "V8ISD::RET_FLAG";
189  }
190}
191
192/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
193/// either one or two GPRs, including FP values.  TODO: we should pass FP values
194/// in FP registers for fastcc functions.
195std::vector<SDOperand>
196SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
197  MachineFunction &MF = DAG.getMachineFunction();
198  SSARegMap *RegMap = MF.getSSARegMap();
199  std::vector<SDOperand> ArgValues;
200
201  static const unsigned ArgRegs[] = {
202    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
203  };
204
205  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
206  unsigned ArgOffset = 68;
207
208  SDOperand Root = DAG.getRoot();
209  std::vector<SDOperand> OutChains;
210
211  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
212    MVT::ValueType ObjectVT = getValueType(I->getType());
213
214    switch (ObjectVT) {
215    default: assert(0 && "Unhandled argument type!");
216    case MVT::i1:
217    case MVT::i8:
218    case MVT::i16:
219    case MVT::i32:
220      if (I->use_empty()) {                // Argument is dead.
221        if (CurArgReg < ArgRegEnd) ++CurArgReg;
222        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
223      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
224        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
225        MF.addLiveIn(*CurArgReg++, VReg);
226        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
227        if (ObjectVT != MVT::i32) {
228          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
229                                                       : ISD::AssertZext;
230          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
231                            DAG.getValueType(ObjectVT));
232          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
233        }
234        ArgValues.push_back(Arg);
235      } else {
236        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
237        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
238        SDOperand Load;
239        if (ObjectVT == MVT::i32) {
240          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
241        } else {
242          unsigned LoadOp =
243            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
244
245          // Sparc is big endian, so add an offset based on the ObjectVT.
246          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
247          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
248                              DAG.getConstant(Offset, MVT::i32));
249          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
250                                DAG.getSrcValue(0), ObjectVT);
251          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
252        }
253        ArgValues.push_back(Load);
254      }
255
256      ArgOffset += 4;
257      break;
258    case MVT::f32:
259      if (I->use_empty()) {                // Argument is dead.
260        if (CurArgReg < ArgRegEnd) ++CurArgReg;
261        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
262      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
263        // FP value is passed in an integer register.
264        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
265        MF.addLiveIn(*CurArgReg++, VReg);
266        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
267
268        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
269        ArgValues.push_back(Arg);
270      } else {
271        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
272        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
273        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
274        ArgValues.push_back(Load);
275      }
276      ArgOffset += 4;
277      break;
278
279    case MVT::i64:
280    case MVT::f64:
281      if (I->use_empty()) {                // Argument is dead.
282        if (CurArgReg < ArgRegEnd) ++CurArgReg;
283        if (CurArgReg < ArgRegEnd) ++CurArgReg;
284        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
285      } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
286                 ((CurArgReg-ArgRegs) & 1) == 0) {
287        // If this is a double argument and the whole thing lives on the stack,
288        // and the argument is aligned, load the double straight from the stack.
289        // We can't do a load in cases like void foo([6ints], int,double),
290        // because the double wouldn't be aligned!
291        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
292        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
293        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
294                                        DAG.getSrcValue(0)));
295      } else {
296        SDOperand HiVal;
297        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
298          unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
299          MF.addLiveIn(*CurArgReg++, VRegHi);
300          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
301        } else {
302          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
303          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
304          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
305        }
306
307        SDOperand LoVal;
308        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
309          unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
310          MF.addLiveIn(*CurArgReg++, VRegLo);
311          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
312        } else {
313          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
314          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
315          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
316        }
317
318        // Compose the two halves together into an i64 unit.
319        SDOperand WholeValue =
320          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
321
322        // If we want a double, do a bit convert.
323        if (ObjectVT == MVT::f64)
324          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
325
326        ArgValues.push_back(WholeValue);
327      }
328      ArgOffset += 8;
329      break;
330    }
331  }
332
333  // Store remaining ArgRegs to the stack if this is a varargs function.
334  if (F.getFunctionType()->isVarArg()) {
335    // Remember the vararg offset for the va_start implementation.
336    VarArgsFrameOffset = ArgOffset;
337
338    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
339      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
340      MF.addLiveIn(*CurArgReg, VReg);
341      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
342
343      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
344      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
345
346      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
347                                      Arg, FIPtr, DAG.getSrcValue(0)));
348      ArgOffset += 4;
349    }
350  }
351
352  if (!OutChains.empty())
353    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
354
355  // Finally, inform the code generator which regs we return values in.
356  switch (getValueType(F.getReturnType())) {
357  default: assert(0 && "Unknown type!");
358  case MVT::isVoid: break;
359  case MVT::i1:
360  case MVT::i8:
361  case MVT::i16:
362  case MVT::i32:
363    MF.addLiveOut(V8::I0);
364    break;
365  case MVT::i64:
366    MF.addLiveOut(V8::I0);
367    MF.addLiveOut(V8::I1);
368    break;
369  case MVT::f32:
370    MF.addLiveOut(V8::F0);
371    break;
372  case MVT::f64:
373    MF.addLiveOut(V8::D0);
374    break;
375  }
376
377  return ArgValues;
378}
379
380std::pair<SDOperand, SDOperand>
381SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
382                                   bool isVarArg, unsigned CC,
383                                   bool isTailCall, SDOperand Callee,
384                                   ArgListTy &Args, SelectionDAG &DAG) {
385  MachineFunction &MF = DAG.getMachineFunction();
386  // Count the size of the outgoing arguments.
387  unsigned ArgsSize = 0;
388  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
389    switch (getValueType(Args[i].second)) {
390    default: assert(0 && "Unknown value type!");
391    case MVT::i1:
392    case MVT::i8:
393    case MVT::i16:
394    case MVT::i32:
395    case MVT::f32:
396      ArgsSize += 4;
397      break;
398    case MVT::i64:
399    case MVT::f64:
400      ArgsSize += 8;
401      break;
402    }
403  }
404  if (ArgsSize > 4*6)
405    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
406  else
407    ArgsSize = 0;
408
409  // Keep stack frames 8-byte aligned.
410  ArgsSize = (ArgsSize+7) & ~7;
411
412  Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
413                      DAG.getConstant(ArgsSize, getPointerTy()));
414
415  SDOperand StackPtr, NullSV;
416  std::vector<SDOperand> Stores;
417  std::vector<SDOperand> RegValuesToPass;
418  unsigned ArgOffset = 68;
419  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
420    SDOperand Val = Args[i].first;
421    MVT::ValueType ObjectVT = Val.getValueType();
422    SDOperand ValToStore(0, 0);
423    unsigned ObjSize;
424    switch (ObjectVT) {
425    default: assert(0 && "Unhandled argument type!");
426    case MVT::i1:
427    case MVT::i8:
428    case MVT::i16:
429      // Promote the integer to 32-bits.  If the input type is signed, use a
430      // sign extend, otherwise use a zero extend.
431      if (Args[i].second->isSigned())
432        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
433      else
434        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
435      // FALL THROUGH
436    case MVT::i32:
437      ObjSize = 4;
438
439      if (RegValuesToPass.size() >= 6) {
440        ValToStore = Val;
441      } else {
442        RegValuesToPass.push_back(Val);
443      }
444      break;
445    case MVT::f32:
446      ObjSize = 4;
447      if (RegValuesToPass.size() >= 6) {
448        ValToStore = Val;
449      } else {
450        // Convert this to a FP value in an int reg.
451        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
452        RegValuesToPass.push_back(Val);
453      }
454      break;
455    case MVT::f64:
456      ObjSize = 8;
457      // If we can store this directly into the outgoing slot, do so.  We can
458      // do this when all ArgRegs are used and if the outgoing slot is aligned.
459      // FIXME: McGill/misr fails with this.
460      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
461        ValToStore = Val;
462        break;
463      }
464
465      // Otherwise, convert this to a FP value in int regs.
466      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
467      // FALL THROUGH
468    case MVT::i64:
469      ObjSize = 8;
470      if (RegValuesToPass.size() >= 6) {
471        ValToStore = Val;    // Whole thing is passed in memory.
472        break;
473      }
474
475      // Split the value into top and bottom part.  Top part goes in a reg.
476      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
477                                 DAG.getConstant(1, MVT::i32));
478      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
479                                 DAG.getConstant(0, MVT::i32));
480      RegValuesToPass.push_back(Hi);
481
482      if (RegValuesToPass.size() >= 6) {
483        ValToStore = Lo;
484        ArgOffset += 4;
485        ObjSize = 4;
486      } else {
487        RegValuesToPass.push_back(Lo);
488      }
489      break;
490    }
491
492    if (ValToStore.Val) {
493      if (!StackPtr.Val) {
494        StackPtr = DAG.getRegister(V8::O6, MVT::i32);
495        NullSV = DAG.getSrcValue(NULL);
496      }
497      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
498      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
499      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
500                                   ValToStore, PtrOff, NullSV));
501    }
502    ArgOffset += ObjSize;
503  }
504
505  // Emit all stores, make sure the occur before any copies into physregs.
506  if (!Stores.empty())
507    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
508
509  static const unsigned ArgRegs[] = {
510    V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
511  };
512
513  // Build a sequence of copy-to-reg nodes chained together with token chain
514  // and flag operands which copy the outgoing args into O[0-5].
515  SDOperand InFlag;
516  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
517    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
518    InFlag = Chain.getValue(1);
519  }
520
521  // If the callee is a GlobalAddress node (quite common, every direct call is)
522  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
523  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
524    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
525
526  std::vector<MVT::ValueType> NodeTys;
527  NodeTys.push_back(MVT::Other);   // Returns a chain
528  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
529  if (InFlag.Val)
530    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
531  else
532    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
533  InFlag = Chain.getValue(1);
534
535  MVT::ValueType RetTyVT = getValueType(RetTy);
536  SDOperand RetVal;
537  if (RetTyVT != MVT::isVoid) {
538    switch (RetTyVT) {
539    default: assert(0 && "Unknown value type to return!");
540    case MVT::i1:
541    case MVT::i8:
542    case MVT::i16:
543      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
544      Chain = RetVal.getValue(1);
545
546      // Add a note to keep track of whether it is sign or zero extended.
547      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
548                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
549      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
550      break;
551    case MVT::i32:
552      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
553      Chain = RetVal.getValue(1);
554      break;
555    case MVT::f32:
556      RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
557      Chain = RetVal.getValue(1);
558      break;
559    case MVT::f64:
560      RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
561      Chain = RetVal.getValue(1);
562      break;
563    case MVT::i64:
564      SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
565      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
566                                        Lo.getValue(2));
567      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
568      Chain = Hi.getValue(1);
569      break;
570    }
571  }
572
573  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
574                      DAG.getConstant(ArgsSize, getPointerTy()));
575
576  return std::make_pair(RetVal, Chain);
577}
578
579SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
580                                               SelectionDAG &DAG) {
581  SDOperand Copy;
582  switch (Op.getValueType()) {
583  default: assert(0 && "Unknown type to return!");
584  case MVT::i32:
585    Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
586    break;
587  case MVT::f32:
588    Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
589    break;
590  case MVT::f64:
591    Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
592    break;
593  case MVT::i64:
594    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
595                               DAG.getConstant(1, MVT::i32));
596    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
597                               DAG.getConstant(0, MVT::i32));
598    Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
599    Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
600    break;
601  }
602  return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
603}
604
605SDOperand SparcV8TargetLowering::
606LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
607             SelectionDAG &DAG) {
608
609  SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
610                                 DAG.getRegister(V8::I6, MVT::i32),
611                                 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
612  return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
613                     VAListP, DAG.getSrcValue(VAListV));
614}
615
616std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
617LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
618           const Type *ArgTy, SelectionDAG &DAG) {
619  // Load the pointer out of the valist.
620  SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
621                              VAListP, DAG.getSrcValue(VAListV));
622  MVT::ValueType ArgVT = getValueType(ArgTy);
623  SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
624                              Ptr, DAG.getSrcValue(NULL));
625  // Increment the pointer.
626  Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
627                    DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
628  // Store it back to the valist.
629  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
630                      VAListP, DAG.getSrcValue(VAListV));
631  return std::make_pair(Val, Chain);
632}
633
634std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
635LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
636                        SelectionDAG &DAG) {
637  assert(0 && "Unimp");
638  abort();
639}
640
641SDOperand SparcV8TargetLowering::
642LowerOperation(SDOperand Op, SelectionDAG &DAG) {
643  switch (Op.getOpcode()) {
644  default: assert(0 && "Should not custom lower this!");
645  case ISD::GlobalAddress: {
646    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
647    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
648    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
649    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
650    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
651  }
652  case ISD::ConstantPool: {
653    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
654    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
655    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
656    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
657    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
658  }
659  case ISD::FP_TO_SINT:
660    // Convert the fp value to integer in an FP register.
661    assert(Op.getValueType() == MVT::i32);
662    Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
663    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
664  case ISD::SINT_TO_FP: {
665    assert(Op.getOperand(0).getValueType() == MVT::i32);
666    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
667    // Convert the int value to FP in an FP register.
668    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
669  }
670  case ISD::BR_CC: {
671    SDOperand Chain = Op.getOperand(0);
672    SDOperand CC = Op.getOperand(1);
673    SDOperand LHS = Op.getOperand(2);
674    SDOperand RHS = Op.getOperand(3);
675    SDOperand Dest = Op.getOperand(4);
676
677    // Get the condition flag.
678    if (LHS.getValueType() == MVT::i32) {
679      std::vector<MVT::ValueType> VTs;
680      VTs.push_back(MVT::i32);
681      VTs.push_back(MVT::Flag);
682      std::vector<SDOperand> Ops;
683      Ops.push_back(LHS);
684      Ops.push_back(RHS);
685      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
686      return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
687    } else {
688      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
689      return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
690    }
691  }
692  case ISD::SELECT_CC: {
693    SDOperand LHS = Op.getOperand(0);
694    SDOperand RHS = Op.getOperand(1);
695    unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
696    SDOperand TrueVal = Op.getOperand(2);
697    SDOperand FalseVal = Op.getOperand(3);
698
699    SDOperand CompareFlag;
700    unsigned Opc;
701    if (LHS.getValueType() == MVT::i32) {
702      std::vector<MVT::ValueType> VTs;
703      VTs.push_back(LHS.getValueType());   // subcc returns a value
704      VTs.push_back(MVT::Flag);
705      std::vector<SDOperand> Ops;
706      Ops.push_back(LHS);
707      Ops.push_back(RHS);
708      CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
709      Opc = V8ISD::SELECT_ICC;
710    } else {
711      CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
712      Opc = V8ISD::SELECT_FCC;
713    }
714    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
715                       DAG.getConstant(CC, MVT::i32), CompareFlag);
716  }
717  }
718}
719
720MachineBasicBlock *
721SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
722                                               MachineBasicBlock *BB) {
723  unsigned BROpcode;
724  // Figure out the conditional branch opcode to use for this select_cc.
725  switch (MI->getOpcode()) {
726  default: assert(0 && "Unknown SELECT_CC!");
727  case V8::SELECT_CC_Int_ICC:
728  case V8::SELECT_CC_FP_ICC:
729  case V8::SELECT_CC_DFP_ICC:
730    // Integer compare.
731    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
732    default: assert(0 && "Unknown integer condition code!");
733    case ISD::SETEQ:  BROpcode = V8::BE; break;
734    case ISD::SETNE:  BROpcode = V8::BNE; break;
735    case ISD::SETLT:  BROpcode = V8::BL; break;
736    case ISD::SETGT:  BROpcode = V8::BG; break;
737    case ISD::SETLE:  BROpcode = V8::BLE; break;
738    case ISD::SETGE:  BROpcode = V8::BGE; break;
739    case ISD::SETULT: BROpcode = V8::BCS; break;
740    case ISD::SETULE: BROpcode = V8::BLEU; break;
741    case ISD::SETUGT: BROpcode = V8::BGU; break;
742    case ISD::SETUGE: BROpcode = V8::BCC; break;
743    }
744    break;
745  case V8::SELECT_CC_Int_FCC:
746  case V8::SELECT_CC_FP_FCC:
747  case V8::SELECT_CC_DFP_FCC:
748    // FP compare.
749    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
750    default: assert(0 && "Unknown fp condition code!");
751    case ISD::SETEQ:  BROpcode = V8::FBE; break;
752    case ISD::SETNE:  BROpcode = V8::FBNE; break;
753    case ISD::SETLT:  BROpcode = V8::FBL; break;
754    case ISD::SETGT:  BROpcode = V8::FBG; break;
755    case ISD::SETLE:  BROpcode = V8::FBLE; break;
756    case ISD::SETGE:  BROpcode = V8::FBGE; break;
757    case ISD::SETULT: BROpcode = V8::FBUL; break;
758    case ISD::SETULE: BROpcode = V8::FBULE; break;
759    case ISD::SETUGT: BROpcode = V8::FBUG; break;
760    case ISD::SETUGE: BROpcode = V8::FBUGE; break;
761    case ISD::SETUO:  BROpcode = V8::FBU; break;
762    case ISD::SETO:   BROpcode = V8::FBO; break;
763    case ISD::SETONE: BROpcode = V8::FBLG; break;
764    case ISD::SETUEQ: BROpcode = V8::FBUE; break;
765    }
766    break;
767  }
768
769  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
770  // control-flow pattern.  The incoming instruction knows the destination vreg
771  // to set, the condition code register to branch on, the true/false values to
772  // select between, and a branch opcode to use.
773  const BasicBlock *LLVM_BB = BB->getBasicBlock();
774  ilist<MachineBasicBlock>::iterator It = BB;
775  ++It;
776
777  //  thisMBB:
778  //  ...
779  //   TrueVal = ...
780  //   [f]bCC copy1MBB
781  //   fallthrough --> copy0MBB
782  MachineBasicBlock *thisMBB = BB;
783  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
784  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
785  BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
786  MachineFunction *F = BB->getParent();
787  F->getBasicBlockList().insert(It, copy0MBB);
788  F->getBasicBlockList().insert(It, sinkMBB);
789  // Update machine-CFG edges
790  BB->addSuccessor(copy0MBB);
791  BB->addSuccessor(sinkMBB);
792
793  //  copy0MBB:
794  //   %FalseValue = ...
795  //   # fallthrough to sinkMBB
796  BB = copy0MBB;
797
798  // Update machine-CFG edges
799  BB->addSuccessor(sinkMBB);
800
801  //  sinkMBB:
802  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
803  //  ...
804  BB = sinkMBB;
805  BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
806    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
807    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
808
809  delete MI;   // The pseudo instruction is gone now.
810  return BB;
811}
812
813//===----------------------------------------------------------------------===//
814// Instruction Selector Implementation
815//===----------------------------------------------------------------------===//
816
817//===--------------------------------------------------------------------===//
818/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
819/// instructions for SelectionDAG operations.
820///
821namespace {
822class SparcV8DAGToDAGISel : public SelectionDAGISel {
823  SparcV8TargetLowering V8Lowering;
824public:
825  SparcV8DAGToDAGISel(TargetMachine &TM)
826    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
827
828  SDOperand Select(SDOperand Op);
829
830  // Complex Pattern Selectors.
831  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
832  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
833
834  /// InstructionSelectBasicBlock - This callback is invoked by
835  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
836  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
837
838  virtual const char *getPassName() const {
839    return "PowerPC DAG->DAG Pattern Instruction Selection";
840  }
841
842  // Include the pieces autogenerated from the target description.
843#include "SparcV8GenDAGISel.inc"
844};
845}  // end anonymous namespace
846
847/// InstructionSelectBasicBlock - This callback is invoked by
848/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
849void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
850  DEBUG(BB->dump());
851
852  // Select target instructions for the DAG.
853  DAG.setRoot(Select(DAG.getRoot()));
854  CodeGenMap.clear();
855  DAG.RemoveDeadNodes();
856
857  // Emit machine code to BB.
858  ScheduleAndEmitDAG(DAG);
859}
860
861bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
862                                       SDOperand &Offset) {
863  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
864    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
865    Offset = CurDAG->getTargetConstant(0, MVT::i32);
866    return true;
867  }
868
869  if (Addr.getOpcode() == ISD::ADD) {
870    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
871      if (Predicate_simm13(CN)) {
872        if (FrameIndexSDNode *FIN =
873                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
874          // Constant offset from frame ref.
875          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
876        } else {
877          Base = Select(Addr.getOperand(0));
878        }
879        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
880        return true;
881      }
882    }
883    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
884      Base = Select(Addr.getOperand(1));
885      Offset = Addr.getOperand(0).getOperand(0);
886      return true;
887    }
888    if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
889      Base = Select(Addr.getOperand(0));
890      Offset = Addr.getOperand(1).getOperand(0);
891      return true;
892    }
893  }
894  Base = Select(Addr);
895  Offset = CurDAG->getTargetConstant(0, MVT::i32);
896  return true;
897}
898
899bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
900                                       SDOperand &R2) {
901  if (Addr.getOpcode() == ISD::FrameIndex) return false;
902  if (Addr.getOpcode() == ISD::ADD) {
903    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
904        Predicate_simm13(Addr.getOperand(1).Val))
905      return false;  // Let the reg+imm pattern catch this!
906    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
907        Addr.getOperand(1).getOpcode() == V8ISD::Lo)
908      return false;  // Let the reg+imm pattern catch this!
909    R1 = Select(Addr.getOperand(0));
910    R2 = Select(Addr.getOperand(1));
911    return true;
912  }
913
914  R1 = Select(Addr);
915  R2 = CurDAG->getRegister(V8::G0, MVT::i32);
916  return true;
917}
918
919SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
920  SDNode *N = Op.Val;
921  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
922      N->getOpcode() < V8ISD::FIRST_NUMBER)
923    return Op;   // Already selected.
924                 // If this has already been converted, use it.
925  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
926  if (CGMI != CodeGenMap.end()) return CGMI->second;
927
928  switch (N->getOpcode()) {
929  default: break;
930  case ISD::FrameIndex: {
931    int FI = cast<FrameIndexSDNode>(N)->getIndex();
932    if (N->hasOneUse())
933      return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
934                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
935                                  CurDAG->getTargetConstant(0, MVT::i32));
936    return CodeGenMap[Op] =
937      CurDAG->getTargetNode(V8::ADDri, MVT::i32,
938                            CurDAG->getTargetFrameIndex(FI, MVT::i32),
939                            CurDAG->getTargetConstant(0, MVT::i32));
940  }
941  case ISD::ADD_PARTS: {
942    SDOperand LHSL = Select(N->getOperand(0));
943    SDOperand LHSH = Select(N->getOperand(1));
944    SDOperand RHSL = Select(N->getOperand(2));
945    SDOperand RHSH = Select(N->getOperand(3));
946    // FIXME, handle immediate RHS.
947    SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
948                                          LHSL, RHSL);
949    SDOperand Hi  = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
950                                          Low.getValue(1));
951    CodeGenMap[SDOperand(N, 0)] = Low;
952    CodeGenMap[SDOperand(N, 1)] = Hi;
953    return Op.ResNo ? Hi : Low;
954  }
955  case ISD::SUB_PARTS: {
956    SDOperand LHSL = Select(N->getOperand(0));
957    SDOperand LHSH = Select(N->getOperand(1));
958    SDOperand RHSL = Select(N->getOperand(2));
959    SDOperand RHSH = Select(N->getOperand(3));
960    // FIXME, handle immediate RHS.
961    SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
962                                          LHSL, RHSL);
963    SDOperand Hi  = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
964                                          Low.getValue(1));
965    CodeGenMap[SDOperand(N, 0)] = Low;
966    CodeGenMap[SDOperand(N, 1)] = Hi;
967    return Op.ResNo ? Hi : Low;
968  }
969  case ISD::SDIV:
970  case ISD::UDIV: {
971    // FIXME: should use a custom expander to expose the SRA to the dag.
972    SDOperand DivLHS = Select(N->getOperand(0));
973    SDOperand DivRHS = Select(N->getOperand(1));
974
975    // Set the Y register to the high-part.
976    SDOperand TopPart;
977    if (N->getOpcode() == ISD::SDIV) {
978      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
979                                      CurDAG->getTargetConstant(31, MVT::i32));
980    } else {
981      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
982    }
983    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
984                                    CurDAG->getRegister(V8::G0, MVT::i32));
985
986    // FIXME: Handle div by immediate.
987    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
988    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
989  }
990  case ISD::MULHU:
991  case ISD::MULHS: {
992    // FIXME: Handle mul by immediate.
993    SDOperand MulLHS = Select(N->getOperand(0));
994    SDOperand MulRHS = Select(N->getOperand(1));
995    unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
996    SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
997                                          MulLHS, MulRHS);
998    // The high part is in the Y register.
999    return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
1000  }
1001  case ISD::CALL:
1002    // FIXME: This is a workaround for a bug in tblgen.
1003  { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
1004    // Emits: (CALL:void (tglobaladdr:i32):$dst)
1005    // Pattern complexity = 2  cost = 1
1006    SDOperand N1 = N->getOperand(1);
1007    if (N1.getOpcode() != ISD::TargetGlobalAddress &&
1008        N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
1009    SDOperand InFlag = SDOperand(0, 0);
1010    SDOperand Chain = N->getOperand(0);
1011    SDOperand Tmp0 = N1;
1012    Chain = Select(Chain);
1013    SDOperand Result;
1014    if (N->getNumOperands() == 3) {
1015      InFlag = Select(N->getOperand(2));
1016      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1017                                     Chain, InFlag);
1018    } else {
1019      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1020                                     Chain);
1021    }
1022    Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
1023     CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
1024    return Result.getValue(Op.ResNo);
1025  }
1026    P47Fail:;
1027
1028  }
1029
1030  return SelectCode(Op);
1031}
1032
1033
1034/// createPPCISelDag - This pass converts a legalized DAG into a
1035/// PowerPC-specific DAG, ready for instruction scheduling.
1036///
1037FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1038  return new SparcV8DAGToDAGISel(TM);
1039}
1040