SparcISelDAGToDAG.cpp revision 7f9975a793c575c3e4081e2b0dc3c950681cd316 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Support/Debug.h"
26#include <iostream>
27using namespace llvm;
28
29//===----------------------------------------------------------------------===//
30// TargetLowering Implementation
31//===----------------------------------------------------------------------===//
32
33namespace V8ISD {
34  enum {
35    FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36    CMPICC,   // Compare two GPR operands, set icc.
37    CMPFCC,   // Compare two FP operands, set fcc.
38    BRICC,    // Branch to dest on icc condition
39    BRFCC,    // Branch to dest on fcc condition
40
41    Hi, Lo,   // Hi/Lo operations, typically on a global address.
42
43    FTOI,     // FP to Int within a FP register.
44    ITOF,     // Int to FP within a FP register.
45
46    SELECT_ICC, // Select between two values using the current ICC flags.
47    SELECT_FCC, // Select between two values using the current FCC flags.
48
49    RET_FLAG,   // Return with a flag operand.
50  };
51}
52
53namespace {
54  class SparcV8TargetLowering : public TargetLowering {
55    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
56  public:
57    SparcV8TargetLowering(TargetMachine &TM);
58    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59    virtual std::vector<SDOperand>
60      LowerArguments(Function &F, SelectionDAG &DAG);
61    virtual std::pair<SDOperand, SDOperand>
62      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
63                  unsigned CC,
64                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
65                  SelectionDAG &DAG);
66
67    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
68                                    SelectionDAG &DAG);
69    virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
70                                   Value *VAListV, SelectionDAG &DAG);
71    virtual std::pair<SDOperand,SDOperand>
72      LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
73                 const Type *ArgTy, SelectionDAG &DAG);
74    virtual std::pair<SDOperand, SDOperand>
75      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
76                              SelectionDAG &DAG);
77    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
78                                                       MachineBasicBlock *MBB);
79
80    virtual const char *getTargetNodeName(unsigned Opcode) const;
81  };
82}
83
84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
85  : TargetLowering(TM) {
86
87  // Set up the register classes.
88  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
89  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
90  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
91
92  // Custom legalize GlobalAddress nodes into LO/HI parts.
93  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
95
96  // Sparc doesn't have sext_inreg, replace them with shl/sra
97  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
98  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
99  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
100
101  // Sparc has no REM operation.
102  setOperationAction(ISD::UREM, MVT::i32, Expand);
103  setOperationAction(ISD::SREM, MVT::i32, Expand);
104
105  // Custom expand fp<->sint
106  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
107  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
108
109  // Expand fp<->uint
110  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
111  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
112
113  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
114  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
115
116  // Turn FP extload into load/fextend
117  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
118
119  // Sparc has no select or setcc: expand to SELECT_CC.
120  setOperationAction(ISD::SELECT, MVT::i32, Expand);
121  setOperationAction(ISD::SELECT, MVT::f32, Expand);
122  setOperationAction(ISD::SELECT, MVT::f64, Expand);
123  setOperationAction(ISD::SETCC, MVT::i32, Expand);
124  setOperationAction(ISD::SETCC, MVT::f32, Expand);
125  setOperationAction(ISD::SETCC, MVT::f64, Expand);
126
127  // Sparc doesn't have BRCOND either, it has BR_CC.
128  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
130  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
131  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
132  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
133  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
134
135  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
136  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
138
139  // V8 has no intrinsics for these particular operations.
140  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
141  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
142  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
143
144  setOperationAction(ISD::FSIN , MVT::f64, Expand);
145  setOperationAction(ISD::FCOS , MVT::f64, Expand);
146  setOperationAction(ISD::FSIN , MVT::f32, Expand);
147  setOperationAction(ISD::FCOS , MVT::f32, Expand);
148  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
149  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
150  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
151  setOperationAction(ISD::ROTL , MVT::i32, Expand);
152  setOperationAction(ISD::ROTR , MVT::i32, Expand);
153  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
154
155  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
156  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
157  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
158
159  // We don't have line number support yet.
160  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
161  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
162  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
163
164  // Expand these to their default code.
165  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
166  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
167  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
168
169  setStackPointerRegisterToSaveRestore(V8::O6);
170
171  computeRegisterProperties();
172}
173
174const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
175  switch (Opcode) {
176  default: return 0;
177  case V8ISD::CMPICC:     return "V8ISD::CMPICC";
178  case V8ISD::CMPFCC:     return "V8ISD::CMPFCC";
179  case V8ISD::BRICC:      return "V8ISD::BRICC";
180  case V8ISD::BRFCC:      return "V8ISD::BRFCC";
181  case V8ISD::Hi:         return "V8ISD::Hi";
182  case V8ISD::Lo:         return "V8ISD::Lo";
183  case V8ISD::FTOI:       return "V8ISD::FTOI";
184  case V8ISD::ITOF:       return "V8ISD::ITOF";
185  case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
186  case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
187  case V8ISD::RET_FLAG:   return "V8ISD::RET_FLAG";
188  }
189}
190
191/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
192/// either one or two GPRs, including FP values.  TODO: we should pass FP values
193/// in FP registers for fastcc functions.
194std::vector<SDOperand>
195SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
196  MachineFunction &MF = DAG.getMachineFunction();
197  SSARegMap *RegMap = MF.getSSARegMap();
198  std::vector<SDOperand> ArgValues;
199
200  static const unsigned ArgRegs[] = {
201    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
202  };
203
204  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
205  unsigned ArgOffset = 68;
206
207  SDOperand Root = DAG.getRoot();
208  std::vector<SDOperand> OutChains;
209
210  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
211    MVT::ValueType ObjectVT = getValueType(I->getType());
212
213    switch (ObjectVT) {
214    default: assert(0 && "Unhandled argument type!");
215    case MVT::i1:
216    case MVT::i8:
217    case MVT::i16:
218    case MVT::i32:
219      if (I->use_empty()) {                // Argument is dead.
220        if (CurArgReg < ArgRegEnd) ++CurArgReg;
221        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
222      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
223        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
224        MF.addLiveIn(*CurArgReg++, VReg);
225        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
226        if (ObjectVT != MVT::i32) {
227          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
228                                                       : ISD::AssertZext;
229          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
230                            DAG.getValueType(ObjectVT));
231          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
232        }
233        ArgValues.push_back(Arg);
234      } else {
235        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
236        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
237        SDOperand Load;
238        if (ObjectVT == MVT::i32) {
239          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
240        } else {
241          unsigned LoadOp =
242            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
243
244          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
245                                DAG.getSrcValue(0), ObjectVT);
246        }
247        ArgValues.push_back(Load);
248      }
249
250      ArgOffset += 4;
251      break;
252    case MVT::f32:
253      if (I->use_empty()) {                // Argument is dead.
254        if (CurArgReg < ArgRegEnd) ++CurArgReg;
255        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
256      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
257        // FP value is passed in an integer register.
258        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
259        MF.addLiveIn(*CurArgReg++, VReg);
260        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
261
262        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
263        ArgValues.push_back(Arg);
264      }
265      ArgOffset += 4;
266      break;
267
268    case MVT::i64:
269    case MVT::f64:
270      if (I->use_empty()) {                // Argument is dead.
271        if (CurArgReg < ArgRegEnd) ++CurArgReg;
272        if (CurArgReg < ArgRegEnd) ++CurArgReg;
273        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
274      } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
275                 ((CurArgReg-ArgRegs) & 1) == 0) {
276        // If this is a double argument and the whole thing lives on the stack,
277        // and the argument is aligned, load the double straight from the stack.
278        // We can't do a load in cases like void foo([6ints], int,double),
279        // because the double wouldn't be aligned!
280        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
281        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
282        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
283                                        DAG.getSrcValue(0)));
284      } else {
285        SDOperand HiVal;
286        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
287          unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
288          MF.addLiveIn(*CurArgReg++, VRegHi);
289          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
290        } else {
291          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
292          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
293          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
294        }
295
296        SDOperand LoVal;
297        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
298          unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
299          MF.addLiveIn(*CurArgReg++, VRegLo);
300          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
301        } else {
302          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
303          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
304          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
305        }
306
307        // Compose the two halves together into an i64 unit.
308        SDOperand WholeValue =
309          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
310
311        // If we want a double, do a bit convert.
312        if (ObjectVT == MVT::f64)
313          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
314
315        ArgValues.push_back(WholeValue);
316      }
317      ArgOffset += 8;
318      break;
319    }
320  }
321
322  // Store remaining ArgRegs to the stack if this is a varargs function.
323  if (F.getFunctionType()->isVarArg()) {
324    // Remember the vararg offset for the va_start implementation.
325    VarArgsFrameOffset = ArgOffset;
326
327    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
328      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
329      MF.addLiveIn(*CurArgReg, VReg);
330      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
331
332      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
333      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
334
335      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
336                                      Arg, FIPtr, DAG.getSrcValue(0)));
337      ArgOffset += 4;
338    }
339  }
340
341  if (!OutChains.empty())
342    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
343
344  // Finally, inform the code generator which regs we return values in.
345  switch (getValueType(F.getReturnType())) {
346  default: assert(0 && "Unknown type!");
347  case MVT::isVoid: break;
348  case MVT::i1:
349  case MVT::i8:
350  case MVT::i16:
351  case MVT::i32:
352    MF.addLiveOut(V8::I0);
353    break;
354  case MVT::i64:
355    MF.addLiveOut(V8::I0);
356    MF.addLiveOut(V8::I1);
357    break;
358  case MVT::f32:
359    MF.addLiveOut(V8::F0);
360    break;
361  case MVT::f64:
362    MF.addLiveOut(V8::D0);
363    break;
364  }
365
366  return ArgValues;
367}
368
369std::pair<SDOperand, SDOperand>
370SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
371                                   bool isVarArg, unsigned CC,
372                                   bool isTailCall, SDOperand Callee,
373                                   ArgListTy &Args, SelectionDAG &DAG) {
374  MachineFunction &MF = DAG.getMachineFunction();
375  // Count the size of the outgoing arguments.
376  unsigned ArgsSize = 0;
377  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
378    switch (getValueType(Args[i].second)) {
379    default: assert(0 && "Unknown value type!");
380    case MVT::i1:
381    case MVT::i8:
382    case MVT::i16:
383    case MVT::i32:
384    case MVT::f32:
385      ArgsSize += 4;
386      break;
387    case MVT::i64:
388    case MVT::f64:
389      ArgsSize += 8;
390      break;
391    }
392  }
393  if (ArgsSize > 4*6)
394    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
395  else
396    ArgsSize = 0;
397
398  // Keep stack frames 8-byte aligned.
399  ArgsSize = (ArgsSize+7) & ~7;
400
401  Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
402                      DAG.getConstant(ArgsSize, getPointerTy()));
403
404  SDOperand StackPtr, NullSV;
405  std::vector<SDOperand> Stores;
406  std::vector<SDOperand> RegValuesToPass;
407  unsigned ArgOffset = 68;
408  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
409    SDOperand Val = Args[i].first;
410    MVT::ValueType ObjectVT = Val.getValueType();
411    SDOperand ValToStore(0, 0);
412    unsigned ObjSize;
413    switch (ObjectVT) {
414    default: assert(0 && "Unhandled argument type!");
415    case MVT::i1:
416    case MVT::i8:
417    case MVT::i16:
418      // Promote the integer to 32-bits.  If the input type is signed, use a
419      // sign extend, otherwise use a zero extend.
420      if (Args[i].second->isSigned())
421        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
422      else
423        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
424      // FALL THROUGH
425    case MVT::i32:
426      ObjSize = 4;
427
428      if (RegValuesToPass.size() >= 6) {
429        ValToStore = Val;
430      } else {
431        RegValuesToPass.push_back(Val);
432      }
433      break;
434    case MVT::f32:
435      ObjSize = 4;
436      if (RegValuesToPass.size() >= 6) {
437        ValToStore = Val;
438      } else {
439        // Convert this to a FP value in an int reg.
440        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
441        RegValuesToPass.push_back(Val);
442      }
443      break;
444    case MVT::f64:
445      ObjSize = 8;
446      // If we can store this directly into the outgoing slot, do so.  We can
447      // do this when all ArgRegs are used and if the outgoing slot is aligned.
448      // FIXME: McGill/misr fails with this.
449      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
450        ValToStore = Val;
451        break;
452      }
453
454      // Otherwise, convert this to a FP value in int regs.
455      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
456      // FALL THROUGH
457    case MVT::i64:
458      ObjSize = 8;
459      if (RegValuesToPass.size() >= 6) {
460        ValToStore = Val;    // Whole thing is passed in memory.
461        break;
462      }
463
464      // Split the value into top and bottom part.  Top part goes in a reg.
465      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
466                                 DAG.getConstant(1, MVT::i32));
467      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
468                                 DAG.getConstant(0, MVT::i32));
469      RegValuesToPass.push_back(Hi);
470
471      if (RegValuesToPass.size() >= 6) {
472        ValToStore = Lo;
473        ArgOffset += 4;
474        ObjSize = 4;
475      } else {
476        RegValuesToPass.push_back(Lo);
477      }
478      break;
479    }
480
481    if (ValToStore.Val) {
482      if (!StackPtr.Val) {
483        StackPtr = DAG.getRegister(V8::O6, MVT::i32);
484        NullSV = DAG.getSrcValue(NULL);
485      }
486      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
487      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
488      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
489                                   ValToStore, PtrOff, NullSV));
490    }
491    ArgOffset += ObjSize;
492  }
493
494  // Emit all stores, make sure the occur before any copies into physregs.
495  if (!Stores.empty())
496    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
497
498  static const unsigned ArgRegs[] = {
499    V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
500  };
501
502  // Build a sequence of copy-to-reg nodes chained together with token chain
503  // and flag operands which copy the outgoing args into O[0-5].
504  SDOperand InFlag;
505  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
506    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
507    InFlag = Chain.getValue(1);
508  }
509
510  // If the callee is a GlobalAddress node (quite common, every direct call is)
511  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
512  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
513    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
514
515  std::vector<MVT::ValueType> NodeTys;
516  NodeTys.push_back(MVT::Other);   // Returns a chain
517  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
518  if (InFlag.Val)
519    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
520  else
521    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
522  InFlag = Chain.getValue(1);
523
524  MVT::ValueType RetTyVT = getValueType(RetTy);
525  SDOperand RetVal;
526  if (RetTyVT != MVT::isVoid) {
527    switch (RetTyVT) {
528    default: assert(0 && "Unknown value type to return!");
529    case MVT::i1:
530    case MVT::i8:
531    case MVT::i16:
532      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
533      Chain = RetVal.getValue(1);
534
535      // Add a note to keep track of whether it is sign or zero extended.
536      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
537                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
538      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
539      break;
540    case MVT::i32:
541      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
542      Chain = RetVal.getValue(1);
543      break;
544    case MVT::f32:
545      RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
546      Chain = RetVal.getValue(1);
547      break;
548    case MVT::f64:
549      RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
550      Chain = RetVal.getValue(1);
551      break;
552    case MVT::i64:
553      SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
554      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
555                                        Lo.getValue(2));
556      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
557      Chain = Hi.getValue(1);
558      break;
559    }
560  }
561
562  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
563                      DAG.getConstant(ArgsSize, getPointerTy()));
564
565  return std::make_pair(RetVal, Chain);
566}
567
568SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
569                                               SelectionDAG &DAG) {
570  SDOperand Copy;
571  switch (Op.getValueType()) {
572  default: assert(0 && "Unknown type to return!");
573  case MVT::i32:
574    Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
575    break;
576  case MVT::f32:
577    Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
578    break;
579  case MVT::f64:
580    Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
581    break;
582  case MVT::i64:
583    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
584                               DAG.getConstant(1, MVT::i32));
585    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
586                               DAG.getConstant(0, MVT::i32));
587    Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
588    Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
589    break;
590  }
591  return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
592}
593
594SDOperand SparcV8TargetLowering::
595LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
596             SelectionDAG &DAG) {
597
598  SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
599                                 DAG.getRegister(V8::I6, MVT::i32),
600                                 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
601  return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
602                     VAListP, DAG.getSrcValue(VAListV));
603}
604
605std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
606LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
607           const Type *ArgTy, SelectionDAG &DAG) {
608  // Load the pointer out of the valist.
609  SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
610                              VAListP, DAG.getSrcValue(VAListV));
611  MVT::ValueType ArgVT = getValueType(ArgTy);
612  SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
613                              Ptr, DAG.getSrcValue(NULL));
614  // Increment the pointer.
615  Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
616                    DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
617  // Store it back to the valist.
618  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
619                      VAListP, DAG.getSrcValue(VAListV));
620  return std::make_pair(Val, Chain);
621}
622
623std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
624LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
625                        SelectionDAG &DAG) {
626  assert(0 && "Unimp");
627  abort();
628}
629
630SDOperand SparcV8TargetLowering::
631LowerOperation(SDOperand Op, SelectionDAG &DAG) {
632  switch (Op.getOpcode()) {
633  default: assert(0 && "Should not custom lower this!");
634  case ISD::GlobalAddress: {
635    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
636    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
637    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
638    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
639    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
640  }
641  case ISD::ConstantPool: {
642    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
643    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
644    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
645    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
646    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
647  }
648  case ISD::FP_TO_SINT:
649    // Convert the fp value to integer in an FP register.
650    assert(Op.getValueType() == MVT::i32);
651    Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
652    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
653  case ISD::SINT_TO_FP: {
654    assert(Op.getOperand(0).getValueType() == MVT::i32);
655    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
656    // Convert the int value to FP in an FP register.
657    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
658  }
659  case ISD::BR_CC: {
660    SDOperand Chain = Op.getOperand(0);
661    SDOperand CC = Op.getOperand(1);
662    SDOperand LHS = Op.getOperand(2);
663    SDOperand RHS = Op.getOperand(3);
664    SDOperand Dest = Op.getOperand(4);
665
666    // Get the condition flag.
667    if (LHS.getValueType() == MVT::i32) {
668      std::vector<MVT::ValueType> VTs;
669      VTs.push_back(MVT::i32);
670      VTs.push_back(MVT::Flag);
671      std::vector<SDOperand> Ops;
672      Ops.push_back(LHS);
673      Ops.push_back(RHS);
674      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
675      return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
676    } else {
677      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
678      return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
679    }
680  }
681  case ISD::SELECT_CC: {
682    SDOperand LHS = Op.getOperand(0);
683    SDOperand RHS = Op.getOperand(1);
684    unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
685    SDOperand TrueVal = Op.getOperand(2);
686    SDOperand FalseVal = Op.getOperand(3);
687
688    SDOperand CompareFlag;
689    unsigned Opc;
690    if (LHS.getValueType() == MVT::i32) {
691      std::vector<MVT::ValueType> VTs;
692      VTs.push_back(LHS.getValueType());   // subcc returns a value
693      VTs.push_back(MVT::Flag);
694      std::vector<SDOperand> Ops;
695      Ops.push_back(LHS);
696      Ops.push_back(RHS);
697      CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
698      Opc = V8ISD::SELECT_ICC;
699    } else {
700      CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
701      Opc = V8ISD::SELECT_FCC;
702    }
703    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
704                       DAG.getConstant(CC, MVT::i32), CompareFlag);
705  }
706  }
707}
708
709MachineBasicBlock *
710SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
711                                               MachineBasicBlock *BB) {
712  unsigned BROpcode;
713  // Figure out the conditional branch opcode to use for this select_cc.
714  switch (MI->getOpcode()) {
715  default: assert(0 && "Unknown SELECT_CC!");
716  case V8::SELECT_CC_Int_ICC:
717  case V8::SELECT_CC_FP_ICC:
718  case V8::SELECT_CC_DFP_ICC:
719    // Integer compare.
720    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
721    default: assert(0 && "Unknown integer condition code!");
722    case ISD::SETEQ:  BROpcode = V8::BE; break;
723    case ISD::SETNE:  BROpcode = V8::BNE; break;
724    case ISD::SETLT:  BROpcode = V8::BL; break;
725    case ISD::SETGT:  BROpcode = V8::BG; break;
726    case ISD::SETLE:  BROpcode = V8::BLE; break;
727    case ISD::SETGE:  BROpcode = V8::BGE; break;
728    case ISD::SETULT: BROpcode = V8::BCS; break;
729    case ISD::SETULE: BROpcode = V8::BLEU; break;
730    case ISD::SETUGT: BROpcode = V8::BGU; break;
731    case ISD::SETUGE: BROpcode = V8::BCC; break;
732    }
733    break;
734  case V8::SELECT_CC_Int_FCC:
735  case V8::SELECT_CC_FP_FCC:
736  case V8::SELECT_CC_DFP_FCC:
737    // FP compare.
738    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
739    default: assert(0 && "Unknown fp condition code!");
740    case ISD::SETEQ:  BROpcode = V8::FBE; break;
741    case ISD::SETNE:  BROpcode = V8::FBNE; break;
742    case ISD::SETLT:  BROpcode = V8::FBL; break;
743    case ISD::SETGT:  BROpcode = V8::FBG; break;
744    case ISD::SETLE:  BROpcode = V8::FBLE; break;
745    case ISD::SETGE:  BROpcode = V8::FBGE; break;
746    case ISD::SETULT: BROpcode = V8::FBUL; break;
747    case ISD::SETULE: BROpcode = V8::FBULE; break;
748    case ISD::SETUGT: BROpcode = V8::FBUG; break;
749    case ISD::SETUGE: BROpcode = V8::FBUGE; break;
750    case ISD::SETUO:  BROpcode = V8::FBU; break;
751    case ISD::SETO:   BROpcode = V8::FBO; break;
752    case ISD::SETONE: BROpcode = V8::FBLG; break;
753    case ISD::SETUEQ: BROpcode = V8::FBUE; break;
754    }
755    break;
756  }
757
758  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
759  // control-flow pattern.  The incoming instruction knows the destination vreg
760  // to set, the condition code register to branch on, the true/false values to
761  // select between, and a branch opcode to use.
762  const BasicBlock *LLVM_BB = BB->getBasicBlock();
763  ilist<MachineBasicBlock>::iterator It = BB;
764  ++It;
765
766  //  thisMBB:
767  //  ...
768  //   TrueVal = ...
769  //   [f]bCC copy1MBB
770  //   fallthrough --> copy0MBB
771  MachineBasicBlock *thisMBB = BB;
772  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
773  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
774  BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
775  MachineFunction *F = BB->getParent();
776  F->getBasicBlockList().insert(It, copy0MBB);
777  F->getBasicBlockList().insert(It, sinkMBB);
778  // Update machine-CFG edges
779  BB->addSuccessor(copy0MBB);
780  BB->addSuccessor(sinkMBB);
781
782  //  copy0MBB:
783  //   %FalseValue = ...
784  //   # fallthrough to sinkMBB
785  BB = copy0MBB;
786
787  // Update machine-CFG edges
788  BB->addSuccessor(sinkMBB);
789
790  //  sinkMBB:
791  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
792  //  ...
793  BB = sinkMBB;
794  BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
795    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
796    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
797
798  delete MI;   // The pseudo instruction is gone now.
799  return BB;
800}
801
802//===----------------------------------------------------------------------===//
803// Instruction Selector Implementation
804//===----------------------------------------------------------------------===//
805
806//===--------------------------------------------------------------------===//
807/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
808/// instructions for SelectionDAG operations.
809///
810namespace {
811class SparcV8DAGToDAGISel : public SelectionDAGISel {
812  SparcV8TargetLowering V8Lowering;
813public:
814  SparcV8DAGToDAGISel(TargetMachine &TM)
815    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
816
817  SDOperand Select(SDOperand Op);
818
819  // Complex Pattern Selectors.
820  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
821  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
822
823  /// InstructionSelectBasicBlock - This callback is invoked by
824  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
825  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
826
827  virtual const char *getPassName() const {
828    return "PowerPC DAG->DAG Pattern Instruction Selection";
829  }
830
831  // Include the pieces autogenerated from the target description.
832#include "SparcV8GenDAGISel.inc"
833};
834}  // end anonymous namespace
835
836/// InstructionSelectBasicBlock - This callback is invoked by
837/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
838void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
839  DEBUG(BB->dump());
840
841  // Select target instructions for the DAG.
842  DAG.setRoot(Select(DAG.getRoot()));
843  CodeGenMap.clear();
844  DAG.RemoveDeadNodes();
845
846  // Emit machine code to BB.
847  ScheduleAndEmitDAG(DAG);
848}
849
850bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
851                                       SDOperand &Offset) {
852  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
853    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
854    Offset = CurDAG->getTargetConstant(0, MVT::i32);
855    return true;
856  }
857
858  if (Addr.getOpcode() == ISD::ADD) {
859    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
860      if (Predicate_simm13(CN)) {
861        if (FrameIndexSDNode *FIN =
862                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
863          // Constant offset from frame ref.
864          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
865        } else {
866          Base = Select(Addr.getOperand(0));
867        }
868        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
869        return true;
870      }
871    }
872    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
873      Base = Select(Addr.getOperand(1));
874      Offset = Addr.getOperand(0).getOperand(0);
875      return true;
876    }
877    if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
878      Base = Select(Addr.getOperand(0));
879      Offset = Addr.getOperand(1).getOperand(0);
880      return true;
881    }
882  }
883  Base = Select(Addr);
884  Offset = CurDAG->getTargetConstant(0, MVT::i32);
885  return true;
886}
887
888bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
889                                       SDOperand &R2) {
890  if (Addr.getOpcode() == ISD::FrameIndex) return false;
891  if (Addr.getOpcode() == ISD::ADD) {
892    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
893        Predicate_simm13(Addr.getOperand(1).Val))
894      return false;  // Let the reg+imm pattern catch this!
895    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
896        Addr.getOperand(1).getOpcode() == V8ISD::Lo)
897      return false;  // Let the reg+imm pattern catch this!
898    R1 = Select(Addr.getOperand(0));
899    R2 = Select(Addr.getOperand(1));
900    return true;
901  }
902
903  R1 = Select(Addr);
904  R2 = CurDAG->getRegister(V8::G0, MVT::i32);
905  return true;
906}
907
908SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
909  SDNode *N = Op.Val;
910  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
911      N->getOpcode() < V8ISD::FIRST_NUMBER)
912    return Op;   // Already selected.
913                 // If this has already been converted, use it.
914  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
915  if (CGMI != CodeGenMap.end()) return CGMI->second;
916
917  switch (N->getOpcode()) {
918  default: break;
919  case ISD::FrameIndex: {
920    int FI = cast<FrameIndexSDNode>(N)->getIndex();
921    if (N->hasOneUse())
922      return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
923                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
924                                  CurDAG->getTargetConstant(0, MVT::i32));
925    return CodeGenMap[Op] =
926      CurDAG->getTargetNode(V8::ADDri, MVT::i32,
927                            CurDAG->getTargetFrameIndex(FI, MVT::i32),
928                            CurDAG->getTargetConstant(0, MVT::i32));
929  }
930  case ISD::ADD_PARTS: {
931    SDOperand LHSL = Select(N->getOperand(0));
932    SDOperand LHSH = Select(N->getOperand(1));
933    SDOperand RHSL = Select(N->getOperand(2));
934    SDOperand RHSH = Select(N->getOperand(3));
935    // FIXME, handle immediate RHS.
936    SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
937                                          LHSL, RHSL);
938    SDOperand Hi  = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
939                                          Low.getValue(1));
940    CodeGenMap[SDOperand(N, 0)] = Low;
941    CodeGenMap[SDOperand(N, 1)] = Hi;
942    return Op.ResNo ? Hi : Low;
943  }
944  case ISD::SUB_PARTS: {
945    SDOperand LHSL = Select(N->getOperand(0));
946    SDOperand LHSH = Select(N->getOperand(1));
947    SDOperand RHSL = Select(N->getOperand(2));
948    SDOperand RHSH = Select(N->getOperand(3));
949    // FIXME, handle immediate RHS.
950    SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
951                                          LHSL, RHSL);
952    SDOperand Hi  = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
953                                          Low.getValue(1));
954    CodeGenMap[SDOperand(N, 0)] = Low;
955    CodeGenMap[SDOperand(N, 1)] = Hi;
956    return Op.ResNo ? Hi : Low;
957  }
958  case ISD::SDIV:
959  case ISD::UDIV: {
960    // FIXME: should use a custom expander to expose the SRA to the dag.
961    SDOperand DivLHS = Select(N->getOperand(0));
962    SDOperand DivRHS = Select(N->getOperand(1));
963
964    // Set the Y register to the high-part.
965    SDOperand TopPart;
966    if (N->getOpcode() == ISD::SDIV) {
967      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
968                                      CurDAG->getTargetConstant(31, MVT::i32));
969    } else {
970      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
971    }
972    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
973                                    CurDAG->getRegister(V8::G0, MVT::i32));
974
975    // FIXME: Handle div by immediate.
976    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
977    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
978  }
979  case ISD::MULHU:
980  case ISD::MULHS: {
981    // FIXME: Handle mul by immediate.
982    SDOperand MulLHS = Select(N->getOperand(0));
983    SDOperand MulRHS = Select(N->getOperand(1));
984    unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
985    SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
986                                          MulLHS, MulRHS);
987    // The high part is in the Y register.
988    return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
989  }
990  case ISD::CALL:
991    // FIXME: This is a workaround for a bug in tblgen.
992  { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
993    // Emits: (CALL:void (tglobaladdr:i32):$dst)
994    // Pattern complexity = 2  cost = 1
995    SDOperand N1 = N->getOperand(1);
996    if (N1.getOpcode() != ISD::TargetGlobalAddress &&
997        N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
998    SDOperand InFlag = SDOperand(0, 0);
999    SDOperand Chain = N->getOperand(0);
1000    SDOperand Tmp0 = N1;
1001    Chain = Select(Chain);
1002    SDOperand Result;
1003    if (N->getNumOperands() == 3) {
1004      InFlag = Select(N->getOperand(2));
1005      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1006                                     Chain, InFlag);
1007    } else {
1008      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1009                                     Chain);
1010    }
1011    Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
1012     CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
1013    return Result.getValue(Op.ResNo);
1014  }
1015    P47Fail:;
1016
1017  }
1018
1019  return SelectCode(Op);
1020}
1021
1022
1023/// createPPCISelDag - This pass converts a legalized DAG into a
1024/// PowerPC-specific DAG, ready for instruction scheduling.
1025///
1026FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1027  return new SparcV8DAGToDAGISel(TM);
1028}
1029