SparcISelDAGToDAG.cpp revision 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/CodeGen/SelectionDAGISel.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Compiler.h" 27#include "llvm/Support/Debug.h" 28#include <queue> 29#include <set> 30using namespace llvm; 31 32//===----------------------------------------------------------------------===// 33// TargetLowering Implementation 34//===----------------------------------------------------------------------===// 35 36namespace SPISD { 37 enum { 38 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 39 CMPICC, // Compare two GPR operands, set icc. 40 CMPFCC, // Compare two FP operands, set fcc. 41 BRICC, // Branch to dest on icc condition 42 BRFCC, // Branch to dest on fcc condition 43 SELECT_ICC, // Select between two values using the current ICC flags. 44 SELECT_FCC, // Select between two values using the current FCC flags. 45 46 Hi, Lo, // Hi/Lo operations, typically on a global address. 47 48 FTOI, // FP to Int within a FP register. 49 ITOF, // Int to FP within a FP register. 50 51 CALL, // A call instruction. 52 RET_FLAG // Return with a flag operand. 53 }; 54} 55 56/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 57/// condition. 58static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 59 switch (CC) { 60 default: assert(0 && "Unknown integer condition code!"); 61 case ISD::SETEQ: return SPCC::ICC_E; 62 case ISD::SETNE: return SPCC::ICC_NE; 63 case ISD::SETLT: return SPCC::ICC_L; 64 case ISD::SETGT: return SPCC::ICC_G; 65 case ISD::SETLE: return SPCC::ICC_LE; 66 case ISD::SETGE: return SPCC::ICC_GE; 67 case ISD::SETULT: return SPCC::ICC_CS; 68 case ISD::SETULE: return SPCC::ICC_LEU; 69 case ISD::SETUGT: return SPCC::ICC_GU; 70 case ISD::SETUGE: return SPCC::ICC_CC; 71 } 72} 73 74/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 75/// FCC condition. 76static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 77 switch (CC) { 78 default: assert(0 && "Unknown fp condition code!"); 79 case ISD::SETEQ: 80 case ISD::SETOEQ: return SPCC::FCC_E; 81 case ISD::SETNE: 82 case ISD::SETUNE: return SPCC::FCC_NE; 83 case ISD::SETLT: 84 case ISD::SETOLT: return SPCC::FCC_L; 85 case ISD::SETGT: 86 case ISD::SETOGT: return SPCC::FCC_G; 87 case ISD::SETLE: 88 case ISD::SETOLE: return SPCC::FCC_LE; 89 case ISD::SETGE: 90 case ISD::SETOGE: return SPCC::FCC_GE; 91 case ISD::SETULT: return SPCC::FCC_UL; 92 case ISD::SETULE: return SPCC::FCC_ULE; 93 case ISD::SETUGT: return SPCC::FCC_UG; 94 case ISD::SETUGE: return SPCC::FCC_UGE; 95 case ISD::SETUO: return SPCC::FCC_U; 96 case ISD::SETO: return SPCC::FCC_O; 97 case ISD::SETONE: return SPCC::FCC_LG; 98 case ISD::SETUEQ: return SPCC::FCC_UE; 99 } 100} 101 102namespace { 103 class SparcTargetLowering : public TargetLowering { 104 int VarArgsFrameOffset; // Frame offset to start of varargs area. 105 public: 106 SparcTargetLowering(TargetMachine &TM); 107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 108 109 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 110 /// in Mask are known to be either zero or one and return them in the 111 /// KnownZero/KnownOne bitsets. 112 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 113 const APInt &Mask, 114 APInt &KnownZero, 115 APInt &KnownOne, 116 const SelectionDAG &DAG, 117 unsigned Depth = 0) const; 118 119 virtual std::vector<SDOperand> 120 LowerArguments(Function &F, SelectionDAG &DAG); 121 virtual std::pair<SDOperand, SDOperand> 122 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 123 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 124 ArgListTy &Args, SelectionDAG &DAG); 125 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 126 MachineBasicBlock *MBB); 127 128 virtual const char *getTargetNodeName(unsigned Opcode) const; 129 }; 130} 131 132SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 133 : TargetLowering(TM) { 134 135 // Set up the register classes. 136 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 137 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 138 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 139 140 // Turn FP extload into load/fextend 141 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 142 143 // Sparc doesn't have i1 sign extending load 144 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 145 146 // Custom legalize GlobalAddress nodes into LO/HI parts. 147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 148 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 149 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 150 151 // Sparc doesn't have sext_inreg, replace them with shl/sra 152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 155 156 // Sparc has no REM or DIVREM operations. 157 setOperationAction(ISD::UREM, MVT::i32, Expand); 158 setOperationAction(ISD::SREM, MVT::i32, Expand); 159 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 160 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 161 162 // Custom expand fp<->sint 163 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 164 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 165 166 // Expand fp<->uint 167 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 168 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 169 170 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 171 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 172 173 // Sparc has no select or setcc: expand to SELECT_CC. 174 setOperationAction(ISD::SELECT, MVT::i32, Expand); 175 setOperationAction(ISD::SELECT, MVT::f32, Expand); 176 setOperationAction(ISD::SELECT, MVT::f64, Expand); 177 setOperationAction(ISD::SETCC, MVT::i32, Expand); 178 setOperationAction(ISD::SETCC, MVT::f32, Expand); 179 setOperationAction(ISD::SETCC, MVT::f64, Expand); 180 181 // Sparc doesn't have BRCOND either, it has BR_CC. 182 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 183 setOperationAction(ISD::BRIND, MVT::Other, Expand); 184 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 185 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 186 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 187 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 188 189 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 190 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 191 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 192 193 // SPARC has no intrinsics for these particular operations. 194 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 195 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 196 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 197 198 setOperationAction(ISD::FSIN , MVT::f64, Expand); 199 setOperationAction(ISD::FCOS , MVT::f64, Expand); 200 setOperationAction(ISD::FREM , MVT::f64, Expand); 201 setOperationAction(ISD::FSIN , MVT::f32, Expand); 202 setOperationAction(ISD::FCOS , MVT::f32, Expand); 203 setOperationAction(ISD::FREM , MVT::f32, Expand); 204 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 205 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 206 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 207 setOperationAction(ISD::ROTL , MVT::i32, Expand); 208 setOperationAction(ISD::ROTR , MVT::i32, Expand); 209 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 210 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 211 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 212 setOperationAction(ISD::FPOW , MVT::f64, Expand); 213 setOperationAction(ISD::FPOW , MVT::f32, Expand); 214 215 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 216 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 217 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 218 219 // We don't have line number support yet. 220 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 221 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 222 setOperationAction(ISD::LABEL, MVT::Other, Expand); 223 224 // RET must be custom lowered, to meet ABI requirements 225 setOperationAction(ISD::RET , MVT::Other, Custom); 226 227 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 228 setOperationAction(ISD::VASTART , MVT::Other, Custom); 229 // VAARG needs to be lowered to not do unaligned accesses for doubles. 230 setOperationAction(ISD::VAARG , MVT::Other, Custom); 231 232 // Use the default implementation. 233 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 234 setOperationAction(ISD::VAEND , MVT::Other, Expand); 235 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 236 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 237 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 238 239 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 240 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 241 242 setStackPointerRegisterToSaveRestore(SP::O6); 243 244 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 245 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 246 } 247 248 computeRegisterProperties(); 249} 250 251const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 252 switch (Opcode) { 253 default: return 0; 254 case SPISD::CMPICC: return "SPISD::CMPICC"; 255 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 256 case SPISD::BRICC: return "SPISD::BRICC"; 257 case SPISD::BRFCC: return "SPISD::BRFCC"; 258 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 259 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 260 case SPISD::Hi: return "SPISD::Hi"; 261 case SPISD::Lo: return "SPISD::Lo"; 262 case SPISD::FTOI: return "SPISD::FTOI"; 263 case SPISD::ITOF: return "SPISD::ITOF"; 264 case SPISD::CALL: return "SPISD::CALL"; 265 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 266 } 267} 268 269/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 270/// be zero. Op is expected to be a target specific node. Used by DAG 271/// combiner. 272void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 273 const APInt &Mask, 274 APInt &KnownZero, 275 APInt &KnownOne, 276 const SelectionDAG &DAG, 277 unsigned Depth) const { 278 APInt KnownZero2, KnownOne2; 279 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 280 281 switch (Op.getOpcode()) { 282 default: break; 283 case SPISD::SELECT_ICC: 284 case SPISD::SELECT_FCC: 285 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 286 Depth+1); 287 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 288 Depth+1); 289 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 290 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 291 292 // Only known if known in both the LHS and RHS. 293 KnownOne &= KnownOne2; 294 KnownZero &= KnownZero2; 295 break; 296 } 297} 298 299/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 300/// either one or two GPRs, including FP values. TODO: we should pass FP values 301/// in FP registers for fastcc functions. 302std::vector<SDOperand> 303SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 304 MachineFunction &MF = DAG.getMachineFunction(); 305 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 306 std::vector<SDOperand> ArgValues; 307 308 static const unsigned ArgRegs[] = { 309 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 310 }; 311 312 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 313 unsigned ArgOffset = 68; 314 315 SDOperand Root = DAG.getRoot(); 316 std::vector<SDOperand> OutChains; 317 318 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 319 MVT::ValueType ObjectVT = getValueType(I->getType()); 320 321 switch (ObjectVT) { 322 default: assert(0 && "Unhandled argument type!"); 323 case MVT::i1: 324 case MVT::i8: 325 case MVT::i16: 326 case MVT::i32: 327 if (I->use_empty()) { // Argument is dead. 328 if (CurArgReg < ArgRegEnd) ++CurArgReg; 329 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 330 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 331 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 332 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 333 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 334 if (ObjectVT != MVT::i32) { 335 unsigned AssertOp = ISD::AssertSext; 336 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 337 DAG.getValueType(ObjectVT)); 338 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 339 } 340 ArgValues.push_back(Arg); 341 } else { 342 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 343 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 344 SDOperand Load; 345 if (ObjectVT == MVT::i32) { 346 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 347 } else { 348 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 349 350 // Sparc is big endian, so add an offset based on the ObjectVT. 351 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 352 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 353 DAG.getConstant(Offset, MVT::i32)); 354 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 355 NULL, 0, ObjectVT); 356 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 357 } 358 ArgValues.push_back(Load); 359 } 360 361 ArgOffset += 4; 362 break; 363 case MVT::f32: 364 if (I->use_empty()) { // Argument is dead. 365 if (CurArgReg < ArgRegEnd) ++CurArgReg; 366 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 367 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 368 // FP value is passed in an integer register. 369 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 370 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 371 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 372 373 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 374 ArgValues.push_back(Arg); 375 } else { 376 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 377 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 378 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 379 ArgValues.push_back(Load); 380 } 381 ArgOffset += 4; 382 break; 383 384 case MVT::i64: 385 case MVT::f64: 386 if (I->use_empty()) { // Argument is dead. 387 if (CurArgReg < ArgRegEnd) ++CurArgReg; 388 if (CurArgReg < ArgRegEnd) ++CurArgReg; 389 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 390 } else if (/* FIXME: Apparently this isn't safe?? */ 391 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 392 ((CurArgReg-ArgRegs) & 1) == 0) { 393 // If this is a double argument and the whole thing lives on the stack, 394 // and the argument is aligned, load the double straight from the stack. 395 // We can't do a load in cases like void foo([6ints], int,double), 396 // because the double wouldn't be aligned! 397 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 398 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 399 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 400 } else { 401 SDOperand HiVal; 402 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 403 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 404 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 405 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 406 } else { 407 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 408 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 409 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 410 } 411 412 SDOperand LoVal; 413 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 414 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 415 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 416 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 417 } else { 418 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 419 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 420 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 421 } 422 423 // Compose the two halves together into an i64 unit. 424 SDOperand WholeValue = 425 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 426 427 // If we want a double, do a bit convert. 428 if (ObjectVT == MVT::f64) 429 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 430 431 ArgValues.push_back(WholeValue); 432 } 433 ArgOffset += 8; 434 break; 435 } 436 } 437 438 // Store remaining ArgRegs to the stack if this is a varargs function. 439 if (F.getFunctionType()->isVarArg()) { 440 // Remember the vararg offset for the va_start implementation. 441 VarArgsFrameOffset = ArgOffset; 442 443 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 444 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 445 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 446 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 447 448 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 449 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 450 451 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 452 ArgOffset += 4; 453 } 454 } 455 456 if (!OutChains.empty()) 457 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 458 &OutChains[0], OutChains.size())); 459 460 // Finally, inform the code generator which regs we return values in. 461 switch (getValueType(F.getReturnType())) { 462 default: assert(0 && "Unknown type!"); 463 case MVT::isVoid: break; 464 case MVT::i1: 465 case MVT::i8: 466 case MVT::i16: 467 case MVT::i32: 468 MF.getRegInfo().addLiveOut(SP::I0); 469 break; 470 case MVT::i64: 471 MF.getRegInfo().addLiveOut(SP::I0); 472 MF.getRegInfo().addLiveOut(SP::I1); 473 break; 474 case MVT::f32: 475 MF.getRegInfo().addLiveOut(SP::F0); 476 break; 477 case MVT::f64: 478 MF.getRegInfo().addLiveOut(SP::D0); 479 break; 480 } 481 482 return ArgValues; 483} 484 485std::pair<SDOperand, SDOperand> 486SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 487 bool RetTyIsSigned, bool isVarArg, unsigned CC, 488 bool isTailCall, SDOperand Callee, 489 ArgListTy &Args, SelectionDAG &DAG) { 490 // Count the size of the outgoing arguments. 491 unsigned ArgsSize = 0; 492 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 493 switch (getValueType(Args[i].Ty)) { 494 default: assert(0 && "Unknown value type!"); 495 case MVT::i1: 496 case MVT::i8: 497 case MVT::i16: 498 case MVT::i32: 499 case MVT::f32: 500 ArgsSize += 4; 501 break; 502 case MVT::i64: 503 case MVT::f64: 504 ArgsSize += 8; 505 break; 506 } 507 } 508 if (ArgsSize > 4*6) 509 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 510 else 511 ArgsSize = 0; 512 513 // Keep stack frames 8-byte aligned. 514 ArgsSize = (ArgsSize+7) & ~7; 515 516 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 517 518 SDOperand StackPtr; 519 std::vector<SDOperand> Stores; 520 std::vector<SDOperand> RegValuesToPass; 521 unsigned ArgOffset = 68; 522 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 523 SDOperand Val = Args[i].Node; 524 MVT::ValueType ObjectVT = Val.getValueType(); 525 SDOperand ValToStore(0, 0); 526 unsigned ObjSize; 527 switch (ObjectVT) { 528 default: assert(0 && "Unhandled argument type!"); 529 case MVT::i1: 530 case MVT::i8: 531 case MVT::i16: { 532 // Promote the integer to 32-bits. If the input type is signed, use a 533 // sign extend, otherwise use a zero extend. 534 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 535 if (Args[i].isSExt) 536 ExtendKind = ISD::SIGN_EXTEND; 537 else if (Args[i].isZExt) 538 ExtendKind = ISD::ZERO_EXTEND; 539 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 540 // FALL THROUGH 541 } 542 case MVT::i32: 543 ObjSize = 4; 544 545 if (RegValuesToPass.size() >= 6) { 546 ValToStore = Val; 547 } else { 548 RegValuesToPass.push_back(Val); 549 } 550 break; 551 case MVT::f32: 552 ObjSize = 4; 553 if (RegValuesToPass.size() >= 6) { 554 ValToStore = Val; 555 } else { 556 // Convert this to a FP value in an int reg. 557 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 558 RegValuesToPass.push_back(Val); 559 } 560 break; 561 case MVT::f64: 562 ObjSize = 8; 563 // If we can store this directly into the outgoing slot, do so. We can 564 // do this when all ArgRegs are used and if the outgoing slot is aligned. 565 // FIXME: McGill/misr fails with this. 566 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 567 ValToStore = Val; 568 break; 569 } 570 571 // Otherwise, convert this to a FP value in int regs. 572 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 573 // FALL THROUGH 574 case MVT::i64: 575 ObjSize = 8; 576 if (RegValuesToPass.size() >= 6) { 577 ValToStore = Val; // Whole thing is passed in memory. 578 break; 579 } 580 581 // Split the value into top and bottom part. Top part goes in a reg. 582 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 583 DAG.getConstant(1, MVT::i32)); 584 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 585 DAG.getConstant(0, MVT::i32)); 586 RegValuesToPass.push_back(Hi); 587 588 if (RegValuesToPass.size() >= 6) { 589 ValToStore = Lo; 590 ArgOffset += 4; 591 ObjSize = 4; 592 } else { 593 RegValuesToPass.push_back(Lo); 594 } 595 break; 596 } 597 598 if (ValToStore.Val) { 599 if (!StackPtr.Val) { 600 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 601 } 602 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 603 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 604 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 605 } 606 ArgOffset += ObjSize; 607 } 608 609 // Emit all stores, make sure the occur before any copies into physregs. 610 if (!Stores.empty()) 611 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 612 613 static const unsigned ArgRegs[] = { 614 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 615 }; 616 617 // Build a sequence of copy-to-reg nodes chained together with token chain 618 // and flag operands which copy the outgoing args into O[0-5]. 619 SDOperand InFlag; 620 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 621 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 622 InFlag = Chain.getValue(1); 623 } 624 625 // If the callee is a GlobalAddress node (quite common, every direct call is) 626 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 627 // Likewise ExternalSymbol -> TargetExternalSymbol. 628 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 629 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 630 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 631 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 632 633 std::vector<MVT::ValueType> NodeTys; 634 NodeTys.push_back(MVT::Other); // Returns a chain 635 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 636 SDOperand Ops[] = { Chain, Callee, InFlag }; 637 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 638 InFlag = Chain.getValue(1); 639 640 MVT::ValueType RetTyVT = getValueType(RetTy); 641 SDOperand RetVal; 642 if (RetTyVT != MVT::isVoid) { 643 switch (RetTyVT) { 644 default: assert(0 && "Unknown value type to return!"); 645 case MVT::i1: 646 case MVT::i8: 647 case MVT::i16: { 648 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 649 Chain = RetVal.getValue(1); 650 651 // Add a note to keep track of whether it is sign or zero extended. 652 ISD::NodeType AssertKind = ISD::AssertZext; 653 if (RetTyIsSigned) 654 AssertKind = ISD::AssertSext; 655 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 656 DAG.getValueType(RetTyVT)); 657 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 658 break; 659 } 660 case MVT::i32: 661 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 662 Chain = RetVal.getValue(1); 663 break; 664 case MVT::f32: 665 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 666 Chain = RetVal.getValue(1); 667 break; 668 case MVT::f64: 669 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 670 Chain = RetVal.getValue(1); 671 break; 672 case MVT::i64: 673 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 674 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 675 Lo.getValue(2)); 676 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 677 Chain = Hi.getValue(1); 678 break; 679 } 680 } 681 682 Chain = DAG.getCALLSEQ_END(Chain, 683 DAG.getConstant(ArgsSize, getPointerTy()), 684 DAG.getConstant(0, getPointerTy()), 685 SDOperand()); 686 return std::make_pair(RetVal, Chain); 687} 688 689// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 690// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 691static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 692 ISD::CondCode CC, unsigned &SPCC) { 693 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 694 CC == ISD::SETNE && 695 ((LHS.getOpcode() == SPISD::SELECT_ICC && 696 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 697 (LHS.getOpcode() == SPISD::SELECT_FCC && 698 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 699 isa<ConstantSDNode>(LHS.getOperand(0)) && 700 isa<ConstantSDNode>(LHS.getOperand(1)) && 701 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 702 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 703 SDOperand CMPCC = LHS.getOperand(3); 704 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 705 LHS = CMPCC.getOperand(0); 706 RHS = CMPCC.getOperand(1); 707 } 708} 709 710 711SDOperand SparcTargetLowering:: 712LowerOperation(SDOperand Op, SelectionDAG &DAG) { 713 switch (Op.getOpcode()) { 714 default: assert(0 && "Should not custom lower this!"); 715 case ISD::GlobalTLSAddress: 716 assert(0 && "TLS not implemented for Sparc."); 717 case ISD::GlobalAddress: { 718 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 719 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 720 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 721 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 722 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 723 } 724 case ISD::ConstantPool: { 725 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 726 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 727 cast<ConstantPoolSDNode>(Op)->getAlignment()); 728 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 729 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 730 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 731 } 732 case ISD::FP_TO_SINT: 733 // Convert the fp value to integer in an FP register. 734 assert(Op.getValueType() == MVT::i32); 735 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 736 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 737 case ISD::SINT_TO_FP: { 738 assert(Op.getOperand(0).getValueType() == MVT::i32); 739 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 740 // Convert the int value to FP in an FP register. 741 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 742 } 743 case ISD::BR_CC: { 744 SDOperand Chain = Op.getOperand(0); 745 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 746 SDOperand LHS = Op.getOperand(2); 747 SDOperand RHS = Op.getOperand(3); 748 SDOperand Dest = Op.getOperand(4); 749 unsigned Opc, SPCC = ~0U; 750 751 // If this is a br_cc of a "setcc", and if the setcc got lowered into 752 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 753 LookThroughSetCC(LHS, RHS, CC, SPCC); 754 755 // Get the condition flag. 756 SDOperand CompareFlag; 757 if (LHS.getValueType() == MVT::i32) { 758 std::vector<MVT::ValueType> VTs; 759 VTs.push_back(MVT::i32); 760 VTs.push_back(MVT::Flag); 761 SDOperand Ops[2] = { LHS, RHS }; 762 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 763 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 764 Opc = SPISD::BRICC; 765 } else { 766 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 767 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 768 Opc = SPISD::BRFCC; 769 } 770 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 771 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 772 } 773 case ISD::SELECT_CC: { 774 SDOperand LHS = Op.getOperand(0); 775 SDOperand RHS = Op.getOperand(1); 776 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 777 SDOperand TrueVal = Op.getOperand(2); 778 SDOperand FalseVal = Op.getOperand(3); 779 unsigned Opc, SPCC = ~0U; 780 781 // If this is a select_cc of a "setcc", and if the setcc got lowered into 782 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 783 LookThroughSetCC(LHS, RHS, CC, SPCC); 784 785 SDOperand CompareFlag; 786 if (LHS.getValueType() == MVT::i32) { 787 std::vector<MVT::ValueType> VTs; 788 VTs.push_back(LHS.getValueType()); // subcc returns a value 789 VTs.push_back(MVT::Flag); 790 SDOperand Ops[2] = { LHS, RHS }; 791 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 792 Opc = SPISD::SELECT_ICC; 793 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 794 } else { 795 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 796 Opc = SPISD::SELECT_FCC; 797 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 798 } 799 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 800 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 801 } 802 case ISD::VASTART: { 803 // vastart just stores the address of the VarArgsFrameIndex slot into the 804 // memory location argument. 805 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 806 DAG.getRegister(SP::I6, MVT::i32), 807 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 808 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 809 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); 810 } 811 case ISD::VAARG: { 812 SDNode *Node = Op.Val; 813 MVT::ValueType VT = Node->getValueType(0); 814 SDOperand InChain = Node->getOperand(0); 815 SDOperand VAListPtr = Node->getOperand(1); 816 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 817 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0); 818 // Increment the pointer, VAList, to the next vaarg 819 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 820 DAG.getConstant(MVT::getSizeInBits(VT)/8, 821 getPointerTy())); 822 // Store the incremented VAList to the legalized pointer 823 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 824 VAListPtr, SV, 0); 825 // Load the actual argument out of the pointer VAList, unless this is an 826 // f64 load. 827 if (VT != MVT::f64) { 828 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 829 } else { 830 // Otherwise, load it as i64, then do a bitconvert. 831 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 832 std::vector<MVT::ValueType> Tys; 833 Tys.push_back(MVT::f64); 834 Tys.push_back(MVT::Other); 835 // Bit-Convert the value to f64. 836 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 837 V.getValue(1) }; 838 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 839 } 840 } 841 case ISD::DYNAMIC_STACKALLOC: { 842 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 843 SDOperand Size = Op.getOperand(1); // Legalize the size. 844 845 unsigned SPReg = SP::O6; 846 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 847 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 848 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 849 850 // The resultant pointer is actually 16 words from the bottom of the stack, 851 // to provide a register spill area. 852 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 853 DAG.getConstant(96, MVT::i32)); 854 std::vector<MVT::ValueType> Tys; 855 Tys.push_back(MVT::i32); 856 Tys.push_back(MVT::Other); 857 SDOperand Ops[2] = { NewVal, Chain }; 858 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 859 } 860 case ISD::RET: { 861 SDOperand Copy; 862 863 switch(Op.getNumOperands()) { 864 default: 865 assert(0 && "Do not know how to return this many arguments!"); 866 abort(); 867 case 1: 868 return SDOperand(); // ret void is legal 869 case 3: { 870 unsigned ArgReg; 871 switch(Op.getOperand(1).getValueType()) { 872 default: assert(0 && "Unknown type to return!"); 873 case MVT::i32: ArgReg = SP::I0; break; 874 case MVT::f32: ArgReg = SP::F0; break; 875 case MVT::f64: ArgReg = SP::D0; break; 876 } 877 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 878 SDOperand()); 879 break; 880 } 881 case 5: 882 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 883 SDOperand()); 884 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 885 break; 886 } 887 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 888 } 889 // Frame & Return address. Currently unimplemented 890 case ISD::RETURNADDR: break; 891 case ISD::FRAMEADDR: break; 892 } 893 return SDOperand(); 894} 895 896MachineBasicBlock * 897SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 898 MachineBasicBlock *BB) { 899 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 900 unsigned BROpcode; 901 unsigned CC; 902 // Figure out the conditional branch opcode to use for this select_cc. 903 switch (MI->getOpcode()) { 904 default: assert(0 && "Unknown SELECT_CC!"); 905 case SP::SELECT_CC_Int_ICC: 906 case SP::SELECT_CC_FP_ICC: 907 case SP::SELECT_CC_DFP_ICC: 908 BROpcode = SP::BCOND; 909 break; 910 case SP::SELECT_CC_Int_FCC: 911 case SP::SELECT_CC_FP_FCC: 912 case SP::SELECT_CC_DFP_FCC: 913 BROpcode = SP::FBCOND; 914 break; 915 } 916 917 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 918 919 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 920 // control-flow pattern. The incoming instruction knows the destination vreg 921 // to set, the condition code register to branch on, the true/false values to 922 // select between, and a branch opcode to use. 923 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 924 ilist<MachineBasicBlock>::iterator It = BB; 925 ++It; 926 927 // thisMBB: 928 // ... 929 // TrueVal = ... 930 // [f]bCC copy1MBB 931 // fallthrough --> copy0MBB 932 MachineBasicBlock *thisMBB = BB; 933 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 934 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 935 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 936 MachineFunction *F = BB->getParent(); 937 F->getBasicBlockList().insert(It, copy0MBB); 938 F->getBasicBlockList().insert(It, sinkMBB); 939 // Update machine-CFG edges by first adding all successors of the current 940 // block to the new block which will contain the Phi node for the select. 941 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 942 e = BB->succ_end(); i != e; ++i) 943 sinkMBB->addSuccessor(*i); 944 // Next, remove all successors of the current block, and add the true 945 // and fallthrough blocks as its successors. 946 while(!BB->succ_empty()) 947 BB->removeSuccessor(BB->succ_begin()); 948 BB->addSuccessor(copy0MBB); 949 BB->addSuccessor(sinkMBB); 950 951 // copy0MBB: 952 // %FalseValue = ... 953 // # fallthrough to sinkMBB 954 BB = copy0MBB; 955 956 // Update machine-CFG edges 957 BB->addSuccessor(sinkMBB); 958 959 // sinkMBB: 960 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 961 // ... 962 BB = sinkMBB; 963 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 964 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 965 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 966 967 delete MI; // The pseudo instruction is gone now. 968 return BB; 969} 970 971//===----------------------------------------------------------------------===// 972// Instruction Selector Implementation 973//===----------------------------------------------------------------------===// 974 975//===--------------------------------------------------------------------===// 976/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 977/// instructions for SelectionDAG operations. 978/// 979namespace { 980class SparcDAGToDAGISel : public SelectionDAGISel { 981 SparcTargetLowering Lowering; 982 983 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 984 /// make the right decision when generating code for different targets. 985 const SparcSubtarget &Subtarget; 986public: 987 SparcDAGToDAGISel(TargetMachine &TM) 988 : SelectionDAGISel(Lowering), Lowering(TM), 989 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 990 } 991 992 SDNode *Select(SDOperand Op); 993 994 // Complex Pattern Selectors. 995 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); 996 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, 997 SDOperand &Offset); 998 999 /// InstructionSelectBasicBlock - This callback is invoked by 1000 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1001 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 1002 1003 virtual const char *getPassName() const { 1004 return "SPARC DAG->DAG Pattern Instruction Selection"; 1005 } 1006 1007 // Include the pieces autogenerated from the target description. 1008#include "SparcGenDAGISel.inc" 1009}; 1010} // end anonymous namespace 1011 1012/// InstructionSelectBasicBlock - This callback is invoked by 1013/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1014void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 1015 DEBUG(BB->dump()); 1016 1017 // Select target instructions for the DAG. 1018 DAG.setRoot(SelectRoot(DAG.getRoot())); 1019 DAG.RemoveDeadNodes(); 1020 1021 // Emit machine code to BB. 1022 ScheduleAndEmitDAG(DAG); 1023} 1024 1025bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, 1026 SDOperand &Base, SDOperand &Offset) { 1027 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1028 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1029 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1030 return true; 1031 } 1032 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1033 Addr.getOpcode() == ISD::TargetGlobalAddress) 1034 return false; // direct calls. 1035 1036 if (Addr.getOpcode() == ISD::ADD) { 1037 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1038 if (Predicate_simm13(CN)) { 1039 if (FrameIndexSDNode *FIN = 1040 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1041 // Constant offset from frame ref. 1042 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1043 } else { 1044 Base = Addr.getOperand(0); 1045 } 1046 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1047 return true; 1048 } 1049 } 1050 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1051 Base = Addr.getOperand(1); 1052 Offset = Addr.getOperand(0).getOperand(0); 1053 return true; 1054 } 1055 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1056 Base = Addr.getOperand(0); 1057 Offset = Addr.getOperand(1).getOperand(0); 1058 return true; 1059 } 1060 } 1061 Base = Addr; 1062 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1063 return true; 1064} 1065 1066bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, 1067 SDOperand &R1, SDOperand &R2) { 1068 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1069 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1070 Addr.getOpcode() == ISD::TargetGlobalAddress) 1071 return false; // direct calls. 1072 1073 if (Addr.getOpcode() == ISD::ADD) { 1074 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1075 Predicate_simm13(Addr.getOperand(1).Val)) 1076 return false; // Let the reg+imm pattern catch this! 1077 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1078 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1079 return false; // Let the reg+imm pattern catch this! 1080 R1 = Addr.getOperand(0); 1081 R2 = Addr.getOperand(1); 1082 return true; 1083 } 1084 1085 R1 = Addr; 1086 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1087 return true; 1088} 1089 1090SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1091 SDNode *N = Op.Val; 1092 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1093 N->getOpcode() < SPISD::FIRST_NUMBER) 1094 return NULL; // Already selected. 1095 1096 switch (N->getOpcode()) { 1097 default: break; 1098 case ISD::SDIV: 1099 case ISD::UDIV: { 1100 // FIXME: should use a custom expander to expose the SRA to the dag. 1101 SDOperand DivLHS = N->getOperand(0); 1102 SDOperand DivRHS = N->getOperand(1); 1103 AddToISelQueue(DivLHS); 1104 AddToISelQueue(DivRHS); 1105 1106 // Set the Y register to the high-part. 1107 SDOperand TopPart; 1108 if (N->getOpcode() == ISD::SDIV) { 1109 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1110 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1111 } else { 1112 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1113 } 1114 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1115 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1116 1117 // FIXME: Handle div by immediate. 1118 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1119 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1120 TopPart); 1121 } 1122 case ISD::MULHU: 1123 case ISD::MULHS: { 1124 // FIXME: Handle mul by immediate. 1125 SDOperand MulLHS = N->getOperand(0); 1126 SDOperand MulRHS = N->getOperand(1); 1127 AddToISelQueue(MulLHS); 1128 AddToISelQueue(MulRHS); 1129 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1130 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1131 MulLHS, MulRHS); 1132 // The high part is in the Y register. 1133 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1134 return NULL; 1135 } 1136 } 1137 1138 return SelectCode(Op); 1139} 1140 1141 1142/// createSparcISelDag - This pass converts a legalized DAG into a 1143/// SPARC-specific DAG, ready for instruction scheduling. 1144/// 1145FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1146 return new SparcDAGToDAGISel(TM); 1147} 1148