SparcISelDAGToDAG.cpp revision 99cf50937d55381fbcdb506e61fb46ade774e7ee 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Support/Debug.h"
26#include <iostream>
27using namespace llvm;
28
29//===----------------------------------------------------------------------===//
30// TargetLowering Implementation
31//===----------------------------------------------------------------------===//
32
33namespace V8ISD {
34  enum {
35    FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36    CMPICC,   // Compare two GPR operands, set icc.
37    CMPFCC,   // Compare two FP operands, set fcc.
38    BRICC,    // Branch to dest on icc condition
39    BRFCC,    // Branch to dest on fcc condition
40
41    Hi, Lo,   // Hi/Lo operations, typically on a global address.
42
43    FTOI,     // FP to Int within a FP register.
44    ITOF,     // Int to FP within a FP register.
45
46    SELECT_ICC, // Select between two values using the current ICC flags.
47    SELECT_FCC, // Select between two values using the current FCC flags.
48
49    RET_FLAG,   // Return with a flag operand.
50  };
51}
52
53namespace {
54  class SparcV8TargetLowering : public TargetLowering {
55    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
56  public:
57    SparcV8TargetLowering(TargetMachine &TM);
58    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59    virtual std::vector<SDOperand>
60      LowerArguments(Function &F, SelectionDAG &DAG);
61    virtual std::pair<SDOperand, SDOperand>
62      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
63                  unsigned CC,
64                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
65                  SelectionDAG &DAG);
66
67    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
68                                    SelectionDAG &DAG);
69    virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
70                                   Value *VAListV, SelectionDAG &DAG);
71    virtual std::pair<SDOperand,SDOperand>
72      LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
73                 const Type *ArgTy, SelectionDAG &DAG);
74    virtual std::pair<SDOperand, SDOperand>
75      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
76                              SelectionDAG &DAG);
77    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
78                                                       MachineBasicBlock *MBB);
79
80    virtual const char *getTargetNodeName(unsigned Opcode) const;
81  };
82}
83
84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
85  : TargetLowering(TM) {
86
87  // Set up the register classes.
88  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
89  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
90  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
91
92  // Custom legalize GlobalAddress nodes into LO/HI parts.
93  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
95
96  // Sparc doesn't have sext_inreg, replace them with shl/sra
97  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
98  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
99  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
100
101  // Sparc has no REM operation.
102  setOperationAction(ISD::UREM, MVT::i32, Expand);
103  setOperationAction(ISD::SREM, MVT::i32, Expand);
104
105  // Custom expand fp<->sint
106  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
107  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
108
109  // Expand fp<->uint
110  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
111  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
112
113  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
114  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
115
116  // Turn FP extload into load/fextend
117  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
118
119  // Sparc has no select or setcc: expand to SELECT_CC.
120  setOperationAction(ISD::SELECT, MVT::i32, Expand);
121  setOperationAction(ISD::SELECT, MVT::f32, Expand);
122  setOperationAction(ISD::SELECT, MVT::f64, Expand);
123  setOperationAction(ISD::SETCC, MVT::i32, Expand);
124  setOperationAction(ISD::SETCC, MVT::f32, Expand);
125  setOperationAction(ISD::SETCC, MVT::f64, Expand);
126
127  // Sparc doesn't have BRCOND either, it has BR_CC.
128  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
130  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
131  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
132  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
133  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
134
135  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
136  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
138
139  // V8 has no intrinsics for these particular operations.
140  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
141  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
142  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
143
144  setOperationAction(ISD::FSIN , MVT::f64, Expand);
145  setOperationAction(ISD::FCOS , MVT::f64, Expand);
146  setOperationAction(ISD::FSIN , MVT::f32, Expand);
147  setOperationAction(ISD::FCOS , MVT::f32, Expand);
148  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
149  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
150  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
151  setOperationAction(ISD::ROTL , MVT::i32, Expand);
152  setOperationAction(ISD::ROTR , MVT::i32, Expand);
153  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
154
155  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
156  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
157  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
158
159  // We don't have line number support yet.
160  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
161  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
162  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
163
164  // Expand these to their default code.
165  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
166  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
167  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
168
169  setStackPointerRegisterToSaveRestore(V8::O6);
170
171  computeRegisterProperties();
172}
173
174const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
175  switch (Opcode) {
176  default: return 0;
177  case V8ISD::CMPICC:     return "V8ISD::CMPICC";
178  case V8ISD::CMPFCC:     return "V8ISD::CMPFCC";
179  case V8ISD::BRICC:      return "V8ISD::BRICC";
180  case V8ISD::BRFCC:      return "V8ISD::BRFCC";
181  case V8ISD::Hi:         return "V8ISD::Hi";
182  case V8ISD::Lo:         return "V8ISD::Lo";
183  case V8ISD::FTOI:       return "V8ISD::FTOI";
184  case V8ISD::ITOF:       return "V8ISD::ITOF";
185  case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
186  case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
187  case V8ISD::RET_FLAG:   return "V8ISD::RET_FLAG";
188  }
189}
190
191/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
192/// either one or two GPRs, including FP values.  TODO: we should pass FP values
193/// in FP registers for fastcc functions.
194std::vector<SDOperand>
195SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
196  MachineFunction &MF = DAG.getMachineFunction();
197  SSARegMap *RegMap = MF.getSSARegMap();
198  std::vector<SDOperand> ArgValues;
199
200  static const unsigned ArgRegs[] = {
201    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
202  };
203
204  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
205  unsigned ArgOffset = 68;
206
207  SDOperand Root = DAG.getRoot();
208  std::vector<SDOperand> OutChains;
209
210  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
211    MVT::ValueType ObjectVT = getValueType(I->getType());
212
213    switch (ObjectVT) {
214    default: assert(0 && "Unhandled argument type!");
215    case MVT::i1:
216    case MVT::i8:
217    case MVT::i16:
218    case MVT::i32:
219      if (I->use_empty()) {                // Argument is dead.
220        if (CurArgReg < ArgRegEnd) ++CurArgReg;
221        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
222      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
223        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
224        MF.addLiveIn(*CurArgReg++, VReg);
225        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
226        if (ObjectVT != MVT::i32) {
227          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
228                                                       : ISD::AssertZext;
229          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
230                            DAG.getValueType(ObjectVT));
231          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
232        }
233        ArgValues.push_back(Arg);
234      } else {
235        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
236        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
237        SDOperand Load;
238        if (ObjectVT == MVT::i32) {
239          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
240        } else {
241          unsigned LoadOp =
242            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
243
244          // Sparc is big endian, so add an offset based on the ObjectVT.
245          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
246          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
247                              DAG.getConstant(Offset, MVT::i32));
248          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
249                                DAG.getSrcValue(0), ObjectVT);
250          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
251        }
252        ArgValues.push_back(Load);
253      }
254
255      ArgOffset += 4;
256      break;
257    case MVT::f32:
258      if (I->use_empty()) {                // Argument is dead.
259        if (CurArgReg < ArgRegEnd) ++CurArgReg;
260        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
261      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
262        // FP value is passed in an integer register.
263        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
264        MF.addLiveIn(*CurArgReg++, VReg);
265        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
266
267        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
268        ArgValues.push_back(Arg);
269      }
270      ArgOffset += 4;
271      break;
272
273    case MVT::i64:
274    case MVT::f64:
275      if (I->use_empty()) {                // Argument is dead.
276        if (CurArgReg < ArgRegEnd) ++CurArgReg;
277        if (CurArgReg < ArgRegEnd) ++CurArgReg;
278        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
279      } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
280                 ((CurArgReg-ArgRegs) & 1) == 0) {
281        // If this is a double argument and the whole thing lives on the stack,
282        // and the argument is aligned, load the double straight from the stack.
283        // We can't do a load in cases like void foo([6ints], int,double),
284        // because the double wouldn't be aligned!
285        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
286        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
287        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
288                                        DAG.getSrcValue(0)));
289      } else {
290        SDOperand HiVal;
291        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
292          unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
293          MF.addLiveIn(*CurArgReg++, VRegHi);
294          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
295        } else {
296          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
297          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
298          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
299        }
300
301        SDOperand LoVal;
302        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
303          unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
304          MF.addLiveIn(*CurArgReg++, VRegLo);
305          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
306        } else {
307          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
308          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
309          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
310        }
311
312        // Compose the two halves together into an i64 unit.
313        SDOperand WholeValue =
314          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
315
316        // If we want a double, do a bit convert.
317        if (ObjectVT == MVT::f64)
318          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
319
320        ArgValues.push_back(WholeValue);
321      }
322      ArgOffset += 8;
323      break;
324    }
325  }
326
327  // Store remaining ArgRegs to the stack if this is a varargs function.
328  if (F.getFunctionType()->isVarArg()) {
329    // Remember the vararg offset for the va_start implementation.
330    VarArgsFrameOffset = ArgOffset;
331
332    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
333      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
334      MF.addLiveIn(*CurArgReg, VReg);
335      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
336
337      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
338      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
339
340      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
341                                      Arg, FIPtr, DAG.getSrcValue(0)));
342      ArgOffset += 4;
343    }
344  }
345
346  if (!OutChains.empty())
347    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
348
349  // Finally, inform the code generator which regs we return values in.
350  switch (getValueType(F.getReturnType())) {
351  default: assert(0 && "Unknown type!");
352  case MVT::isVoid: break;
353  case MVT::i1:
354  case MVT::i8:
355  case MVT::i16:
356  case MVT::i32:
357    MF.addLiveOut(V8::I0);
358    break;
359  case MVT::i64:
360    MF.addLiveOut(V8::I0);
361    MF.addLiveOut(V8::I1);
362    break;
363  case MVT::f32:
364    MF.addLiveOut(V8::F0);
365    break;
366  case MVT::f64:
367    MF.addLiveOut(V8::D0);
368    break;
369  }
370
371  return ArgValues;
372}
373
374std::pair<SDOperand, SDOperand>
375SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
376                                   bool isVarArg, unsigned CC,
377                                   bool isTailCall, SDOperand Callee,
378                                   ArgListTy &Args, SelectionDAG &DAG) {
379  MachineFunction &MF = DAG.getMachineFunction();
380  // Count the size of the outgoing arguments.
381  unsigned ArgsSize = 0;
382  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
383    switch (getValueType(Args[i].second)) {
384    default: assert(0 && "Unknown value type!");
385    case MVT::i1:
386    case MVT::i8:
387    case MVT::i16:
388    case MVT::i32:
389    case MVT::f32:
390      ArgsSize += 4;
391      break;
392    case MVT::i64:
393    case MVT::f64:
394      ArgsSize += 8;
395      break;
396    }
397  }
398  if (ArgsSize > 4*6)
399    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
400  else
401    ArgsSize = 0;
402
403  // Keep stack frames 8-byte aligned.
404  ArgsSize = (ArgsSize+7) & ~7;
405
406  Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
407                      DAG.getConstant(ArgsSize, getPointerTy()));
408
409  SDOperand StackPtr, NullSV;
410  std::vector<SDOperand> Stores;
411  std::vector<SDOperand> RegValuesToPass;
412  unsigned ArgOffset = 68;
413  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
414    SDOperand Val = Args[i].first;
415    MVT::ValueType ObjectVT = Val.getValueType();
416    SDOperand ValToStore(0, 0);
417    unsigned ObjSize;
418    switch (ObjectVT) {
419    default: assert(0 && "Unhandled argument type!");
420    case MVT::i1:
421    case MVT::i8:
422    case MVT::i16:
423      // Promote the integer to 32-bits.  If the input type is signed, use a
424      // sign extend, otherwise use a zero extend.
425      if (Args[i].second->isSigned())
426        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
427      else
428        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
429      // FALL THROUGH
430    case MVT::i32:
431      ObjSize = 4;
432
433      if (RegValuesToPass.size() >= 6) {
434        ValToStore = Val;
435      } else {
436        RegValuesToPass.push_back(Val);
437      }
438      break;
439    case MVT::f32:
440      ObjSize = 4;
441      if (RegValuesToPass.size() >= 6) {
442        ValToStore = Val;
443      } else {
444        // Convert this to a FP value in an int reg.
445        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
446        RegValuesToPass.push_back(Val);
447      }
448      break;
449    case MVT::f64:
450      ObjSize = 8;
451      // If we can store this directly into the outgoing slot, do so.  We can
452      // do this when all ArgRegs are used and if the outgoing slot is aligned.
453      // FIXME: McGill/misr fails with this.
454      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
455        ValToStore = Val;
456        break;
457      }
458
459      // Otherwise, convert this to a FP value in int regs.
460      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
461      // FALL THROUGH
462    case MVT::i64:
463      ObjSize = 8;
464      if (RegValuesToPass.size() >= 6) {
465        ValToStore = Val;    // Whole thing is passed in memory.
466        break;
467      }
468
469      // Split the value into top and bottom part.  Top part goes in a reg.
470      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
471                                 DAG.getConstant(1, MVT::i32));
472      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
473                                 DAG.getConstant(0, MVT::i32));
474      RegValuesToPass.push_back(Hi);
475
476      if (RegValuesToPass.size() >= 6) {
477        ValToStore = Lo;
478        ArgOffset += 4;
479        ObjSize = 4;
480      } else {
481        RegValuesToPass.push_back(Lo);
482      }
483      break;
484    }
485
486    if (ValToStore.Val) {
487      if (!StackPtr.Val) {
488        StackPtr = DAG.getRegister(V8::O6, MVT::i32);
489        NullSV = DAG.getSrcValue(NULL);
490      }
491      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
492      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
493      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
494                                   ValToStore, PtrOff, NullSV));
495    }
496    ArgOffset += ObjSize;
497  }
498
499  // Emit all stores, make sure the occur before any copies into physregs.
500  if (!Stores.empty())
501    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
502
503  static const unsigned ArgRegs[] = {
504    V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
505  };
506
507  // Build a sequence of copy-to-reg nodes chained together with token chain
508  // and flag operands which copy the outgoing args into O[0-5].
509  SDOperand InFlag;
510  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
511    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
512    InFlag = Chain.getValue(1);
513  }
514
515  // If the callee is a GlobalAddress node (quite common, every direct call is)
516  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
517  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
518    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
519
520  std::vector<MVT::ValueType> NodeTys;
521  NodeTys.push_back(MVT::Other);   // Returns a chain
522  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
523  if (InFlag.Val)
524    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
525  else
526    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
527  InFlag = Chain.getValue(1);
528
529  MVT::ValueType RetTyVT = getValueType(RetTy);
530  SDOperand RetVal;
531  if (RetTyVT != MVT::isVoid) {
532    switch (RetTyVT) {
533    default: assert(0 && "Unknown value type to return!");
534    case MVT::i1:
535    case MVT::i8:
536    case MVT::i16:
537      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
538      Chain = RetVal.getValue(1);
539
540      // Add a note to keep track of whether it is sign or zero extended.
541      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
542                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
543      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
544      break;
545    case MVT::i32:
546      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
547      Chain = RetVal.getValue(1);
548      break;
549    case MVT::f32:
550      RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
551      Chain = RetVal.getValue(1);
552      break;
553    case MVT::f64:
554      RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
555      Chain = RetVal.getValue(1);
556      break;
557    case MVT::i64:
558      SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
559      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
560                                        Lo.getValue(2));
561      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
562      Chain = Hi.getValue(1);
563      break;
564    }
565  }
566
567  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
568                      DAG.getConstant(ArgsSize, getPointerTy()));
569
570  return std::make_pair(RetVal, Chain);
571}
572
573SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
574                                               SelectionDAG &DAG) {
575  SDOperand Copy;
576  switch (Op.getValueType()) {
577  default: assert(0 && "Unknown type to return!");
578  case MVT::i32:
579    Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
580    break;
581  case MVT::f32:
582    Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
583    break;
584  case MVT::f64:
585    Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
586    break;
587  case MVT::i64:
588    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
589                               DAG.getConstant(1, MVT::i32));
590    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
591                               DAG.getConstant(0, MVT::i32));
592    Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
593    Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
594    break;
595  }
596  return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
597}
598
599SDOperand SparcV8TargetLowering::
600LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
601             SelectionDAG &DAG) {
602
603  SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
604                                 DAG.getRegister(V8::I6, MVT::i32),
605                                 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
606  return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
607                     VAListP, DAG.getSrcValue(VAListV));
608}
609
610std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
611LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
612           const Type *ArgTy, SelectionDAG &DAG) {
613  // Load the pointer out of the valist.
614  SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
615                              VAListP, DAG.getSrcValue(VAListV));
616  MVT::ValueType ArgVT = getValueType(ArgTy);
617  SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
618                              Ptr, DAG.getSrcValue(NULL));
619  // Increment the pointer.
620  Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
621                    DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
622  // Store it back to the valist.
623  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
624                      VAListP, DAG.getSrcValue(VAListV));
625  return std::make_pair(Val, Chain);
626}
627
628std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
629LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
630                        SelectionDAG &DAG) {
631  assert(0 && "Unimp");
632  abort();
633}
634
635SDOperand SparcV8TargetLowering::
636LowerOperation(SDOperand Op, SelectionDAG &DAG) {
637  switch (Op.getOpcode()) {
638  default: assert(0 && "Should not custom lower this!");
639  case ISD::GlobalAddress: {
640    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
641    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
642    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
643    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
644    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
645  }
646  case ISD::ConstantPool: {
647    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
648    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
649    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
650    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
651    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
652  }
653  case ISD::FP_TO_SINT:
654    // Convert the fp value to integer in an FP register.
655    assert(Op.getValueType() == MVT::i32);
656    Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
657    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
658  case ISD::SINT_TO_FP: {
659    assert(Op.getOperand(0).getValueType() == MVT::i32);
660    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
661    // Convert the int value to FP in an FP register.
662    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
663  }
664  case ISD::BR_CC: {
665    SDOperand Chain = Op.getOperand(0);
666    SDOperand CC = Op.getOperand(1);
667    SDOperand LHS = Op.getOperand(2);
668    SDOperand RHS = Op.getOperand(3);
669    SDOperand Dest = Op.getOperand(4);
670
671    // Get the condition flag.
672    if (LHS.getValueType() == MVT::i32) {
673      std::vector<MVT::ValueType> VTs;
674      VTs.push_back(MVT::i32);
675      VTs.push_back(MVT::Flag);
676      std::vector<SDOperand> Ops;
677      Ops.push_back(LHS);
678      Ops.push_back(RHS);
679      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
680      return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
681    } else {
682      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
683      return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
684    }
685  }
686  case ISD::SELECT_CC: {
687    SDOperand LHS = Op.getOperand(0);
688    SDOperand RHS = Op.getOperand(1);
689    unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
690    SDOperand TrueVal = Op.getOperand(2);
691    SDOperand FalseVal = Op.getOperand(3);
692
693    SDOperand CompareFlag;
694    unsigned Opc;
695    if (LHS.getValueType() == MVT::i32) {
696      std::vector<MVT::ValueType> VTs;
697      VTs.push_back(LHS.getValueType());   // subcc returns a value
698      VTs.push_back(MVT::Flag);
699      std::vector<SDOperand> Ops;
700      Ops.push_back(LHS);
701      Ops.push_back(RHS);
702      CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
703      Opc = V8ISD::SELECT_ICC;
704    } else {
705      CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
706      Opc = V8ISD::SELECT_FCC;
707    }
708    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
709                       DAG.getConstant(CC, MVT::i32), CompareFlag);
710  }
711  }
712}
713
714MachineBasicBlock *
715SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
716                                               MachineBasicBlock *BB) {
717  unsigned BROpcode;
718  // Figure out the conditional branch opcode to use for this select_cc.
719  switch (MI->getOpcode()) {
720  default: assert(0 && "Unknown SELECT_CC!");
721  case V8::SELECT_CC_Int_ICC:
722  case V8::SELECT_CC_FP_ICC:
723  case V8::SELECT_CC_DFP_ICC:
724    // Integer compare.
725    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
726    default: assert(0 && "Unknown integer condition code!");
727    case ISD::SETEQ:  BROpcode = V8::BE; break;
728    case ISD::SETNE:  BROpcode = V8::BNE; break;
729    case ISD::SETLT:  BROpcode = V8::BL; break;
730    case ISD::SETGT:  BROpcode = V8::BG; break;
731    case ISD::SETLE:  BROpcode = V8::BLE; break;
732    case ISD::SETGE:  BROpcode = V8::BGE; break;
733    case ISD::SETULT: BROpcode = V8::BCS; break;
734    case ISD::SETULE: BROpcode = V8::BLEU; break;
735    case ISD::SETUGT: BROpcode = V8::BGU; break;
736    case ISD::SETUGE: BROpcode = V8::BCC; break;
737    }
738    break;
739  case V8::SELECT_CC_Int_FCC:
740  case V8::SELECT_CC_FP_FCC:
741  case V8::SELECT_CC_DFP_FCC:
742    // FP compare.
743    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
744    default: assert(0 && "Unknown fp condition code!");
745    case ISD::SETEQ:  BROpcode = V8::FBE; break;
746    case ISD::SETNE:  BROpcode = V8::FBNE; break;
747    case ISD::SETLT:  BROpcode = V8::FBL; break;
748    case ISD::SETGT:  BROpcode = V8::FBG; break;
749    case ISD::SETLE:  BROpcode = V8::FBLE; break;
750    case ISD::SETGE:  BROpcode = V8::FBGE; break;
751    case ISD::SETULT: BROpcode = V8::FBUL; break;
752    case ISD::SETULE: BROpcode = V8::FBULE; break;
753    case ISD::SETUGT: BROpcode = V8::FBUG; break;
754    case ISD::SETUGE: BROpcode = V8::FBUGE; break;
755    case ISD::SETUO:  BROpcode = V8::FBU; break;
756    case ISD::SETO:   BROpcode = V8::FBO; break;
757    case ISD::SETONE: BROpcode = V8::FBLG; break;
758    case ISD::SETUEQ: BROpcode = V8::FBUE; break;
759    }
760    break;
761  }
762
763  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
764  // control-flow pattern.  The incoming instruction knows the destination vreg
765  // to set, the condition code register to branch on, the true/false values to
766  // select between, and a branch opcode to use.
767  const BasicBlock *LLVM_BB = BB->getBasicBlock();
768  ilist<MachineBasicBlock>::iterator It = BB;
769  ++It;
770
771  //  thisMBB:
772  //  ...
773  //   TrueVal = ...
774  //   [f]bCC copy1MBB
775  //   fallthrough --> copy0MBB
776  MachineBasicBlock *thisMBB = BB;
777  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
778  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
779  BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
780  MachineFunction *F = BB->getParent();
781  F->getBasicBlockList().insert(It, copy0MBB);
782  F->getBasicBlockList().insert(It, sinkMBB);
783  // Update machine-CFG edges
784  BB->addSuccessor(copy0MBB);
785  BB->addSuccessor(sinkMBB);
786
787  //  copy0MBB:
788  //   %FalseValue = ...
789  //   # fallthrough to sinkMBB
790  BB = copy0MBB;
791
792  // Update machine-CFG edges
793  BB->addSuccessor(sinkMBB);
794
795  //  sinkMBB:
796  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
797  //  ...
798  BB = sinkMBB;
799  BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
800    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
801    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
802
803  delete MI;   // The pseudo instruction is gone now.
804  return BB;
805}
806
807//===----------------------------------------------------------------------===//
808// Instruction Selector Implementation
809//===----------------------------------------------------------------------===//
810
811//===--------------------------------------------------------------------===//
812/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
813/// instructions for SelectionDAG operations.
814///
815namespace {
816class SparcV8DAGToDAGISel : public SelectionDAGISel {
817  SparcV8TargetLowering V8Lowering;
818public:
819  SparcV8DAGToDAGISel(TargetMachine &TM)
820    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
821
822  SDOperand Select(SDOperand Op);
823
824  // Complex Pattern Selectors.
825  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
826  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
827
828  /// InstructionSelectBasicBlock - This callback is invoked by
829  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
830  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
831
832  virtual const char *getPassName() const {
833    return "PowerPC DAG->DAG Pattern Instruction Selection";
834  }
835
836  // Include the pieces autogenerated from the target description.
837#include "SparcV8GenDAGISel.inc"
838};
839}  // end anonymous namespace
840
841/// InstructionSelectBasicBlock - This callback is invoked by
842/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
843void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
844  DEBUG(BB->dump());
845
846  // Select target instructions for the DAG.
847  DAG.setRoot(Select(DAG.getRoot()));
848  CodeGenMap.clear();
849  DAG.RemoveDeadNodes();
850
851  // Emit machine code to BB.
852  ScheduleAndEmitDAG(DAG);
853}
854
855bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
856                                       SDOperand &Offset) {
857  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
858    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
859    Offset = CurDAG->getTargetConstant(0, MVT::i32);
860    return true;
861  }
862
863  if (Addr.getOpcode() == ISD::ADD) {
864    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
865      if (Predicate_simm13(CN)) {
866        if (FrameIndexSDNode *FIN =
867                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
868          // Constant offset from frame ref.
869          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
870        } else {
871          Base = Select(Addr.getOperand(0));
872        }
873        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
874        return true;
875      }
876    }
877    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
878      Base = Select(Addr.getOperand(1));
879      Offset = Addr.getOperand(0).getOperand(0);
880      return true;
881    }
882    if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
883      Base = Select(Addr.getOperand(0));
884      Offset = Addr.getOperand(1).getOperand(0);
885      return true;
886    }
887  }
888  Base = Select(Addr);
889  Offset = CurDAG->getTargetConstant(0, MVT::i32);
890  return true;
891}
892
893bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
894                                       SDOperand &R2) {
895  if (Addr.getOpcode() == ISD::FrameIndex) return false;
896  if (Addr.getOpcode() == ISD::ADD) {
897    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
898        Predicate_simm13(Addr.getOperand(1).Val))
899      return false;  // Let the reg+imm pattern catch this!
900    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
901        Addr.getOperand(1).getOpcode() == V8ISD::Lo)
902      return false;  // Let the reg+imm pattern catch this!
903    R1 = Select(Addr.getOperand(0));
904    R2 = Select(Addr.getOperand(1));
905    return true;
906  }
907
908  R1 = Select(Addr);
909  R2 = CurDAG->getRegister(V8::G0, MVT::i32);
910  return true;
911}
912
913SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
914  SDNode *N = Op.Val;
915  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
916      N->getOpcode() < V8ISD::FIRST_NUMBER)
917    return Op;   // Already selected.
918                 // If this has already been converted, use it.
919  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
920  if (CGMI != CodeGenMap.end()) return CGMI->second;
921
922  switch (N->getOpcode()) {
923  default: break;
924  case ISD::FrameIndex: {
925    int FI = cast<FrameIndexSDNode>(N)->getIndex();
926    if (N->hasOneUse())
927      return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
928                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
929                                  CurDAG->getTargetConstant(0, MVT::i32));
930    return CodeGenMap[Op] =
931      CurDAG->getTargetNode(V8::ADDri, MVT::i32,
932                            CurDAG->getTargetFrameIndex(FI, MVT::i32),
933                            CurDAG->getTargetConstant(0, MVT::i32));
934  }
935  case ISD::ADD_PARTS: {
936    SDOperand LHSL = Select(N->getOperand(0));
937    SDOperand LHSH = Select(N->getOperand(1));
938    SDOperand RHSL = Select(N->getOperand(2));
939    SDOperand RHSH = Select(N->getOperand(3));
940    // FIXME, handle immediate RHS.
941    SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
942                                          LHSL, RHSL);
943    SDOperand Hi  = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
944                                          Low.getValue(1));
945    CodeGenMap[SDOperand(N, 0)] = Low;
946    CodeGenMap[SDOperand(N, 1)] = Hi;
947    return Op.ResNo ? Hi : Low;
948  }
949  case ISD::SUB_PARTS: {
950    SDOperand LHSL = Select(N->getOperand(0));
951    SDOperand LHSH = Select(N->getOperand(1));
952    SDOperand RHSL = Select(N->getOperand(2));
953    SDOperand RHSH = Select(N->getOperand(3));
954    // FIXME, handle immediate RHS.
955    SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
956                                          LHSL, RHSL);
957    SDOperand Hi  = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
958                                          Low.getValue(1));
959    CodeGenMap[SDOperand(N, 0)] = Low;
960    CodeGenMap[SDOperand(N, 1)] = Hi;
961    return Op.ResNo ? Hi : Low;
962  }
963  case ISD::SDIV:
964  case ISD::UDIV: {
965    // FIXME: should use a custom expander to expose the SRA to the dag.
966    SDOperand DivLHS = Select(N->getOperand(0));
967    SDOperand DivRHS = Select(N->getOperand(1));
968
969    // Set the Y register to the high-part.
970    SDOperand TopPart;
971    if (N->getOpcode() == ISD::SDIV) {
972      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
973                                      CurDAG->getTargetConstant(31, MVT::i32));
974    } else {
975      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
976    }
977    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
978                                    CurDAG->getRegister(V8::G0, MVT::i32));
979
980    // FIXME: Handle div by immediate.
981    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
982    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
983  }
984  case ISD::MULHU:
985  case ISD::MULHS: {
986    // FIXME: Handle mul by immediate.
987    SDOperand MulLHS = Select(N->getOperand(0));
988    SDOperand MulRHS = Select(N->getOperand(1));
989    unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
990    SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
991                                          MulLHS, MulRHS);
992    // The high part is in the Y register.
993    return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
994  }
995  case ISD::CALL:
996    // FIXME: This is a workaround for a bug in tblgen.
997  { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
998    // Emits: (CALL:void (tglobaladdr:i32):$dst)
999    // Pattern complexity = 2  cost = 1
1000    SDOperand N1 = N->getOperand(1);
1001    if (N1.getOpcode() != ISD::TargetGlobalAddress &&
1002        N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
1003    SDOperand InFlag = SDOperand(0, 0);
1004    SDOperand Chain = N->getOperand(0);
1005    SDOperand Tmp0 = N1;
1006    Chain = Select(Chain);
1007    SDOperand Result;
1008    if (N->getNumOperands() == 3) {
1009      InFlag = Select(N->getOperand(2));
1010      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1011                                     Chain, InFlag);
1012    } else {
1013      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1014                                     Chain);
1015    }
1016    Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
1017     CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
1018    return Result.getValue(Op.ResNo);
1019  }
1020    P47Fail:;
1021
1022  }
1023
1024  return SelectCode(Op);
1025}
1026
1027
1028/// createPPCISelDag - This pass converts a legalized DAG into a
1029/// PowerPC-specific DAG, ready for instruction scheduling.
1030///
1031FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1032  return new SparcV8DAGToDAGISel(TM);
1033}
1034