SparcISelDAGToDAG.cpp revision a7dc4a59cbb19cfb5dbc0f9ca500f26dddfbb7f6
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/CodeGen/SSARegMap.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Debug.h" 27#include <iostream> 28#include <set> 29using namespace llvm; 30 31//===----------------------------------------------------------------------===// 32// TargetLowering Implementation 33//===----------------------------------------------------------------------===// 34 35namespace SPISD { 36 enum { 37 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 38 CMPICC, // Compare two GPR operands, set icc. 39 CMPFCC, // Compare two FP operands, set fcc. 40 BRICC, // Branch to dest on icc condition 41 BRFCC, // Branch to dest on fcc condition 42 SELECT_ICC, // Select between two values using the current ICC flags. 43 SELECT_FCC, // Select between two values using the current FCC flags. 44 45 Hi, Lo, // Hi/Lo operations, typically on a global address. 46 47 FTOI, // FP to Int within a FP register. 48 ITOF, // Int to FP within a FP register. 49 50 CALL, // A call instruction. 51 RET_FLAG // Return with a flag operand. 52 }; 53} 54 55/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 56/// condition. 57static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 58 switch (CC) { 59 default: assert(0 && "Unknown integer condition code!"); 60 case ISD::SETEQ: return SPCC::ICC_E; 61 case ISD::SETNE: return SPCC::ICC_NE; 62 case ISD::SETLT: return SPCC::ICC_L; 63 case ISD::SETGT: return SPCC::ICC_G; 64 case ISD::SETLE: return SPCC::ICC_LE; 65 case ISD::SETGE: return SPCC::ICC_GE; 66 case ISD::SETULT: return SPCC::ICC_CS; 67 case ISD::SETULE: return SPCC::ICC_LEU; 68 case ISD::SETUGT: return SPCC::ICC_GU; 69 case ISD::SETUGE: return SPCC::ICC_CC; 70 } 71} 72 73/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 74/// FCC condition. 75static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 76 switch (CC) { 77 default: assert(0 && "Unknown fp condition code!"); 78 case ISD::SETEQ: 79 case ISD::SETOEQ: return SPCC::FCC_E; 80 case ISD::SETNE: 81 case ISD::SETUNE: return SPCC::FCC_NE; 82 case ISD::SETLT: 83 case ISD::SETOLT: return SPCC::FCC_L; 84 case ISD::SETGT: 85 case ISD::SETOGT: return SPCC::FCC_G; 86 case ISD::SETLE: 87 case ISD::SETOLE: return SPCC::FCC_LE; 88 case ISD::SETGE: 89 case ISD::SETOGE: return SPCC::FCC_GE; 90 case ISD::SETULT: return SPCC::FCC_UL; 91 case ISD::SETULE: return SPCC::FCC_ULE; 92 case ISD::SETUGT: return SPCC::FCC_UG; 93 case ISD::SETUGE: return SPCC::FCC_UGE; 94 case ISD::SETUO: return SPCC::FCC_U; 95 case ISD::SETO: return SPCC::FCC_O; 96 case ISD::SETONE: return SPCC::FCC_LG; 97 case ISD::SETUEQ: return SPCC::FCC_UE; 98 } 99} 100 101namespace { 102 class SparcTargetLowering : public TargetLowering { 103 int VarArgsFrameOffset; // Frame offset to start of varargs area. 104 public: 105 SparcTargetLowering(TargetMachine &TM); 106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 107 108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 109 /// in Mask are known to be either zero or one and return them in the 110 /// KnownZero/KnownOne bitsets. 111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 112 uint64_t Mask, 113 uint64_t &KnownZero, 114 uint64_t &KnownOne, 115 unsigned Depth = 0) const; 116 117 virtual std::vector<SDOperand> 118 LowerArguments(Function &F, SelectionDAG &DAG); 119 virtual std::pair<SDOperand, SDOperand> 120 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 121 unsigned CC, 122 bool isTailCall, SDOperand Callee, ArgListTy &Args, 123 SelectionDAG &DAG); 124 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 125 MachineBasicBlock *MBB); 126 127 virtual const char *getTargetNodeName(unsigned Opcode) const; 128 }; 129} 130 131SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 132 : TargetLowering(TM) { 133 134 // Set up the register classes. 135 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 136 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 137 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 138 139 // Custom legalize GlobalAddress nodes into LO/HI parts. 140 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 141 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 142 143 // Sparc doesn't have sext_inreg, replace them with shl/sra 144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 147 148 // Sparc has no REM operation. 149 setOperationAction(ISD::UREM, MVT::i32, Expand); 150 setOperationAction(ISD::SREM, MVT::i32, Expand); 151 152 // Custom expand fp<->sint 153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 154 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 155 156 // Expand fp<->uint 157 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 158 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 159 160 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 161 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 162 163 // Turn FP extload into load/fextend 164 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 165 166 // Sparc has no select or setcc: expand to SELECT_CC. 167 setOperationAction(ISD::SELECT, MVT::i32, Expand); 168 setOperationAction(ISD::SELECT, MVT::f32, Expand); 169 setOperationAction(ISD::SELECT, MVT::f64, Expand); 170 setOperationAction(ISD::SETCC, MVT::i32, Expand); 171 setOperationAction(ISD::SETCC, MVT::f32, Expand); 172 setOperationAction(ISD::SETCC, MVT::f64, Expand); 173 174 // Sparc doesn't have BRCOND either, it has BR_CC. 175 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 176 setOperationAction(ISD::BRIND, MVT::i32, Expand); 177 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 178 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 179 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 180 181 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 182 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 183 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 184 185 // SPARC has no intrinsics for these particular operations. 186 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 187 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 188 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 189 190 setOperationAction(ISD::FSIN , MVT::f64, Expand); 191 setOperationAction(ISD::FCOS , MVT::f64, Expand); 192 setOperationAction(ISD::FSIN , MVT::f32, Expand); 193 setOperationAction(ISD::FCOS , MVT::f32, Expand); 194 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 195 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 196 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 197 setOperationAction(ISD::ROTL , MVT::i32, Expand); 198 setOperationAction(ISD::ROTR , MVT::i32, Expand); 199 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 200 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 201 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 202 203 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 204 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 205 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 206 207 // We don't have line number support yet. 208 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 209 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 210 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 211 212 // RET must be custom lowered, to meet ABI requirements 213 setOperationAction(ISD::RET , MVT::Other, Custom); 214 215 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 216 setOperationAction(ISD::VASTART , MVT::Other, Custom); 217 // VAARG needs to be lowered to not do unaligned accesses for doubles. 218 setOperationAction(ISD::VAARG , MVT::Other, Custom); 219 220 // Use the default implementation. 221 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 222 setOperationAction(ISD::VAEND , MVT::Other, Expand); 223 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 224 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 225 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 226 227 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 228 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 229 230 setStackPointerRegisterToSaveRestore(SP::O6); 231 232 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 233 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 234 } 235 236 computeRegisterProperties(); 237} 238 239const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 240 switch (Opcode) { 241 default: return 0; 242 case SPISD::CMPICC: return "SPISD::CMPICC"; 243 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 244 case SPISD::BRICC: return "SPISD::BRICC"; 245 case SPISD::BRFCC: return "SPISD::BRFCC"; 246 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 247 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 248 case SPISD::Hi: return "SPISD::Hi"; 249 case SPISD::Lo: return "SPISD::Lo"; 250 case SPISD::FTOI: return "SPISD::FTOI"; 251 case SPISD::ITOF: return "SPISD::ITOF"; 252 case SPISD::CALL: return "SPISD::CALL"; 253 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 254 } 255} 256 257/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 258/// be zero. Op is expected to be a target specific node. Used by DAG 259/// combiner. 260void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 261 uint64_t Mask, 262 uint64_t &KnownZero, 263 uint64_t &KnownOne, 264 unsigned Depth) const { 265 uint64_t KnownZero2, KnownOne2; 266 KnownZero = KnownOne = 0; // Don't know anything. 267 268 switch (Op.getOpcode()) { 269 default: break; 270 case SPISD::SELECT_ICC: 271 case SPISD::SELECT_FCC: 272 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 273 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 274 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 275 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 276 277 // Only known if known in both the LHS and RHS. 278 KnownOne &= KnownOne2; 279 KnownZero &= KnownZero2; 280 break; 281 } 282} 283 284/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 285/// either one or two GPRs, including FP values. TODO: we should pass FP values 286/// in FP registers for fastcc functions. 287std::vector<SDOperand> 288SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 289 MachineFunction &MF = DAG.getMachineFunction(); 290 SSARegMap *RegMap = MF.getSSARegMap(); 291 std::vector<SDOperand> ArgValues; 292 293 static const unsigned ArgRegs[] = { 294 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 295 }; 296 297 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 298 unsigned ArgOffset = 68; 299 300 SDOperand Root = DAG.getRoot(); 301 std::vector<SDOperand> OutChains; 302 303 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 304 MVT::ValueType ObjectVT = getValueType(I->getType()); 305 306 switch (ObjectVT) { 307 default: assert(0 && "Unhandled argument type!"); 308 case MVT::i1: 309 case MVT::i8: 310 case MVT::i16: 311 case MVT::i32: 312 if (I->use_empty()) { // Argument is dead. 313 if (CurArgReg < ArgRegEnd) ++CurArgReg; 314 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 315 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 316 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 317 MF.addLiveIn(*CurArgReg++, VReg); 318 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 319 if (ObjectVT != MVT::i32) { 320 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 321 : ISD::AssertZext; 322 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 323 DAG.getValueType(ObjectVT)); 324 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 325 } 326 ArgValues.push_back(Arg); 327 } else { 328 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 329 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 330 SDOperand Load; 331 if (ObjectVT == MVT::i32) { 332 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 333 } else { 334 unsigned LoadOp = 335 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 336 337 // Sparc is big endian, so add an offset based on the ObjectVT. 338 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 339 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 340 DAG.getConstant(Offset, MVT::i32)); 341 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 342 DAG.getSrcValue(0), ObjectVT); 343 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 344 } 345 ArgValues.push_back(Load); 346 } 347 348 ArgOffset += 4; 349 break; 350 case MVT::f32: 351 if (I->use_empty()) { // Argument is dead. 352 if (CurArgReg < ArgRegEnd) ++CurArgReg; 353 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 354 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 355 // FP value is passed in an integer register. 356 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 357 MF.addLiveIn(*CurArgReg++, VReg); 358 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 359 360 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 361 ArgValues.push_back(Arg); 362 } else { 363 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 364 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 365 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); 366 ArgValues.push_back(Load); 367 } 368 ArgOffset += 4; 369 break; 370 371 case MVT::i64: 372 case MVT::f64: 373 if (I->use_empty()) { // Argument is dead. 374 if (CurArgReg < ArgRegEnd) ++CurArgReg; 375 if (CurArgReg < ArgRegEnd) ++CurArgReg; 376 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 377 } else if (/* FIXME: Apparently this isn't safe?? */ 378 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 379 ((CurArgReg-ArgRegs) & 1) == 0) { 380 // If this is a double argument and the whole thing lives on the stack, 381 // and the argument is aligned, load the double straight from the stack. 382 // We can't do a load in cases like void foo([6ints], int,double), 383 // because the double wouldn't be aligned! 384 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 385 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 386 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 387 DAG.getSrcValue(0))); 388 } else { 389 SDOperand HiVal; 390 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 391 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 392 MF.addLiveIn(*CurArgReg++, VRegHi); 393 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 394 } else { 395 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 396 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 397 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 398 } 399 400 SDOperand LoVal; 401 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 402 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 403 MF.addLiveIn(*CurArgReg++, VRegLo); 404 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 405 } else { 406 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 407 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 408 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 409 } 410 411 // Compose the two halves together into an i64 unit. 412 SDOperand WholeValue = 413 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 414 415 // If we want a double, do a bit convert. 416 if (ObjectVT == MVT::f64) 417 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 418 419 ArgValues.push_back(WholeValue); 420 } 421 ArgOffset += 8; 422 break; 423 } 424 } 425 426 // Store remaining ArgRegs to the stack if this is a varargs function. 427 if (F.getFunctionType()->isVarArg()) { 428 // Remember the vararg offset for the va_start implementation. 429 VarArgsFrameOffset = ArgOffset; 430 431 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 432 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 433 MF.addLiveIn(*CurArgReg, VReg); 434 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 435 436 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 437 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 438 439 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 440 Arg, FIPtr, DAG.getSrcValue(0))); 441 ArgOffset += 4; 442 } 443 } 444 445 if (!OutChains.empty()) 446 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 447 448 // Finally, inform the code generator which regs we return values in. 449 switch (getValueType(F.getReturnType())) { 450 default: assert(0 && "Unknown type!"); 451 case MVT::isVoid: break; 452 case MVT::i1: 453 case MVT::i8: 454 case MVT::i16: 455 case MVT::i32: 456 MF.addLiveOut(SP::I0); 457 break; 458 case MVT::i64: 459 MF.addLiveOut(SP::I0); 460 MF.addLiveOut(SP::I1); 461 break; 462 case MVT::f32: 463 MF.addLiveOut(SP::F0); 464 break; 465 case MVT::f64: 466 MF.addLiveOut(SP::D0); 467 break; 468 } 469 470 return ArgValues; 471} 472 473std::pair<SDOperand, SDOperand> 474SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 475 bool isVarArg, unsigned CC, 476 bool isTailCall, SDOperand Callee, 477 ArgListTy &Args, SelectionDAG &DAG) { 478 // Count the size of the outgoing arguments. 479 unsigned ArgsSize = 0; 480 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 481 switch (getValueType(Args[i].second)) { 482 default: assert(0 && "Unknown value type!"); 483 case MVT::i1: 484 case MVT::i8: 485 case MVT::i16: 486 case MVT::i32: 487 case MVT::f32: 488 ArgsSize += 4; 489 break; 490 case MVT::i64: 491 case MVT::f64: 492 ArgsSize += 8; 493 break; 494 } 495 } 496 if (ArgsSize > 4*6) 497 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 498 else 499 ArgsSize = 0; 500 501 // Keep stack frames 8-byte aligned. 502 ArgsSize = (ArgsSize+7) & ~7; 503 504 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 505 506 SDOperand StackPtr, NullSV; 507 std::vector<SDOperand> Stores; 508 std::vector<SDOperand> RegValuesToPass; 509 unsigned ArgOffset = 68; 510 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 511 SDOperand Val = Args[i].first; 512 MVT::ValueType ObjectVT = Val.getValueType(); 513 SDOperand ValToStore(0, 0); 514 unsigned ObjSize; 515 switch (ObjectVT) { 516 default: assert(0 && "Unhandled argument type!"); 517 case MVT::i1: 518 case MVT::i8: 519 case MVT::i16: 520 // Promote the integer to 32-bits. If the input type is signed, use a 521 // sign extend, otherwise use a zero extend. 522 if (Args[i].second->isSigned()) 523 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 524 else 525 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 526 // FALL THROUGH 527 case MVT::i32: 528 ObjSize = 4; 529 530 if (RegValuesToPass.size() >= 6) { 531 ValToStore = Val; 532 } else { 533 RegValuesToPass.push_back(Val); 534 } 535 break; 536 case MVT::f32: 537 ObjSize = 4; 538 if (RegValuesToPass.size() >= 6) { 539 ValToStore = Val; 540 } else { 541 // Convert this to a FP value in an int reg. 542 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 543 RegValuesToPass.push_back(Val); 544 } 545 break; 546 case MVT::f64: 547 ObjSize = 8; 548 // If we can store this directly into the outgoing slot, do so. We can 549 // do this when all ArgRegs are used and if the outgoing slot is aligned. 550 // FIXME: McGill/misr fails with this. 551 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 552 ValToStore = Val; 553 break; 554 } 555 556 // Otherwise, convert this to a FP value in int regs. 557 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 558 // FALL THROUGH 559 case MVT::i64: 560 ObjSize = 8; 561 if (RegValuesToPass.size() >= 6) { 562 ValToStore = Val; // Whole thing is passed in memory. 563 break; 564 } 565 566 // Split the value into top and bottom part. Top part goes in a reg. 567 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 568 DAG.getConstant(1, MVT::i32)); 569 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 570 DAG.getConstant(0, MVT::i32)); 571 RegValuesToPass.push_back(Hi); 572 573 if (RegValuesToPass.size() >= 6) { 574 ValToStore = Lo; 575 ArgOffset += 4; 576 ObjSize = 4; 577 } else { 578 RegValuesToPass.push_back(Lo); 579 } 580 break; 581 } 582 583 if (ValToStore.Val) { 584 if (!StackPtr.Val) { 585 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 586 NullSV = DAG.getSrcValue(NULL); 587 } 588 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 589 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 590 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 591 ValToStore, PtrOff, NullSV)); 592 } 593 ArgOffset += ObjSize; 594 } 595 596 // Emit all stores, make sure the occur before any copies into physregs. 597 if (!Stores.empty()) 598 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 599 600 static const unsigned ArgRegs[] = { 601 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 602 }; 603 604 // Build a sequence of copy-to-reg nodes chained together with token chain 605 // and flag operands which copy the outgoing args into O[0-5]. 606 SDOperand InFlag; 607 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 608 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 609 InFlag = Chain.getValue(1); 610 } 611 612 // If the callee is a GlobalAddress node (quite common, every direct call is) 613 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 614 // Likewise ExternalSymbol -> TargetExternalSymbol. 615 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 616 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 617 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 618 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 619 620 std::vector<MVT::ValueType> NodeTys; 621 NodeTys.push_back(MVT::Other); // Returns a chain 622 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 623 std::vector<SDOperand> Ops; 624 Ops.push_back(Chain); 625 Ops.push_back(Callee); 626 if (InFlag.Val) 627 Ops.push_back(InFlag); 628 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops); 629 InFlag = Chain.getValue(1); 630 631 MVT::ValueType RetTyVT = getValueType(RetTy); 632 SDOperand RetVal; 633 if (RetTyVT != MVT::isVoid) { 634 switch (RetTyVT) { 635 default: assert(0 && "Unknown value type to return!"); 636 case MVT::i1: 637 case MVT::i8: 638 case MVT::i16: 639 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 640 Chain = RetVal.getValue(1); 641 642 // Add a note to keep track of whether it is sign or zero extended. 643 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 644 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 645 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 646 break; 647 case MVT::i32: 648 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 649 Chain = RetVal.getValue(1); 650 break; 651 case MVT::f32: 652 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 653 Chain = RetVal.getValue(1); 654 break; 655 case MVT::f64: 656 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 657 Chain = RetVal.getValue(1); 658 break; 659 case MVT::i64: 660 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 661 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 662 Lo.getValue(2)); 663 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 664 Chain = Hi.getValue(1); 665 break; 666 } 667 } 668 669 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 670 DAG.getConstant(ArgsSize, getPointerTy())); 671 672 return std::make_pair(RetVal, Chain); 673} 674 675// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 676// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 677static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 678 ISD::CondCode CC, unsigned &SPCC) { 679 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 680 CC == ISD::SETNE && 681 ((LHS.getOpcode() == SPISD::SELECT_ICC && 682 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 683 (LHS.getOpcode() == SPISD::SELECT_FCC && 684 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 685 isa<ConstantSDNode>(LHS.getOperand(0)) && 686 isa<ConstantSDNode>(LHS.getOperand(1)) && 687 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 688 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 689 SDOperand CMPCC = LHS.getOperand(3); 690 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 691 LHS = CMPCC.getOperand(0); 692 RHS = CMPCC.getOperand(1); 693 } 694} 695 696 697SDOperand SparcTargetLowering:: 698LowerOperation(SDOperand Op, SelectionDAG &DAG) { 699 switch (Op.getOpcode()) { 700 default: assert(0 && "Should not custom lower this!"); 701 case ISD::GlobalAddress: { 702 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 703 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 704 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 705 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 706 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 707 } 708 case ISD::ConstantPool: { 709 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 710 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 711 cast<ConstantPoolSDNode>(Op)->getAlignment()); 712 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 713 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 714 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 715 } 716 case ISD::FP_TO_SINT: 717 // Convert the fp value to integer in an FP register. 718 assert(Op.getValueType() == MVT::i32); 719 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 720 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 721 case ISD::SINT_TO_FP: { 722 assert(Op.getOperand(0).getValueType() == MVT::i32); 723 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 724 // Convert the int value to FP in an FP register. 725 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 726 } 727 case ISD::BR_CC: { 728 SDOperand Chain = Op.getOperand(0); 729 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 730 SDOperand LHS = Op.getOperand(2); 731 SDOperand RHS = Op.getOperand(3); 732 SDOperand Dest = Op.getOperand(4); 733 unsigned Opc, SPCC = ~0U; 734 735 // If this is a br_cc of a "setcc", and if the setcc got lowered into 736 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 737 LookThroughSetCC(LHS, RHS, CC, SPCC); 738 739 // Get the condition flag. 740 SDOperand CompareFlag; 741 if (LHS.getValueType() == MVT::i32) { 742 std::vector<MVT::ValueType> VTs; 743 VTs.push_back(MVT::i32); 744 VTs.push_back(MVT::Flag); 745 std::vector<SDOperand> Ops; 746 Ops.push_back(LHS); 747 Ops.push_back(RHS); 748 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1); 749 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 750 Opc = SPISD::BRICC; 751 } else { 752 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 753 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 754 Opc = SPISD::BRFCC; 755 } 756 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 757 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 758 } 759 case ISD::SELECT_CC: { 760 SDOperand LHS = Op.getOperand(0); 761 SDOperand RHS = Op.getOperand(1); 762 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 763 SDOperand TrueVal = Op.getOperand(2); 764 SDOperand FalseVal = Op.getOperand(3); 765 unsigned Opc, SPCC = ~0U; 766 767 // If this is a select_cc of a "setcc", and if the setcc got lowered into 768 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 769 LookThroughSetCC(LHS, RHS, CC, SPCC); 770 771 SDOperand CompareFlag; 772 if (LHS.getValueType() == MVT::i32) { 773 std::vector<MVT::ValueType> VTs; 774 VTs.push_back(LHS.getValueType()); // subcc returns a value 775 VTs.push_back(MVT::Flag); 776 std::vector<SDOperand> Ops; 777 Ops.push_back(LHS); 778 Ops.push_back(RHS); 779 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1); 780 Opc = SPISD::SELECT_ICC; 781 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 782 } else { 783 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 784 Opc = SPISD::SELECT_FCC; 785 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 786 } 787 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 788 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 789 } 790 case ISD::VASTART: { 791 // vastart just stores the address of the VarArgsFrameIndex slot into the 792 // memory location argument. 793 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 794 DAG.getRegister(SP::I6, MVT::i32), 795 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 796 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 797 Op.getOperand(1), Op.getOperand(2)); 798 } 799 case ISD::VAARG: { 800 SDNode *Node = Op.Val; 801 MVT::ValueType VT = Node->getValueType(0); 802 SDOperand InChain = Node->getOperand(0); 803 SDOperand VAListPtr = Node->getOperand(1); 804 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 805 Node->getOperand(2)); 806 // Increment the pointer, VAList, to the next vaarg 807 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 808 DAG.getConstant(MVT::getSizeInBits(VT)/8, 809 getPointerTy())); 810 // Store the incremented VAList to the legalized pointer 811 InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr, 812 VAListPtr, Node->getOperand(2)); 813 // Load the actual argument out of the pointer VAList, unless this is an 814 // f64 load. 815 if (VT != MVT::f64) { 816 return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0)); 817 } else { 818 // Otherwise, load it as i64, then do a bitconvert. 819 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0)); 820 std::vector<MVT::ValueType> Tys; 821 Tys.push_back(MVT::f64); 822 Tys.push_back(MVT::Other); 823 std::vector<SDOperand> Ops; 824 // Bit-Convert the value to f64. 825 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V)); 826 Ops.push_back(V.getValue(1)); 827 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 828 } 829 } 830 case ISD::DYNAMIC_STACKALLOC: { 831 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 832 SDOperand Size = Op.getOperand(1); // Legalize the size. 833 834 unsigned SPReg = SP::O6; 835 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 836 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 837 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 838 839 // The resultant pointer is actually 16 words from the bottom of the stack, 840 // to provide a register spill area. 841 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 842 DAG.getConstant(96, MVT::i32)); 843 std::vector<MVT::ValueType> Tys; 844 Tys.push_back(MVT::i32); 845 Tys.push_back(MVT::Other); 846 std::vector<SDOperand> Ops; 847 Ops.push_back(NewVal); 848 Ops.push_back(Chain); 849 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 850 } 851 case ISD::RET: { 852 SDOperand Copy; 853 854 switch(Op.getNumOperands()) { 855 default: 856 assert(0 && "Do not know how to return this many arguments!"); 857 abort(); 858 case 1: 859 return SDOperand(); // ret void is legal 860 case 3: { 861 unsigned ArgReg; 862 switch(Op.getOperand(1).getValueType()) { 863 default: assert(0 && "Unknown type to return!"); 864 case MVT::i32: ArgReg = SP::I0; break; 865 case MVT::f32: ArgReg = SP::F0; break; 866 case MVT::f64: ArgReg = SP::D0; break; 867 } 868 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 869 SDOperand()); 870 break; 871 } 872 case 5: 873 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 874 SDOperand()); 875 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 876 break; 877 } 878 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 879 } 880 } 881} 882 883MachineBasicBlock * 884SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 885 MachineBasicBlock *BB) { 886 unsigned BROpcode; 887 unsigned CC; 888 // Figure out the conditional branch opcode to use for this select_cc. 889 switch (MI->getOpcode()) { 890 default: assert(0 && "Unknown SELECT_CC!"); 891 case SP::SELECT_CC_Int_ICC: 892 case SP::SELECT_CC_FP_ICC: 893 case SP::SELECT_CC_DFP_ICC: 894 BROpcode = SP::BCOND; 895 break; 896 case SP::SELECT_CC_Int_FCC: 897 case SP::SELECT_CC_FP_FCC: 898 case SP::SELECT_CC_DFP_FCC: 899 BROpcode = SP::FBCOND; 900 break; 901 } 902 903 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 904 905 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 906 // control-flow pattern. The incoming instruction knows the destination vreg 907 // to set, the condition code register to branch on, the true/false values to 908 // select between, and a branch opcode to use. 909 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 910 ilist<MachineBasicBlock>::iterator It = BB; 911 ++It; 912 913 // thisMBB: 914 // ... 915 // TrueVal = ... 916 // [f]bCC copy1MBB 917 // fallthrough --> copy0MBB 918 MachineBasicBlock *thisMBB = BB; 919 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 920 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 921 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC); 922 MachineFunction *F = BB->getParent(); 923 F->getBasicBlockList().insert(It, copy0MBB); 924 F->getBasicBlockList().insert(It, sinkMBB); 925 // Update machine-CFG edges by first adding all successors of the current 926 // block to the new block which will contain the Phi node for the select. 927 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 928 e = BB->succ_end(); i != e; ++i) 929 sinkMBB->addSuccessor(*i); 930 // Next, remove all successors of the current block, and add the true 931 // and fallthrough blocks as its successors. 932 while(!BB->succ_empty()) 933 BB->removeSuccessor(BB->succ_begin()); 934 BB->addSuccessor(copy0MBB); 935 BB->addSuccessor(sinkMBB); 936 937 // copy0MBB: 938 // %FalseValue = ... 939 // # fallthrough to sinkMBB 940 BB = copy0MBB; 941 942 // Update machine-CFG edges 943 BB->addSuccessor(sinkMBB); 944 945 // sinkMBB: 946 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 947 // ... 948 BB = sinkMBB; 949 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg()) 950 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 951 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 952 953 delete MI; // The pseudo instruction is gone now. 954 return BB; 955} 956 957//===----------------------------------------------------------------------===// 958// Instruction Selector Implementation 959//===----------------------------------------------------------------------===// 960 961//===--------------------------------------------------------------------===// 962/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 963/// instructions for SelectionDAG operations. 964/// 965namespace { 966class SparcDAGToDAGISel : public SelectionDAGISel { 967 SparcTargetLowering Lowering; 968 969 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 970 /// make the right decision when generating code for different targets. 971 const SparcSubtarget &Subtarget; 972public: 973 SparcDAGToDAGISel(TargetMachine &TM) 974 : SelectionDAGISel(Lowering), Lowering(TM), 975 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 976 } 977 978 void Select(SDOperand &Result, SDOperand Op); 979 980 // Complex Pattern Selectors. 981 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 982 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 983 984 /// InstructionSelectBasicBlock - This callback is invoked by 985 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 986 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 987 988 virtual const char *getPassName() const { 989 return "SPARC DAG->DAG Pattern Instruction Selection"; 990 } 991 992 // Include the pieces autogenerated from the target description. 993#include "SparcGenDAGISel.inc" 994}; 995} // end anonymous namespace 996 997/// InstructionSelectBasicBlock - This callback is invoked by 998/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 999void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 1000 DEBUG(BB->dump()); 1001 1002 // Select target instructions for the DAG. 1003 DAG.setRoot(SelectRoot(DAG.getRoot())); 1004 assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!"); 1005 CodeGenMap.clear(); 1006 HandleMap.clear(); 1007 ReplaceMap.clear(); 1008 DAG.RemoveDeadNodes(); 1009 1010 // Emit machine code to BB. 1011 ScheduleAndEmitDAG(DAG); 1012} 1013 1014bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 1015 SDOperand &Offset) { 1016 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1017 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1018 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1019 return true; 1020 } 1021 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1022 Addr.getOpcode() == ISD::TargetGlobalAddress) 1023 return false; // direct calls. 1024 1025 if (Addr.getOpcode() == ISD::ADD) { 1026 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1027 if (Predicate_simm13(CN)) { 1028 if (FrameIndexSDNode *FIN = 1029 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1030 // Constant offset from frame ref. 1031 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1032 } else { 1033 Base = Addr.getOperand(0); 1034 } 1035 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1036 return true; 1037 } 1038 } 1039 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1040 Base = Addr.getOperand(1); 1041 Offset = Addr.getOperand(0).getOperand(0); 1042 return true; 1043 } 1044 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1045 Base = Addr.getOperand(0); 1046 Offset = Addr.getOperand(1).getOperand(0); 1047 return true; 1048 } 1049 } 1050 Base = Addr; 1051 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1052 return true; 1053} 1054 1055bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 1056 SDOperand &R2) { 1057 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1058 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1059 Addr.getOpcode() == ISD::TargetGlobalAddress) 1060 return false; // direct calls. 1061 1062 if (Addr.getOpcode() == ISD::ADD) { 1063 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1064 Predicate_simm13(Addr.getOperand(1).Val)) 1065 return false; // Let the reg+imm pattern catch this! 1066 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1067 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1068 return false; // Let the reg+imm pattern catch this! 1069 R1 = Addr.getOperand(0); 1070 R2 = Addr.getOperand(1); 1071 return true; 1072 } 1073 1074 R1 = Addr; 1075 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1076 return true; 1077} 1078 1079void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { 1080 SDNode *N = Op.Val; 1081 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1082 N->getOpcode() < SPISD::FIRST_NUMBER) { 1083 Result = Op; 1084 return; // Already selected. 1085 } 1086 1087 // If this has already been converted, use it. 1088 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 1089 if (CGMI != CodeGenMap.end()) { 1090 Result = CGMI->second; 1091 return; 1092 } 1093 1094 switch (N->getOpcode()) { 1095 default: break; 1096 case ISD::SDIV: 1097 case ISD::UDIV: { 1098 // FIXME: should use a custom expander to expose the SRA to the dag. 1099 SDOperand DivLHS, DivRHS; 1100 Select(DivLHS, N->getOperand(0)); 1101 Select(DivRHS, N->getOperand(1)); 1102 1103 // Set the Y register to the high-part. 1104 SDOperand TopPart; 1105 if (N->getOpcode() == ISD::SDIV) { 1106 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1107 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1108 } else { 1109 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1110 } 1111 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1112 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1113 1114 // FIXME: Handle div by immediate. 1115 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1116 Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 1117 return; 1118 } 1119 case ISD::MULHU: 1120 case ISD::MULHS: { 1121 // FIXME: Handle mul by immediate. 1122 SDOperand MulLHS, MulRHS; 1123 Select(MulLHS, N->getOperand(0)); 1124 Select(MulRHS, N->getOperand(1)); 1125 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1126 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1127 MulLHS, MulRHS); 1128 // The high part is in the Y register. 1129 Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1130 return; 1131 } 1132 } 1133 1134 SelectCode(Result, Op); 1135} 1136 1137 1138/// createSparcISelDag - This pass converts a legalized DAG into a 1139/// SPARC-specific DAG, ready for instruction scheduling. 1140/// 1141FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1142 return new SparcDAGToDAGISel(TM); 1143} 1144