SparcISelDAGToDAG.cpp revision abf6d1784b2d4bbcb7d20ab64881f77d755059f6
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 112 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 113 114 // Turn FP extload into load/fextend 115 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 116 117 // Sparc has no select or setcc: expand to SELECT_CC. 118 setOperationAction(ISD::SELECT, MVT::i32, Expand); 119 setOperationAction(ISD::SELECT, MVT::f32, Expand); 120 setOperationAction(ISD::SELECT, MVT::f64, Expand); 121 setOperationAction(ISD::SETCC, MVT::i32, Expand); 122 setOperationAction(ISD::SETCC, MVT::f32, Expand); 123 setOperationAction(ISD::SETCC, MVT::f64, Expand); 124 125 // Sparc doesn't have BRCOND either, it has BR_CC. 126 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 127 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 128 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 129 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 130 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 131 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 132 133 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 134 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 135 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 136 137 // V8 has no intrinsics for these particular operations. 138 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 139 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 140 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 141 142 setOperationAction(ISD::FSIN , MVT::f64, Expand); 143 setOperationAction(ISD::FCOS , MVT::f64, Expand); 144 setOperationAction(ISD::FSIN , MVT::f32, Expand); 145 setOperationAction(ISD::FCOS , MVT::f32, Expand); 146 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 147 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 148 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 149 150 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 151 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 152 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 153 154 // We don't have line number support yet. 155 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 156 157 computeRegisterProperties(); 158} 159 160/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 161/// either one or two GPRs, including FP values. TODO: we should pass FP values 162/// in FP registers for fastcc functions. 163std::vector<SDOperand> 164SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 165 MachineFunction &MF = DAG.getMachineFunction(); 166 SSARegMap *RegMap = MF.getSSARegMap(); 167 std::vector<SDOperand> ArgValues; 168 169 static const unsigned ArgRegs[] = { 170 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 171 }; 172 173 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 174 unsigned ArgOffset = 68; 175 176 SDOperand Root = DAG.getRoot(); 177 std::vector<SDOperand> OutChains; 178 179 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 180 MVT::ValueType ObjectVT = getValueType(I->getType()); 181 182 switch (ObjectVT) { 183 default: assert(0 && "Unhandled argument type!"); 184 case MVT::i1: 185 case MVT::i8: 186 case MVT::i16: 187 case MVT::i32: 188 if (I->use_empty()) { // Argument is dead. 189 if (CurArgReg < ArgRegEnd) ++CurArgReg; 190 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 191 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 192 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 193 MF.addLiveIn(*CurArgReg++, VReg); 194 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 195 if (ObjectVT != MVT::i32) { 196 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 197 : ISD::AssertZext; 198 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 199 DAG.getValueType(ObjectVT)); 200 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 201 } 202 ArgValues.push_back(Arg); 203 } else { 204 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 205 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 206 SDOperand Load; 207 if (ObjectVT == MVT::i32) { 208 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 209 } else { 210 unsigned LoadOp = 211 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 212 213 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 214 DAG.getSrcValue(0), ObjectVT); 215 } 216 ArgValues.push_back(Load); 217 } 218 219 ArgOffset += 4; 220 break; 221 case MVT::f32: 222 if (I->use_empty()) { // Argument is dead. 223 if (CurArgReg < ArgRegEnd) ++CurArgReg; 224 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 225 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 226 // FP value is passed in an integer register. 227 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 228 MF.addLiveIn(*CurArgReg++, VReg); 229 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 230 231 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 232 ArgValues.push_back(Arg); 233 } 234 ArgOffset += 4; 235 break; 236 237 case MVT::i64: 238 case MVT::f64: 239 if (I->use_empty()) { // Argument is dead. 240 if (CurArgReg < ArgRegEnd) ++CurArgReg; 241 if (CurArgReg < ArgRegEnd) ++CurArgReg; 242 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 243 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 244 ((CurArgReg-ArgRegs) & 1) == 0) { 245 // If this is a double argument and the whole thing lives on the stack, 246 // and the argument is aligned, load the double straight from the stack. 247 // We can't do a load in cases like void foo([6ints], int,double), 248 // because the double wouldn't be aligned! 249 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 250 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 251 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 252 DAG.getSrcValue(0))); 253 } else { 254 SDOperand HiVal; 255 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 256 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 257 MF.addLiveIn(*CurArgReg++, VRegHi); 258 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 259 } else { 260 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 261 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 262 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 263 } 264 265 SDOperand LoVal; 266 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 267 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 268 MF.addLiveIn(*CurArgReg++, VRegLo); 269 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 270 } else { 271 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 272 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 273 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 274 } 275 276 // Compose the two halves together into an i64 unit. 277 SDOperand WholeValue = 278 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 279 280 // If we want a double, do a bit convert. 281 if (ObjectVT == MVT::f64) 282 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 283 284 ArgValues.push_back(WholeValue); 285 } 286 ArgOffset += 8; 287 break; 288 } 289 } 290 291 // Store remaining ArgRegs to the stack if this is a varargs function. 292 if (F.getFunctionType()->isVarArg()) { 293 // Remember the vararg offset for the va_start implementation. 294 VarArgsFrameOffset = ArgOffset; 295 296 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 297 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 298 MF.addLiveIn(*CurArgReg, VReg); 299 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 300 301 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 302 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 303 304 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 305 Arg, FIPtr, DAG.getSrcValue(0))); 306 ArgOffset += 4; 307 } 308 } 309 310 if (!OutChains.empty()) 311 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 312 313 // Finally, inform the code generator which regs we return values in. 314 switch (getValueType(F.getReturnType())) { 315 default: assert(0 && "Unknown type!"); 316 case MVT::isVoid: break; 317 case MVT::i1: 318 case MVT::i8: 319 case MVT::i16: 320 case MVT::i32: 321 MF.addLiveOut(V8::I0); 322 break; 323 case MVT::i64: 324 MF.addLiveOut(V8::I0); 325 MF.addLiveOut(V8::I1); 326 break; 327 case MVT::f32: 328 MF.addLiveOut(V8::F0); 329 break; 330 case MVT::f64: 331 MF.addLiveOut(V8::D0); 332 break; 333 } 334 335 return ArgValues; 336} 337 338std::pair<SDOperand, SDOperand> 339SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 340 bool isVarArg, unsigned CC, 341 bool isTailCall, SDOperand Callee, 342 ArgListTy &Args, SelectionDAG &DAG) { 343 MachineFunction &MF = DAG.getMachineFunction(); 344 // Count the size of the outgoing arguments. 345 unsigned ArgsSize = 0; 346 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 347 switch (getValueType(Args[i].second)) { 348 default: assert(0 && "Unknown value type!"); 349 case MVT::i1: 350 case MVT::i8: 351 case MVT::i16: 352 case MVT::i32: 353 case MVT::f32: 354 ArgsSize += 4; 355 break; 356 case MVT::i64: 357 case MVT::f64: 358 ArgsSize += 8; 359 break; 360 } 361 } 362 if (ArgsSize > 4*6) 363 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 364 else 365 ArgsSize = 0; 366 367 // Keep stack frames 8-byte aligned. 368 ArgsSize = (ArgsSize+7) & ~7; 369 370 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 371 DAG.getConstant(ArgsSize, getPointerTy())); 372 373 SDOperand StackPtr, NullSV; 374 std::vector<SDOperand> Stores; 375 std::vector<SDOperand> RegValuesToPass; 376 unsigned ArgOffset = 68; 377 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 378 SDOperand Val = Args[i].first; 379 MVT::ValueType ObjectVT = Val.getValueType(); 380 SDOperand ValToStore; 381 unsigned ObjSize; 382 switch (ObjectVT) { 383 default: assert(0 && "Unhandled argument type!"); 384 case MVT::i1: 385 case MVT::i8: 386 case MVT::i16: 387 // Promote the integer to 32-bits. If the input type is signed, use a 388 // sign extend, otherwise use a zero extend. 389 if (Args[i].second->isSigned()) 390 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 391 else 392 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 393 // FALL THROUGH 394 case MVT::i32: 395 ObjSize = 4; 396 397 if (RegValuesToPass.size() >= 6) { 398 ValToStore = Val; 399 } else { 400 RegValuesToPass.push_back(Val); 401 } 402 break; 403 case MVT::f32: 404 ObjSize = 4; 405 if (RegValuesToPass.size() >= 6) { 406 ValToStore = Val; 407 } else { 408 // Convert this to a FP value in an int reg. 409 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 410 RegValuesToPass.push_back(Val); 411 } 412 break; 413 case MVT::f64: 414 ObjSize = 8; 415 // If we can store this directly into the outgoing slot, do so. We can 416 // do this when all ArgRegs are used and if the outgoing slot is aligned. 417 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 418 ValToStore = Val; 419 break; 420 } 421 422 // Otherwise, convert this to a FP value in int regs. 423 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 424 // FALL THROUGH 425 case MVT::i64: 426 ObjSize = 8; 427 if (RegValuesToPass.size() >= 6) { 428 ValToStore = Val; // Whole thing is passed in memory. 429 break; 430 } 431 432 // Split the value into top and bottom part. Top part goes in a reg. 433 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 434 DAG.getConstant(1, MVT::i32)); 435 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 436 DAG.getConstant(0, MVT::i32)); 437 RegValuesToPass.push_back(Hi); 438 439 if (RegValuesToPass.size() >= 6) { 440 ValToStore = Lo; 441 ArgOffset += 4; 442 ObjSize = 4; 443 } else { 444 RegValuesToPass.push_back(Lo); 445 } 446 break; 447 } 448 449 if (ValToStore.Val) { 450 if (!StackPtr.Val) { 451 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 452 NullSV = DAG.getSrcValue(NULL); 453 } 454 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 455 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 456 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 457 ValToStore, PtrOff, NullSV)); 458 } 459 ArgOffset += ObjSize; 460 } 461 462 // Emit all stores, make sure the occur before any copies into physregs. 463 if (!Stores.empty()) 464 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 465 466 static const unsigned ArgRegs[] = { 467 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 468 }; 469 470 // Build a sequence of copy-to-reg nodes chained together with token chain 471 // and flag operands which copy the outgoing args into O[0-5]. 472 SDOperand InFlag; 473 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 474 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 475 InFlag = Chain.getValue(1); 476 } 477 478 // If the callee is a GlobalAddress node (quite common, every direct call is) 479 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 480 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 481 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 482 483 std::vector<MVT::ValueType> NodeTys; 484 NodeTys.push_back(MVT::Other); // Returns a chain 485 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 486 if (InFlag.Val) 487 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 488 else 489 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 490 InFlag = Chain.getValue(1); 491 492 MVT::ValueType RetTyVT = getValueType(RetTy); 493 SDOperand RetVal; 494 if (RetTyVT != MVT::isVoid) { 495 switch (RetTyVT) { 496 default: assert(0 && "Unknown value type to return!"); 497 case MVT::i1: 498 case MVT::i8: 499 case MVT::i16: 500 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 501 Chain = RetVal.getValue(1); 502 503 // Add a note to keep track of whether it is sign or zero extended. 504 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 505 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 506 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 507 break; 508 case MVT::i32: 509 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 510 Chain = RetVal.getValue(1); 511 break; 512 case MVT::f32: 513 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 514 Chain = RetVal.getValue(1); 515 break; 516 case MVT::f64: 517 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 518 Chain = RetVal.getValue(1); 519 break; 520 case MVT::i64: 521 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 522 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 523 Lo.getValue(2)); 524 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 525 Chain = Hi.getValue(1); 526 break; 527 } 528 } 529 530 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 531 DAG.getConstant(ArgsSize, getPointerTy())); 532 533 return std::make_pair(RetVal, Chain); 534} 535 536SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 537 SelectionDAG &DAG) { 538 SDOperand Copy; 539 switch (Op.getValueType()) { 540 default: assert(0 && "Unknown type to return!"); 541 case MVT::i32: 542 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 543 break; 544 case MVT::f32: 545 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 546 break; 547 case MVT::f64: 548 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 549 break; 550 case MVT::i64: 551 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 552 DAG.getConstant(1, MVT::i32)); 553 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 554 DAG.getConstant(0, MVT::i32)); 555 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 556 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 557 break; 558 } 559 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 560} 561 562SDOperand SparcV8TargetLowering:: 563LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 564 SelectionDAG &DAG) { 565 566 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 567 DAG.getRegister(V8::I6, MVT::i32), 568 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 569 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset, 570 VAListP, DAG.getSrcValue(VAListV)); 571} 572 573std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 574LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 575 const Type *ArgTy, SelectionDAG &DAG) { 576 // Load the pointer out of the valist. 577 SDOperand Ptr = DAG.getLoad(MVT::i32, Chain, 578 VAListP, DAG.getSrcValue(VAListV)); 579 MVT::ValueType ArgVT = getValueType(ArgTy); 580 SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1), 581 Ptr, DAG.getSrcValue(NULL)); 582 // Increment the pointer. 583 Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr, 584 DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32)); 585 // Store it back to the valist. 586 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr, 587 VAListP, DAG.getSrcValue(VAListV)); 588 return std::make_pair(Val, Chain); 589} 590 591std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 592LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 593 SelectionDAG &DAG) { 594 assert(0 && "Unimp"); 595 abort(); 596} 597 598SDOperand SparcV8TargetLowering:: 599LowerOperation(SDOperand Op, SelectionDAG &DAG) { 600 switch (Op.getOpcode()) { 601 default: assert(0 && "Should not custom lower this!"); 602 case ISD::GlobalAddress: { 603 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 604 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 605 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 606 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 607 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 608 } 609 case ISD::ConstantPool: { 610 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 611 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 612 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 613 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 614 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 615 } 616 case ISD::FP_TO_SINT: 617 // Convert the fp value to integer in an FP register. 618 assert(Op.getValueType() == MVT::i32); 619 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 620 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 621 case ISD::SINT_TO_FP: { 622 assert(Op.getOperand(0).getValueType() == MVT::i32); 623 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 624 // Convert the int value to FP in an FP register. 625 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op); 626 } 627 case ISD::BR_CC: { 628 SDOperand Chain = Op.getOperand(0); 629 SDOperand CC = Op.getOperand(1); 630 SDOperand LHS = Op.getOperand(2); 631 SDOperand RHS = Op.getOperand(3); 632 SDOperand Dest = Op.getOperand(4); 633 634 // Get the condition flag. 635 if (LHS.getValueType() == MVT::i32) { 636 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); 637 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 638 } else { 639 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 640 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 641 } 642 } 643 case ISD::SELECT_CC: { 644 SDOperand LHS = Op.getOperand(0); 645 SDOperand RHS = Op.getOperand(1); 646 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 647 SDOperand TrueVal = Op.getOperand(2); 648 SDOperand FalseVal = Op.getOperand(3); 649 650 unsigned Opc; 651 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 652 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); 653 654 Opc = LHS.getValueType() == MVT::i32 ? 655 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 656 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 657 DAG.getConstant(CC, MVT::i32), CompareFlag); 658 } 659 } 660} 661 662MachineBasicBlock * 663SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 664 MachineBasicBlock *BB) { 665 unsigned BROpcode; 666 // Figure out the conditional branch opcode to use for this select_cc. 667 switch (MI->getOpcode()) { 668 default: assert(0 && "Unknown SELECT_CC!"); 669 case V8::SELECT_CC_Int_ICC: 670 case V8::SELECT_CC_FP_ICC: 671 case V8::SELECT_CC_DFP_ICC: 672 // Integer compare. 673 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 674 default: assert(0 && "Unknown integer condition code!"); 675 case ISD::SETEQ: BROpcode = V8::BE; break; 676 case ISD::SETNE: BROpcode = V8::BNE; break; 677 case ISD::SETLT: BROpcode = V8::BL; break; 678 case ISD::SETGT: BROpcode = V8::BG; break; 679 case ISD::SETLE: BROpcode = V8::BLE; break; 680 case ISD::SETGE: BROpcode = V8::BGE; break; 681 case ISD::SETULT: BROpcode = V8::BCS; break; 682 case ISD::SETULE: BROpcode = V8::BLEU; break; 683 case ISD::SETUGT: BROpcode = V8::BGU; break; 684 case ISD::SETUGE: BROpcode = V8::BCC; break; 685 } 686 break; 687 case V8::SELECT_CC_Int_FCC: 688 case V8::SELECT_CC_FP_FCC: 689 case V8::SELECT_CC_DFP_FCC: 690 // FP compare. 691 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 692 default: assert(0 && "Unknown fp condition code!"); 693 case ISD::SETEQ: BROpcode = V8::FBE; break; 694 case ISD::SETNE: BROpcode = V8::FBNE; break; 695 case ISD::SETLT: BROpcode = V8::FBL; break; 696 case ISD::SETGT: BROpcode = V8::FBG; break; 697 case ISD::SETLE: BROpcode = V8::FBLE; break; 698 case ISD::SETGE: BROpcode = V8::FBGE; break; 699 case ISD::SETULT: BROpcode = V8::FBUL; break; 700 case ISD::SETULE: BROpcode = V8::FBULE; break; 701 case ISD::SETUGT: BROpcode = V8::FBUG; break; 702 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 703 case ISD::SETUO: BROpcode = V8::FBU; break; 704 case ISD::SETO: BROpcode = V8::FBO; break; 705 case ISD::SETONE: BROpcode = V8::FBLG; break; 706 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 707 } 708 break; 709 } 710 711 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 712 // control-flow pattern. The incoming instruction knows the destination vreg 713 // to set, the condition code register to branch on, the true/false values to 714 // select between, and a branch opcode to use. 715 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 716 ilist<MachineBasicBlock>::iterator It = BB; 717 ++It; 718 719 // thisMBB: 720 // ... 721 // TrueVal = ... 722 // [f]bCC copy1MBB 723 // fallthrough --> copy0MBB 724 MachineBasicBlock *thisMBB = BB; 725 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 726 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 727 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 728 MachineFunction *F = BB->getParent(); 729 F->getBasicBlockList().insert(It, copy0MBB); 730 F->getBasicBlockList().insert(It, sinkMBB); 731 // Update machine-CFG edges 732 BB->addSuccessor(copy0MBB); 733 BB->addSuccessor(sinkMBB); 734 735 // copy0MBB: 736 // %FalseValue = ... 737 // # fallthrough to sinkMBB 738 BB = copy0MBB; 739 740 // Update machine-CFG edges 741 BB->addSuccessor(sinkMBB); 742 743 // sinkMBB: 744 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 745 // ... 746 BB = sinkMBB; 747 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 748 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 749 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 750 751 delete MI; // The pseudo instruction is gone now. 752 return BB; 753} 754 755//===----------------------------------------------------------------------===// 756// Instruction Selector Implementation 757//===----------------------------------------------------------------------===// 758 759//===--------------------------------------------------------------------===// 760/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 761/// instructions for SelectionDAG operations. 762/// 763namespace { 764class SparcV8DAGToDAGISel : public SelectionDAGISel { 765 SparcV8TargetLowering V8Lowering; 766public: 767 SparcV8DAGToDAGISel(TargetMachine &TM) 768 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 769 770 SDOperand Select(SDOperand Op); 771 772 // Complex Pattern Selectors. 773 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 774 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 775 776 /// InstructionSelectBasicBlock - This callback is invoked by 777 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 778 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 779 780 virtual const char *getPassName() const { 781 return "PowerPC DAG->DAG Pattern Instruction Selection"; 782 } 783 784 // Include the pieces autogenerated from the target description. 785#include "SparcV8GenDAGISel.inc" 786}; 787} // end anonymous namespace 788 789/// InstructionSelectBasicBlock - This callback is invoked by 790/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 791void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 792 DEBUG(BB->dump()); 793 794 // Select target instructions for the DAG. 795 DAG.setRoot(Select(DAG.getRoot())); 796 CodeGenMap.clear(); 797 DAG.RemoveDeadNodes(); 798 799 // Emit machine code to BB. 800 ScheduleAndEmitDAG(DAG); 801} 802 803bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 804 SDOperand &Offset) { 805 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 806 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 807 Offset = CurDAG->getTargetConstant(0, MVT::i32); 808 return true; 809 } 810 811 if (Addr.getOpcode() == ISD::ADD) { 812 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 813 if (Predicate_simm13(CN)) { 814 if (FrameIndexSDNode *FIN = 815 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 816 // Constant offset from frame ref. 817 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 818 } else { 819 Base = Select(Addr.getOperand(0)); 820 } 821 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 822 return true; 823 } 824 } 825 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 826 Base = Select(Addr.getOperand(1)); 827 Offset = Addr.getOperand(0).getOperand(0); 828 return true; 829 } 830 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 831 Base = Select(Addr.getOperand(0)); 832 Offset = Addr.getOperand(1).getOperand(0); 833 return true; 834 } 835 } 836 Base = Select(Addr); 837 Offset = CurDAG->getTargetConstant(0, MVT::i32); 838 return true; 839} 840 841bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 842 SDOperand &R2) { 843 if (Addr.getOpcode() == ISD::FrameIndex) return false; 844 if (Addr.getOpcode() == ISD::ADD) { 845 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 846 Predicate_simm13(Addr.getOperand(1).Val)) 847 return false; // Let the reg+imm pattern catch this! 848 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 849 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 850 return false; // Let the reg+imm pattern catch this! 851 R1 = Select(Addr.getOperand(0)); 852 R2 = Select(Addr.getOperand(1)); 853 return true; 854 } 855 856 R1 = Select(Addr); 857 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 858 return true; 859} 860 861SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 862 SDNode *N = Op.Val; 863 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 864 N->getOpcode() < V8ISD::FIRST_NUMBER) 865 return Op; // Already selected. 866 // If this has already been converted, use it. 867 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 868 if (CGMI != CodeGenMap.end()) return CGMI->second; 869 870 switch (N->getOpcode()) { 871 default: break; 872 case ISD::Register: return Op; 873 case ISD::FrameIndex: { 874 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 875 if (N->hasOneUse()) 876 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 877 CurDAG->getTargetFrameIndex(FI, MVT::i32), 878 CurDAG->getTargetConstant(0, MVT::i32)); 879 return CodeGenMap[Op] = 880 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 881 CurDAG->getTargetFrameIndex(FI, MVT::i32), 882 CurDAG->getTargetConstant(0, MVT::i32)); 883 } 884 case V8ISD::CMPICC: { 885 // FIXME: Handle compare with immediate. 886 SDOperand LHS = Select(N->getOperand(0)); 887 SDOperand RHS = Select(N->getOperand(1)); 888 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 889 LHS, RHS); 890 return CodeGenMap[Op] = Result.getValue(1); 891 } 892 case ISD::ADD_PARTS: { 893 SDOperand LHSL = Select(N->getOperand(0)); 894 SDOperand LHSH = Select(N->getOperand(1)); 895 SDOperand RHSL = Select(N->getOperand(2)); 896 SDOperand RHSH = Select(N->getOperand(3)); 897 // FIXME, handle immediate RHS. 898 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 899 LHSL, RHSL); 900 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 901 Low.getValue(1)); 902 CodeGenMap[SDOperand(N, 0)] = Low; 903 CodeGenMap[SDOperand(N, 1)] = Hi; 904 return Op.ResNo ? Hi : Low; 905 } 906 case ISD::SUB_PARTS: { 907 SDOperand LHSL = Select(N->getOperand(0)); 908 SDOperand LHSH = Select(N->getOperand(1)); 909 SDOperand RHSL = Select(N->getOperand(2)); 910 SDOperand RHSH = Select(N->getOperand(3)); 911 // FIXME, handle immediate RHS. 912 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 913 LHSL, RHSL); 914 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 915 Low.getValue(1)); 916 CodeGenMap[SDOperand(N, 0)] = Low; 917 CodeGenMap[SDOperand(N, 1)] = Hi; 918 return Op.ResNo ? Hi : Low; 919 } 920 case ISD::SDIV: 921 case ISD::UDIV: { 922 // FIXME: should use a custom expander to expose the SRA to the dag. 923 SDOperand DivLHS = Select(N->getOperand(0)); 924 SDOperand DivRHS = Select(N->getOperand(1)); 925 926 // Set the Y register to the high-part. 927 SDOperand TopPart; 928 if (N->getOpcode() == ISD::SDIV) { 929 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 930 CurDAG->getTargetConstant(31, MVT::i32)); 931 } else { 932 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 933 } 934 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 935 CurDAG->getRegister(V8::G0, MVT::i32)); 936 937 // FIXME: Handle div by immediate. 938 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 939 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 940 } 941 case ISD::MULHU: 942 case ISD::MULHS: { 943 // FIXME: Handle mul by immediate. 944 SDOperand MulLHS = Select(N->getOperand(0)); 945 SDOperand MulRHS = Select(N->getOperand(1)); 946 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 947 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 948 MulLHS, MulRHS); 949 // The high part is in the Y register. 950 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 951 } 952 case ISD::CALL: 953 // FIXME: This is a workaround for a bug in tblgen. 954 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 955 // Emits: (CALL:void (tglobaladdr:i32):$dst) 956 // Pattern complexity = 2 cost = 1 957 SDOperand N1 = N->getOperand(1); 958 if (N1.getOpcode() != ISD::TargetGlobalAddress && 959 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 960 SDOperand InFlag = SDOperand(0, 0); 961 SDOperand Chain = N->getOperand(0); 962 SDOperand Tmp0 = N1; 963 Chain = Select(Chain); 964 SDOperand Result; 965 if (N->getNumOperands() == 3) { 966 InFlag = Select(N->getOperand(2)); 967 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 968 Chain, InFlag); 969 } else { 970 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 971 Chain); 972 } 973 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 974 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 975 return Result.getValue(Op.ResNo); 976 } 977 P47Fail:; 978 979 } 980 981 return SelectCode(Op); 982} 983 984 985/// createPPCISelDag - This pass converts a legalized DAG into a 986/// PowerPC-specific DAG, ready for instruction scheduling. 987/// 988FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 989 return new SparcV8DAGToDAGISel(TM); 990} 991