SparcISelDAGToDAG.cpp revision b4d899e21ccb4414f671efd54b3f87dbcd751aae
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 112 113 // Sparc has no select or setcc: expand to SELECT_CC. 114 setOperationAction(ISD::SELECT, MVT::i32, Expand); 115 setOperationAction(ISD::SELECT, MVT::f32, Expand); 116 setOperationAction(ISD::SELECT, MVT::f64, Expand); 117 setOperationAction(ISD::SETCC, MVT::i32, Expand); 118 setOperationAction(ISD::SETCC, MVT::f32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f64, Expand); 120 121 // Sparc doesn't have BRCOND either, it has BR_CC. 122 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 123 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 124 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 125 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 126 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 127 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 128 129 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 130 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 131 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 132 133 computeRegisterProperties(); 134} 135 136/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 137/// either one or two GPRs, including FP values. TODO: we should pass FP values 138/// in FP registers for fastcc functions. 139std::vector<SDOperand> 140SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 141 MachineFunction &MF = DAG.getMachineFunction(); 142 SSARegMap *RegMap = MF.getSSARegMap(); 143 std::vector<SDOperand> ArgValues; 144 145 static const unsigned ArgRegs[] = { 146 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 147 }; 148 149 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 150 unsigned ArgOffset = 68; 151 152 SDOperand Root = DAG.getRoot(); 153 std::vector<SDOperand> OutChains; 154 155 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 156 MVT::ValueType ObjectVT = getValueType(I->getType()); 157 158 switch (ObjectVT) { 159 default: assert(0 && "Unhandled argument type!"); 160 case MVT::i1: 161 case MVT::i8: 162 case MVT::i16: 163 case MVT::i32: 164 if (I->use_empty()) { // Argument is dead. 165 if (CurArgReg < ArgRegEnd) ++CurArgReg; 166 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 167 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 168 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 169 MF.addLiveIn(*CurArgReg++, VReg); 170 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 171 if (ObjectVT != MVT::i32) { 172 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 173 : ISD::AssertZext; 174 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 175 DAG.getValueType(ObjectVT)); 176 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 177 } 178 ArgValues.push_back(Arg); 179 } else { 180 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 181 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 182 SDOperand Load; 183 if (ObjectVT == MVT::i32) { 184 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 185 } else { 186 unsigned LoadOp = 187 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 188 189 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 190 DAG.getSrcValue(0), ObjectVT); 191 } 192 ArgValues.push_back(Load); 193 } 194 195 ArgOffset += 4; 196 break; 197 case MVT::f32: 198 if (I->use_empty()) { // Argument is dead. 199 if (CurArgReg < ArgRegEnd) ++CurArgReg; 200 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 201 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 202 // FP value is passed in an integer register. 203 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 204 MF.addLiveIn(*CurArgReg++, VReg); 205 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 206 207 // We use the stack space that is already reserved for this reg. 208 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 209 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 210 211 SDOperand SV = DAG.getSrcValue(0); 212 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 213 Arg, FIPtr, SV); 214 ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV)); 215 } 216 ArgOffset += 4; 217 break; 218 219 case MVT::i64: 220 case MVT::f64: 221 if (I->use_empty()) { // Argument is dead. 222 if (CurArgReg < ArgRegEnd) ++CurArgReg; 223 if (CurArgReg < ArgRegEnd) ++CurArgReg; 224 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 225 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 226 ((CurArgReg-ArgRegs) & 1) == 0) { 227 // If this is a double argument and the whole thing lives on the stack, 228 // and the argument is aligned, load the double straight from the stack. 229 // We can't do a load in cases like void foo([6ints], int,double), 230 // because the double wouldn't be aligned! 231 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 232 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 233 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 234 DAG.getSrcValue(0))); 235 } else { 236 SDOperand HiVal; 237 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 238 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 239 MF.addLiveIn(*CurArgReg++, VRegHi); 240 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 241 } else { 242 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 243 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 244 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 245 } 246 247 SDOperand LoVal; 248 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 249 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 250 MF.addLiveIn(*CurArgReg++, VRegLo); 251 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 252 } else { 253 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 254 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 255 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 256 } 257 258 // Compose the two halves together into an i64 unit. 259 SDOperand WholeValue = 260 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 261 262 if (ObjectVT == MVT::i64) { 263 // If we are emitting an i64, this is what we want. 264 ArgValues.push_back(WholeValue); 265 } else { 266 assert(ObjectVT == MVT::f64); 267 // Otherwise, emit a store to the stack and reload into FPR. 268 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 269 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 270 SDOperand SV = DAG.getSrcValue(0); 271 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 272 WholeValue, FIPtr, SV); 273 ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV)); 274 } 275 } 276 ArgOffset += 8; 277 break; 278 } 279 } 280 281 // Store remaining ArgRegs to the stack if this is a varargs function. 282 if (F.getFunctionType()->isVarArg()) { 283 // Remember the vararg offset for the va_start implementation. 284 VarArgsFrameOffset = ArgOffset; 285 286 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 287 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 288 MF.addLiveIn(*CurArgReg, VReg); 289 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 290 291 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 292 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 293 294 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 295 Arg, FIPtr, DAG.getSrcValue(0))); 296 ArgOffset += 4; 297 } 298 } 299 300 if (!OutChains.empty()) 301 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 302 303 // Finally, inform the code generator which regs we return values in. 304 switch (getValueType(F.getReturnType())) { 305 default: assert(0 && "Unknown type!"); 306 case MVT::isVoid: break; 307 case MVT::i1: 308 case MVT::i8: 309 case MVT::i16: 310 case MVT::i32: 311 MF.addLiveOut(V8::I0); 312 break; 313 case MVT::i64: 314 MF.addLiveOut(V8::I0); 315 MF.addLiveOut(V8::I1); 316 break; 317 case MVT::f32: 318 MF.addLiveOut(V8::F0); 319 break; 320 case MVT::f64: 321 MF.addLiveOut(V8::D0); 322 break; 323 } 324 325 return ArgValues; 326} 327 328std::pair<SDOperand, SDOperand> 329SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 330 bool isVarArg, unsigned CC, 331 bool isTailCall, SDOperand Callee, 332 ArgListTy &Args, SelectionDAG &DAG) { 333 MachineFunction &MF = DAG.getMachineFunction(); 334 // Count the size of the outgoing arguments. 335 unsigned ArgsSize = 0; 336 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 337 switch (getValueType(Args[i].second)) { 338 default: assert(0 && "Unknown value type!"); 339 case MVT::i1: 340 case MVT::i8: 341 case MVT::i16: 342 case MVT::i32: 343 case MVT::f32: 344 ArgsSize += 4; 345 break; 346 case MVT::i64: 347 case MVT::f64: 348 ArgsSize += 8; 349 break; 350 } 351 } 352 if (ArgsSize > 4*6) 353 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 354 else 355 ArgsSize = 0; 356 357 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 358 DAG.getConstant(ArgsSize, getPointerTy())); 359 360 SDOperand StackPtr, NullSV; 361 std::vector<SDOperand> Stores; 362 std::vector<SDOperand> RegValuesToPass; 363 unsigned ArgOffset = 68; 364 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 365 SDOperand Val = Args[i].first; 366 MVT::ValueType ObjectVT = Val.getValueType(); 367 SDOperand ValToStore; 368 unsigned ObjSize; 369 switch (ObjectVT) { 370 default: assert(0 && "Unhandled argument type!"); 371 case MVT::i1: 372 case MVT::i8: 373 case MVT::i16: 374 // Promote the integer to 32-bits. If the input type is signed, use a 375 // sign extend, otherwise use a zero extend. 376 if (Args[i].second->isSigned()) 377 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 378 else 379 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 380 // FALL THROUGH 381 case MVT::i32: 382 ObjSize = 4; 383 384 if (RegValuesToPass.size() >= 6) { 385 ValToStore = Val; 386 } else { 387 RegValuesToPass.push_back(Val); 388 } 389 break; 390 case MVT::f32: 391 ObjSize = 4; 392 if (RegValuesToPass.size() >= 6) { 393 ValToStore = Val; 394 } else { 395 // Convert this to a FP value in an int reg. 396 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); 397 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 398 SDOperand SV = DAG.getSrcValue(0); 399 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 400 Val, FIPtr, SV); 401 Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV); 402 RegValuesToPass.push_back(Val); 403 } 404 break; 405 case MVT::f64: { 406 ObjSize = 8; 407 // If we can store this directly into the outgoing slot, do so. We can 408 // do this when all ArgRegs are used and if the outgoing slot is aligned. 409 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 410 ValToStore = Val; 411 break; 412 } 413 414 // Otherwise, convert this to a FP value in int regs. 415 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 416 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 417 SDOperand SV = DAG.getSrcValue(0); 418 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 419 Val, FIPtr, SV); 420 Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV); 421 } 422 // FALL THROUGH 423 case MVT::i64: 424 ObjSize = 8; 425 if (RegValuesToPass.size() >= 6) { 426 ValToStore = Val; // Whole thing is passed in memory. 427 break; 428 } 429 430 // Split the value into top and bottom part. Top part goes in a reg. 431 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 432 DAG.getConstant(1, MVT::i32)); 433 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 434 DAG.getConstant(0, MVT::i32)); 435 RegValuesToPass.push_back(Hi); 436 437 if (RegValuesToPass.size() >= 6) { 438 ValToStore = Lo; 439 } else { 440 RegValuesToPass.push_back(Lo); 441 } 442 break; 443 } 444 445 if (ValToStore.Val) { 446 if (!StackPtr.Val) { 447 StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::SP, MVT::i32); 448 NullSV = DAG.getSrcValue(NULL); 449 } 450 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 451 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 452 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 453 ValToStore, PtrOff, NullSV)); 454 } 455 ArgOffset += ObjSize; 456 } 457 458 // Emit all stores, make sure the occur before any copies into physregs. 459 if (!Stores.empty()) 460 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 461 462 static const unsigned ArgRegs[] = { 463 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 464 }; 465 466 // Build a sequence of copy-to-reg nodes chained together with token chain 467 // and flag operands which copy the outgoing args into O[0-5]. 468 SDOperand InFlag; 469 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 470 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 471 InFlag = Chain.getValue(1); 472 } 473 474 std::vector<MVT::ValueType> RetVals; 475 RetVals.push_back(MVT::Other); 476 RetVals.push_back(MVT::Flag); 477 478 // If the callee is a GlobalAddress node (quite common, every direct call is) 479 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 480 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 481 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 482 483 std::vector<MVT::ValueType> NodeTys; 484 NodeTys.push_back(MVT::Other); // Returns a chain 485 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 486 if (InFlag.Val) 487 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 488 else 489 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 490 InFlag = Chain.getValue(1); 491 492 MVT::ValueType RetTyVT = getValueType(RetTy); 493 SDOperand RetVal; 494 if (RetTyVT != MVT::isVoid) { 495 switch (RetTyVT) { 496 default: assert(0 && "Unknown value type to return!"); 497 case MVT::i1: 498 case MVT::i8: 499 case MVT::i16: 500 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 501 Chain = RetVal.getValue(1); 502 503 // Add a note to keep track of whether it is sign or zero extended. 504 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 505 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 506 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 507 break; 508 case MVT::i32: 509 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 510 Chain = RetVal.getValue(1); 511 break; 512 case MVT::f32: 513 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 514 Chain = RetVal.getValue(1); 515 break; 516 case MVT::f64: 517 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 518 Chain = RetVal.getValue(1); 519 break; 520 case MVT::i64: 521 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 522 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 523 Lo.getValue(2)); 524 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 525 Chain = Hi.getValue(1); 526 break; 527 } 528 } 529 530 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 531 DAG.getConstant(ArgsSize, getPointerTy())); 532 533 MVT::ValueType ActualRetTyVT = RetTyVT; 534 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 535 ActualRetTyVT = MVT::i32; // Promote result to i32. 536 537 return std::make_pair(RetVal, Chain); 538} 539 540SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 541 SelectionDAG &DAG) { 542 SDOperand Copy; 543 switch (Op.getValueType()) { 544 default: assert(0 && "Unknown type to return!"); 545 case MVT::i32: 546 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 547 break; 548 case MVT::f32: 549 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 550 break; 551 case MVT::f64: 552 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 553 break; 554 case MVT::i64: 555 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 556 DAG.getConstant(1, MVT::i32)); 557 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 558 DAG.getConstant(0, MVT::i32)); 559 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 560 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 561 break; 562 } 563 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 564} 565 566SDOperand SparcV8TargetLowering:: 567LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 568 SelectionDAG &DAG) { 569 570 assert(0 && "Unimp"); 571 abort(); 572} 573 574std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 575LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 576 const Type *ArgTy, SelectionDAG &DAG) { 577 assert(0 && "Unimp"); 578 abort(); 579} 580 581std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 582LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 583 SelectionDAG &DAG) { 584 assert(0 && "Unimp"); 585 abort(); 586} 587 588SDOperand SparcV8TargetLowering:: 589LowerOperation(SDOperand Op, SelectionDAG &DAG) { 590 switch (Op.getOpcode()) { 591 default: assert(0 && "Should not custom lower this!"); 592 case ISD::GlobalAddress: { 593 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 594 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 595 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 596 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 597 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 598 } 599 case ISD::ConstantPool: { 600 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 601 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 602 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 603 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 604 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 605 } 606 case ISD::FP_TO_SINT: { 607 // Convert the fp value to integer in an FP register. 608 Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(), 609 Op.getOperand(0)); 610 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 611 int FrameIdx = 612 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 613 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 614 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 615 Op, FI, DAG.getSrcValue(0)); 616 return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0)); 617 } 618 case ISD::SINT_TO_FP: { 619 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 620 int FrameIdx = 621 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 622 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 623 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 624 Op.getOperand(0), FI, DAG.getSrcValue(0)); 625 626 Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0)); 627 628 // Convert the int value to FP in an FP register. 629 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op); 630 } 631 case ISD::BR_CC: { 632 SDOperand Chain = Op.getOperand(0); 633 SDOperand CC = Op.getOperand(1); 634 SDOperand LHS = Op.getOperand(2); 635 SDOperand RHS = Op.getOperand(3); 636 SDOperand Dest = Op.getOperand(4); 637 638 // Get the condition flag. 639 if (LHS.getValueType() == MVT::i32) { 640 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); 641 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 642 } else { 643 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 644 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 645 } 646 } 647 case ISD::SELECT_CC: { 648 SDOperand LHS = Op.getOperand(0); 649 SDOperand RHS = Op.getOperand(1); 650 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 651 SDOperand TrueVal = Op.getOperand(2); 652 SDOperand FalseVal = Op.getOperand(3); 653 654 unsigned Opc; 655 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 656 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); 657 658 Opc = LHS.getValueType() == MVT::i32 ? 659 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 660 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 661 DAG.getConstant(CC, MVT::i32), CompareFlag); 662 } 663 } 664} 665 666MachineBasicBlock * 667SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 668 MachineBasicBlock *BB) { 669 unsigned BROpcode; 670 // Figure out the conditional branch opcode to use for this select_cc. 671 switch (MI->getOpcode()) { 672 default: assert(0 && "Unknown SELECT_CC!"); 673 case V8::SELECT_CC_Int_ICC: 674 case V8::SELECT_CC_FP_ICC: 675 case V8::SELECT_CC_DFP_ICC: 676 // Integer compare. 677 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 678 default: assert(0 && "Unknown integer condition code!"); 679 case ISD::SETEQ: BROpcode = V8::BE; break; 680 case ISD::SETNE: BROpcode = V8::BNE; break; 681 case ISD::SETLT: BROpcode = V8::BL; break; 682 case ISD::SETGT: BROpcode = V8::BG; break; 683 case ISD::SETLE: BROpcode = V8::BLE; break; 684 case ISD::SETGE: BROpcode = V8::BGE; break; 685 case ISD::SETULT: BROpcode = V8::BCS; break; 686 case ISD::SETULE: BROpcode = V8::BLEU; break; 687 case ISD::SETUGT: BROpcode = V8::BGU; break; 688 case ISD::SETUGE: BROpcode = V8::BCC; break; 689 } 690 break; 691 case V8::SELECT_CC_Int_FCC: 692 case V8::SELECT_CC_FP_FCC: 693 case V8::SELECT_CC_DFP_FCC: 694 // FP compare. 695 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 696 default: assert(0 && "Unknown fp condition code!"); 697 case ISD::SETEQ: BROpcode = V8::FBE; break; 698 case ISD::SETNE: BROpcode = V8::FBNE; break; 699 case ISD::SETLT: BROpcode = V8::FBL; break; 700 case ISD::SETGT: BROpcode = V8::FBG; break; 701 case ISD::SETLE: BROpcode = V8::FBLE; break; 702 case ISD::SETGE: BROpcode = V8::FBGE; break; 703 case ISD::SETULT: BROpcode = V8::FBUL; break; 704 case ISD::SETULE: BROpcode = V8::FBULE; break; 705 case ISD::SETUGT: BROpcode = V8::FBUG; break; 706 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 707 case ISD::SETUO: BROpcode = V8::FBU; break; 708 case ISD::SETO: BROpcode = V8::FBO; break; 709 case ISD::SETONE: BROpcode = V8::FBLG; break; 710 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 711 } 712 break; 713 } 714 715 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 716 // control-flow pattern. The incoming instruction knows the destination vreg 717 // to set, the condition code register to branch on, the true/false values to 718 // select between, and a branch opcode to use. 719 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 720 ilist<MachineBasicBlock>::iterator It = BB; 721 ++It; 722 723 // thisMBB: 724 // ... 725 // TrueVal = ... 726 // [f]bCC copy1MBB 727 // fallthrough --> copy0MBB 728 MachineBasicBlock *thisMBB = BB; 729 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 730 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 731 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 732 MachineFunction *F = BB->getParent(); 733 F->getBasicBlockList().insert(It, copy0MBB); 734 F->getBasicBlockList().insert(It, sinkMBB); 735 // Update machine-CFG edges 736 BB->addSuccessor(copy0MBB); 737 BB->addSuccessor(sinkMBB); 738 739 // copy0MBB: 740 // %FalseValue = ... 741 // # fallthrough to sinkMBB 742 BB = copy0MBB; 743 744 // Update machine-CFG edges 745 BB->addSuccessor(sinkMBB); 746 747 // sinkMBB: 748 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 749 // ... 750 BB = sinkMBB; 751 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 752 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 753 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 754 755 delete MI; // The pseudo instruction is gone now. 756 return BB; 757} 758 759//===----------------------------------------------------------------------===// 760// Instruction Selector Implementation 761//===----------------------------------------------------------------------===// 762 763//===--------------------------------------------------------------------===// 764/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 765/// instructions for SelectionDAG operations. 766/// 767namespace { 768class SparcV8DAGToDAGISel : public SelectionDAGISel { 769 SparcV8TargetLowering V8Lowering; 770public: 771 SparcV8DAGToDAGISel(TargetMachine &TM) 772 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 773 774 SDOperand Select(SDOperand Op); 775 776 // Complex Pattern Selectors. 777 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 778 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 779 780 /// InstructionSelectBasicBlock - This callback is invoked by 781 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 782 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 783 784 virtual const char *getPassName() const { 785 return "PowerPC DAG->DAG Pattern Instruction Selection"; 786 } 787 788 // Include the pieces autogenerated from the target description. 789#include "SparcV8GenDAGISel.inc" 790}; 791} // end anonymous namespace 792 793/// InstructionSelectBasicBlock - This callback is invoked by 794/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 795void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 796 DEBUG(BB->dump()); 797 798 // Select target instructions for the DAG. 799 DAG.setRoot(Select(DAG.getRoot())); 800 CodeGenMap.clear(); 801 DAG.RemoveDeadNodes(); 802 803 // Emit machine code to BB. 804 ScheduleAndEmitDAG(DAG); 805} 806 807bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 808 SDOperand &Offset) { 809 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 810 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 811 Offset = CurDAG->getTargetConstant(0, MVT::i32); 812 return true; 813 } 814 815 if (Addr.getOpcode() == ISD::ADD) { 816 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 817 if (Predicate_simm13(CN)) { 818 if (FrameIndexSDNode *FIN = 819 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 820 // Constant offset from frame ref. 821 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 822 } else { 823 Base = Select(Addr.getOperand(0)); 824 } 825 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 826 return true; 827 } 828 } 829 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 830 Base = Select(Addr.getOperand(1)); 831 Offset = Addr.getOperand(0).getOperand(0); 832 return true; 833 } 834 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 835 Base = Select(Addr.getOperand(0)); 836 Offset = Addr.getOperand(1).getOperand(0); 837 return true; 838 } 839 } 840 Base = Select(Addr); 841 Offset = CurDAG->getTargetConstant(0, MVT::i32); 842 return true; 843} 844 845bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 846 SDOperand &R2) { 847 if (Addr.getOpcode() == ISD::FrameIndex) return false; 848 if (Addr.getOpcode() == ISD::ADD) { 849 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 850 Predicate_simm13(Addr.getOperand(1).Val)) 851 return false; // Let the reg+imm pattern catch this! 852 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 853 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 854 return false; // Let the reg+imm pattern catch this! 855 R1 = Select(Addr.getOperand(0)); 856 R2 = Select(Addr.getOperand(1)); 857 return true; 858 } 859 860 R1 = Select(Addr); 861 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 862 return true; 863} 864 865SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 866 SDNode *N = Op.Val; 867 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 868 N->getOpcode() < V8ISD::FIRST_NUMBER) 869 return Op; // Already selected. 870 // If this has already been converted, use it. 871 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 872 if (CGMI != CodeGenMap.end()) return CGMI->second; 873 874 switch (N->getOpcode()) { 875 default: break; 876 case ISD::FrameIndex: { 877 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 878 if (N->hasOneUse()) 879 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 880 CurDAG->getTargetFrameIndex(FI, MVT::i32), 881 CurDAG->getTargetConstant(0, MVT::i32)); 882 return CodeGenMap[Op] = 883 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 884 CurDAG->getTargetFrameIndex(FI, MVT::i32), 885 CurDAG->getTargetConstant(0, MVT::i32)); 886 } 887 case V8ISD::CMPICC: { 888 // FIXME: Handle compare with immediate. 889 SDOperand LHS = Select(N->getOperand(0)); 890 SDOperand RHS = Select(N->getOperand(1)); 891 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 892 LHS, RHS); 893 return CodeGenMap[Op] = Result.getValue(1); 894 } 895 case ISD::ADD_PARTS: { 896 SDOperand LHSL = Select(N->getOperand(0)); 897 SDOperand LHSH = Select(N->getOperand(1)); 898 SDOperand RHSL = Select(N->getOperand(2)); 899 SDOperand RHSH = Select(N->getOperand(3)); 900 // FIXME, handle immediate RHS. 901 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 902 LHSL, RHSL); 903 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 904 Low.getValue(1)); 905 CodeGenMap[SDOperand(N, 0)] = Low; 906 CodeGenMap[SDOperand(N, 1)] = Hi; 907 return Op.ResNo ? Hi : Low; 908 } 909 case ISD::SUB_PARTS: { 910 SDOperand LHSL = Select(N->getOperand(0)); 911 SDOperand LHSH = Select(N->getOperand(1)); 912 SDOperand RHSL = Select(N->getOperand(2)); 913 SDOperand RHSH = Select(N->getOperand(3)); 914 // FIXME, handle immediate RHS. 915 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 916 LHSL, RHSL); 917 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 918 Low.getValue(1)); 919 CodeGenMap[SDOperand(N, 0)] = Low; 920 CodeGenMap[SDOperand(N, 1)] = Hi; 921 return Op.ResNo ? Hi : Low; 922 } 923 case ISD::SDIV: 924 case ISD::UDIV: { 925 // FIXME: should use a custom expander to expose the SRA to the dag. 926 SDOperand DivLHS = Select(N->getOperand(0)); 927 SDOperand DivRHS = Select(N->getOperand(1)); 928 929 // Set the Y register to the high-part. 930 SDOperand TopPart; 931 if (N->getOpcode() == ISD::SDIV) { 932 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 933 CurDAG->getTargetConstant(31, MVT::i32)); 934 } else { 935 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 936 } 937 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 938 CurDAG->getRegister(V8::G0, MVT::i32)); 939 940 // FIXME: Handle div by immediate. 941 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 942 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 943 } 944 case ISD::MULHU: 945 case ISD::MULHS: { 946 // FIXME: Handle mul by immediate. 947 SDOperand MulLHS = Select(N->getOperand(0)); 948 SDOperand MulRHS = Select(N->getOperand(1)); 949 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 950 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 951 MulLHS, MulRHS); 952 // The high part is in the Y register. 953 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 954 } 955 case ISD::CALL: 956 // FIXME: This is a workaround for a bug in tblgen. 957 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 958 // Emits: (CALL:void (tglobaladdr:i32):$dst) 959 // Pattern complexity = 2 cost = 1 960 SDOperand N1 = N->getOperand(1); 961 if (N1.getOpcode() != ISD::TargetGlobalAddress) goto P47Fail; 962 SDOperand InFlag = SDOperand(0, 0); 963 SDOperand Chain = N->getOperand(0); 964 SDOperand Tmp0 = N1; 965 Chain = Select(Chain); 966 SDOperand Result; 967 if (N->getNumOperands() == 3) { 968 InFlag = Select(N->getOperand(2)); 969 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 970 Chain, InFlag); 971 } else { 972 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 973 Chain); 974 } 975 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 976 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 977 return Result.getValue(Op.ResNo); 978 } 979 P47Fail:; 980 981 } 982 983 return SelectCode(Op); 984} 985 986 987/// createPPCISelDag - This pass converts a legalized DAG into a 988/// PowerPC-specific DAG, ready for instruction scheduling. 989/// 990FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 991 return new SparcV8DAGToDAGISel(TM); 992} 993