SparcISelDAGToDAG.cpp revision b99329e8a0ec3b5a0004dd649e3546939f5c31e7
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 80 virtual const char *getTargetNodeName(unsigned Opcode) const; 81 }; 82} 83 84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 85 : TargetLowering(TM) { 86 87 // Set up the register classes. 88 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 89 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 90 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 91 92 // Custom legalize GlobalAddress nodes into LO/HI parts. 93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 94 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 95 96 // Sparc doesn't have sext_inreg, replace them with shl/sra 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 100 101 // Sparc has no REM operation. 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i32, Expand); 104 105 // Custom expand fp<->sint 106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 107 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 108 109 // Expand fp<->uint 110 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 111 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 112 113 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 114 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 115 116 // Turn FP extload into load/fextend 117 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 118 119 // Sparc has no select or setcc: expand to SELECT_CC. 120 setOperationAction(ISD::SELECT, MVT::i32, Expand); 121 setOperationAction(ISD::SELECT, MVT::f32, Expand); 122 setOperationAction(ISD::SELECT, MVT::f64, Expand); 123 setOperationAction(ISD::SETCC, MVT::i32, Expand); 124 setOperationAction(ISD::SETCC, MVT::f32, Expand); 125 setOperationAction(ISD::SETCC, MVT::f64, Expand); 126 127 // Sparc doesn't have BRCOND either, it has BR_CC. 128 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 129 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 130 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 131 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 132 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 133 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 134 135 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 138 139 // V8 has no intrinsics for these particular operations. 140 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 141 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 142 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 143 144 setOperationAction(ISD::FSIN , MVT::f64, Expand); 145 setOperationAction(ISD::FCOS , MVT::f64, Expand); 146 setOperationAction(ISD::FSIN , MVT::f32, Expand); 147 setOperationAction(ISD::FCOS , MVT::f32, Expand); 148 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 149 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 150 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 151 setOperationAction(ISD::ROTL , MVT::i32, Expand); 152 setOperationAction(ISD::ROTR , MVT::i32, Expand); 153 154 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 155 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 156 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 157 158 // We don't have line number support yet. 159 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 160 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 161 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 162 163 // Not implemented yet. 164 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 165 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 166 167 computeRegisterProperties(); 168} 169 170const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { 171 switch (Opcode) { 172 default: return 0; 173 case V8ISD::CMPICC: return "V8ISD::CMPICC"; 174 case V8ISD::CMPFCC: return "V8ISD::CMPFCC"; 175 case V8ISD::BRICC: return "V8ISD::BRICC"; 176 case V8ISD::BRFCC: return "V8ISD::BRFCC"; 177 case V8ISD::Hi: return "V8ISD::Hi"; 178 case V8ISD::Lo: return "V8ISD::Lo"; 179 case V8ISD::FTOI: return "V8ISD::FTOI"; 180 case V8ISD::ITOF: return "V8ISD::ITOF"; 181 case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC"; 182 case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC"; 183 case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG"; 184 } 185} 186 187/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 188/// either one or two GPRs, including FP values. TODO: we should pass FP values 189/// in FP registers for fastcc functions. 190std::vector<SDOperand> 191SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 192 MachineFunction &MF = DAG.getMachineFunction(); 193 SSARegMap *RegMap = MF.getSSARegMap(); 194 std::vector<SDOperand> ArgValues; 195 196 static const unsigned ArgRegs[] = { 197 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 198 }; 199 200 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 201 unsigned ArgOffset = 68; 202 203 SDOperand Root = DAG.getRoot(); 204 std::vector<SDOperand> OutChains; 205 206 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 207 MVT::ValueType ObjectVT = getValueType(I->getType()); 208 209 switch (ObjectVT) { 210 default: assert(0 && "Unhandled argument type!"); 211 case MVT::i1: 212 case MVT::i8: 213 case MVT::i16: 214 case MVT::i32: 215 if (I->use_empty()) { // Argument is dead. 216 if (CurArgReg < ArgRegEnd) ++CurArgReg; 217 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 218 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 219 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 220 MF.addLiveIn(*CurArgReg++, VReg); 221 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 222 if (ObjectVT != MVT::i32) { 223 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 224 : ISD::AssertZext; 225 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 226 DAG.getValueType(ObjectVT)); 227 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 228 } 229 ArgValues.push_back(Arg); 230 } else { 231 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 232 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 233 SDOperand Load; 234 if (ObjectVT == MVT::i32) { 235 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 236 } else { 237 unsigned LoadOp = 238 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 239 240 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 241 DAG.getSrcValue(0), ObjectVT); 242 } 243 ArgValues.push_back(Load); 244 } 245 246 ArgOffset += 4; 247 break; 248 case MVT::f32: 249 if (I->use_empty()) { // Argument is dead. 250 if (CurArgReg < ArgRegEnd) ++CurArgReg; 251 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 252 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 253 // FP value is passed in an integer register. 254 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 255 MF.addLiveIn(*CurArgReg++, VReg); 256 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 257 258 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 259 ArgValues.push_back(Arg); 260 } 261 ArgOffset += 4; 262 break; 263 264 case MVT::i64: 265 case MVT::f64: 266 if (I->use_empty()) { // Argument is dead. 267 if (CurArgReg < ArgRegEnd) ++CurArgReg; 268 if (CurArgReg < ArgRegEnd) ++CurArgReg; 269 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 270 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 271 ((CurArgReg-ArgRegs) & 1) == 0) { 272 // If this is a double argument and the whole thing lives on the stack, 273 // and the argument is aligned, load the double straight from the stack. 274 // We can't do a load in cases like void foo([6ints], int,double), 275 // because the double wouldn't be aligned! 276 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 277 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 278 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 279 DAG.getSrcValue(0))); 280 } else { 281 SDOperand HiVal; 282 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 283 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 284 MF.addLiveIn(*CurArgReg++, VRegHi); 285 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 286 } else { 287 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 288 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 289 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 290 } 291 292 SDOperand LoVal; 293 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 294 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 295 MF.addLiveIn(*CurArgReg++, VRegLo); 296 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 297 } else { 298 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 299 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 300 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 301 } 302 303 // Compose the two halves together into an i64 unit. 304 SDOperand WholeValue = 305 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 306 307 // If we want a double, do a bit convert. 308 if (ObjectVT == MVT::f64) 309 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 310 311 ArgValues.push_back(WholeValue); 312 } 313 ArgOffset += 8; 314 break; 315 } 316 } 317 318 // Store remaining ArgRegs to the stack if this is a varargs function. 319 if (F.getFunctionType()->isVarArg()) { 320 // Remember the vararg offset for the va_start implementation. 321 VarArgsFrameOffset = ArgOffset; 322 323 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 324 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 325 MF.addLiveIn(*CurArgReg, VReg); 326 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 327 328 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 329 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 330 331 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 332 Arg, FIPtr, DAG.getSrcValue(0))); 333 ArgOffset += 4; 334 } 335 } 336 337 if (!OutChains.empty()) 338 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 339 340 // Finally, inform the code generator which regs we return values in. 341 switch (getValueType(F.getReturnType())) { 342 default: assert(0 && "Unknown type!"); 343 case MVT::isVoid: break; 344 case MVT::i1: 345 case MVT::i8: 346 case MVT::i16: 347 case MVT::i32: 348 MF.addLiveOut(V8::I0); 349 break; 350 case MVT::i64: 351 MF.addLiveOut(V8::I0); 352 MF.addLiveOut(V8::I1); 353 break; 354 case MVT::f32: 355 MF.addLiveOut(V8::F0); 356 break; 357 case MVT::f64: 358 MF.addLiveOut(V8::D0); 359 break; 360 } 361 362 return ArgValues; 363} 364 365std::pair<SDOperand, SDOperand> 366SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 367 bool isVarArg, unsigned CC, 368 bool isTailCall, SDOperand Callee, 369 ArgListTy &Args, SelectionDAG &DAG) { 370 MachineFunction &MF = DAG.getMachineFunction(); 371 // Count the size of the outgoing arguments. 372 unsigned ArgsSize = 0; 373 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 374 switch (getValueType(Args[i].second)) { 375 default: assert(0 && "Unknown value type!"); 376 case MVT::i1: 377 case MVT::i8: 378 case MVT::i16: 379 case MVT::i32: 380 case MVT::f32: 381 ArgsSize += 4; 382 break; 383 case MVT::i64: 384 case MVT::f64: 385 ArgsSize += 8; 386 break; 387 } 388 } 389 if (ArgsSize > 4*6) 390 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 391 else 392 ArgsSize = 0; 393 394 // Keep stack frames 8-byte aligned. 395 ArgsSize = (ArgsSize+7) & ~7; 396 397 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 398 DAG.getConstant(ArgsSize, getPointerTy())); 399 400 SDOperand StackPtr, NullSV; 401 std::vector<SDOperand> Stores; 402 std::vector<SDOperand> RegValuesToPass; 403 unsigned ArgOffset = 68; 404 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 405 SDOperand Val = Args[i].first; 406 MVT::ValueType ObjectVT = Val.getValueType(); 407 SDOperand ValToStore(0, 0); 408 unsigned ObjSize; 409 switch (ObjectVT) { 410 default: assert(0 && "Unhandled argument type!"); 411 case MVT::i1: 412 case MVT::i8: 413 case MVT::i16: 414 // Promote the integer to 32-bits. If the input type is signed, use a 415 // sign extend, otherwise use a zero extend. 416 if (Args[i].second->isSigned()) 417 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 418 else 419 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 420 // FALL THROUGH 421 case MVT::i32: 422 ObjSize = 4; 423 424 if (RegValuesToPass.size() >= 6) { 425 ValToStore = Val; 426 } else { 427 RegValuesToPass.push_back(Val); 428 } 429 break; 430 case MVT::f32: 431 ObjSize = 4; 432 if (RegValuesToPass.size() >= 6) { 433 ValToStore = Val; 434 } else { 435 // Convert this to a FP value in an int reg. 436 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 437 RegValuesToPass.push_back(Val); 438 } 439 break; 440 case MVT::f64: 441 ObjSize = 8; 442 // If we can store this directly into the outgoing slot, do so. We can 443 // do this when all ArgRegs are used and if the outgoing slot is aligned. 444 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 445 ValToStore = Val; 446 break; 447 } 448 449 // Otherwise, convert this to a FP value in int regs. 450 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 451 // FALL THROUGH 452 case MVT::i64: 453 ObjSize = 8; 454 if (RegValuesToPass.size() >= 6) { 455 ValToStore = Val; // Whole thing is passed in memory. 456 break; 457 } 458 459 // Split the value into top and bottom part. Top part goes in a reg. 460 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 461 DAG.getConstant(1, MVT::i32)); 462 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 463 DAG.getConstant(0, MVT::i32)); 464 RegValuesToPass.push_back(Hi); 465 466 if (RegValuesToPass.size() >= 6) { 467 ValToStore = Lo; 468 ArgOffset += 4; 469 ObjSize = 4; 470 } else { 471 RegValuesToPass.push_back(Lo); 472 } 473 break; 474 } 475 476 if (ValToStore.Val) { 477 if (!StackPtr.Val) { 478 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 479 NullSV = DAG.getSrcValue(NULL); 480 } 481 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 482 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 483 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 484 ValToStore, PtrOff, NullSV)); 485 } 486 ArgOffset += ObjSize; 487 } 488 489 // Emit all stores, make sure the occur before any copies into physregs. 490 if (!Stores.empty()) 491 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 492 493 static const unsigned ArgRegs[] = { 494 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 495 }; 496 497 // Build a sequence of copy-to-reg nodes chained together with token chain 498 // and flag operands which copy the outgoing args into O[0-5]. 499 SDOperand InFlag; 500 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 501 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 502 InFlag = Chain.getValue(1); 503 } 504 505 // If the callee is a GlobalAddress node (quite common, every direct call is) 506 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 507 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 508 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 509 510 std::vector<MVT::ValueType> NodeTys; 511 NodeTys.push_back(MVT::Other); // Returns a chain 512 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 513 if (InFlag.Val) 514 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 515 else 516 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 517 InFlag = Chain.getValue(1); 518 519 MVT::ValueType RetTyVT = getValueType(RetTy); 520 SDOperand RetVal; 521 if (RetTyVT != MVT::isVoid) { 522 switch (RetTyVT) { 523 default: assert(0 && "Unknown value type to return!"); 524 case MVT::i1: 525 case MVT::i8: 526 case MVT::i16: 527 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 528 Chain = RetVal.getValue(1); 529 530 // Add a note to keep track of whether it is sign or zero extended. 531 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 532 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 533 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 534 break; 535 case MVT::i32: 536 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 537 Chain = RetVal.getValue(1); 538 break; 539 case MVT::f32: 540 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 541 Chain = RetVal.getValue(1); 542 break; 543 case MVT::f64: 544 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 545 Chain = RetVal.getValue(1); 546 break; 547 case MVT::i64: 548 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 549 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 550 Lo.getValue(2)); 551 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 552 Chain = Hi.getValue(1); 553 break; 554 } 555 } 556 557 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 558 DAG.getConstant(ArgsSize, getPointerTy())); 559 560 return std::make_pair(RetVal, Chain); 561} 562 563SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 564 SelectionDAG &DAG) { 565 SDOperand Copy; 566 switch (Op.getValueType()) { 567 default: assert(0 && "Unknown type to return!"); 568 case MVT::i32: 569 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 570 break; 571 case MVT::f32: 572 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 573 break; 574 case MVT::f64: 575 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 576 break; 577 case MVT::i64: 578 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 579 DAG.getConstant(1, MVT::i32)); 580 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 581 DAG.getConstant(0, MVT::i32)); 582 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 583 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 584 break; 585 } 586 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 587} 588 589SDOperand SparcV8TargetLowering:: 590LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 591 SelectionDAG &DAG) { 592 593 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 594 DAG.getRegister(V8::I6, MVT::i32), 595 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 596 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset, 597 VAListP, DAG.getSrcValue(VAListV)); 598} 599 600std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 601LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 602 const Type *ArgTy, SelectionDAG &DAG) { 603 // Load the pointer out of the valist. 604 SDOperand Ptr = DAG.getLoad(MVT::i32, Chain, 605 VAListP, DAG.getSrcValue(VAListV)); 606 MVT::ValueType ArgVT = getValueType(ArgTy); 607 SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1), 608 Ptr, DAG.getSrcValue(NULL)); 609 // Increment the pointer. 610 Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr, 611 DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32)); 612 // Store it back to the valist. 613 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr, 614 VAListP, DAG.getSrcValue(VAListV)); 615 return std::make_pair(Val, Chain); 616} 617 618std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 619LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 620 SelectionDAG &DAG) { 621 assert(0 && "Unimp"); 622 abort(); 623} 624 625SDOperand SparcV8TargetLowering:: 626LowerOperation(SDOperand Op, SelectionDAG &DAG) { 627 switch (Op.getOpcode()) { 628 default: assert(0 && "Should not custom lower this!"); 629 case ISD::GlobalAddress: { 630 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 631 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 632 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 633 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 634 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 635 } 636 case ISD::ConstantPool: { 637 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 638 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 639 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 640 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 641 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 642 } 643 case ISD::FP_TO_SINT: 644 // Convert the fp value to integer in an FP register. 645 assert(Op.getValueType() == MVT::i32); 646 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 647 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 648 case ISD::SINT_TO_FP: { 649 assert(Op.getOperand(0).getValueType() == MVT::i32); 650 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 651 // Convert the int value to FP in an FP register. 652 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp); 653 } 654 case ISD::BR_CC: { 655 SDOperand Chain = Op.getOperand(0); 656 SDOperand CC = Op.getOperand(1); 657 SDOperand LHS = Op.getOperand(2); 658 SDOperand RHS = Op.getOperand(3); 659 SDOperand Dest = Op.getOperand(4); 660 661 // Get the condition flag. 662 if (LHS.getValueType() == MVT::i32) { 663 std::vector<MVT::ValueType> VTs; 664 VTs.push_back(MVT::i32); 665 VTs.push_back(MVT::Flag); 666 std::vector<SDOperand> Ops; 667 Ops.push_back(LHS); 668 Ops.push_back(RHS); 669 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 670 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 671 } else { 672 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 673 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 674 } 675 } 676 case ISD::SELECT_CC: { 677 SDOperand LHS = Op.getOperand(0); 678 SDOperand RHS = Op.getOperand(1); 679 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 680 SDOperand TrueVal = Op.getOperand(2); 681 SDOperand FalseVal = Op.getOperand(3); 682 683 SDOperand CompareFlag; 684 unsigned Opc; 685 if (LHS.getValueType() == MVT::i32) { 686 std::vector<MVT::ValueType> VTs; 687 VTs.push_back(LHS.getValueType()); // subcc returns a value 688 VTs.push_back(MVT::Flag); 689 std::vector<SDOperand> Ops; 690 Ops.push_back(LHS); 691 Ops.push_back(RHS); 692 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 693 Opc = V8ISD::SELECT_ICC; 694 } else { 695 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 696 Opc = V8ISD::SELECT_FCC; 697 } 698 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 699 DAG.getConstant(CC, MVT::i32), CompareFlag); 700 } 701 } 702} 703 704MachineBasicBlock * 705SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 706 MachineBasicBlock *BB) { 707 unsigned BROpcode; 708 // Figure out the conditional branch opcode to use for this select_cc. 709 switch (MI->getOpcode()) { 710 default: assert(0 && "Unknown SELECT_CC!"); 711 case V8::SELECT_CC_Int_ICC: 712 case V8::SELECT_CC_FP_ICC: 713 case V8::SELECT_CC_DFP_ICC: 714 // Integer compare. 715 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 716 default: assert(0 && "Unknown integer condition code!"); 717 case ISD::SETEQ: BROpcode = V8::BE; break; 718 case ISD::SETNE: BROpcode = V8::BNE; break; 719 case ISD::SETLT: BROpcode = V8::BL; break; 720 case ISD::SETGT: BROpcode = V8::BG; break; 721 case ISD::SETLE: BROpcode = V8::BLE; break; 722 case ISD::SETGE: BROpcode = V8::BGE; break; 723 case ISD::SETULT: BROpcode = V8::BCS; break; 724 case ISD::SETULE: BROpcode = V8::BLEU; break; 725 case ISD::SETUGT: BROpcode = V8::BGU; break; 726 case ISD::SETUGE: BROpcode = V8::BCC; break; 727 } 728 break; 729 case V8::SELECT_CC_Int_FCC: 730 case V8::SELECT_CC_FP_FCC: 731 case V8::SELECT_CC_DFP_FCC: 732 // FP compare. 733 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 734 default: assert(0 && "Unknown fp condition code!"); 735 case ISD::SETEQ: BROpcode = V8::FBE; break; 736 case ISD::SETNE: BROpcode = V8::FBNE; break; 737 case ISD::SETLT: BROpcode = V8::FBL; break; 738 case ISD::SETGT: BROpcode = V8::FBG; break; 739 case ISD::SETLE: BROpcode = V8::FBLE; break; 740 case ISD::SETGE: BROpcode = V8::FBGE; break; 741 case ISD::SETULT: BROpcode = V8::FBUL; break; 742 case ISD::SETULE: BROpcode = V8::FBULE; break; 743 case ISD::SETUGT: BROpcode = V8::FBUG; break; 744 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 745 case ISD::SETUO: BROpcode = V8::FBU; break; 746 case ISD::SETO: BROpcode = V8::FBO; break; 747 case ISD::SETONE: BROpcode = V8::FBLG; break; 748 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 749 } 750 break; 751 } 752 753 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 754 // control-flow pattern. The incoming instruction knows the destination vreg 755 // to set, the condition code register to branch on, the true/false values to 756 // select between, and a branch opcode to use. 757 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 758 ilist<MachineBasicBlock>::iterator It = BB; 759 ++It; 760 761 // thisMBB: 762 // ... 763 // TrueVal = ... 764 // [f]bCC copy1MBB 765 // fallthrough --> copy0MBB 766 MachineBasicBlock *thisMBB = BB; 767 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 768 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 769 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 770 MachineFunction *F = BB->getParent(); 771 F->getBasicBlockList().insert(It, copy0MBB); 772 F->getBasicBlockList().insert(It, sinkMBB); 773 // Update machine-CFG edges 774 BB->addSuccessor(copy0MBB); 775 BB->addSuccessor(sinkMBB); 776 777 // copy0MBB: 778 // %FalseValue = ... 779 // # fallthrough to sinkMBB 780 BB = copy0MBB; 781 782 // Update machine-CFG edges 783 BB->addSuccessor(sinkMBB); 784 785 // sinkMBB: 786 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 787 // ... 788 BB = sinkMBB; 789 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 790 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 791 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 792 793 delete MI; // The pseudo instruction is gone now. 794 return BB; 795} 796 797//===----------------------------------------------------------------------===// 798// Instruction Selector Implementation 799//===----------------------------------------------------------------------===// 800 801//===--------------------------------------------------------------------===// 802/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 803/// instructions for SelectionDAG operations. 804/// 805namespace { 806class SparcV8DAGToDAGISel : public SelectionDAGISel { 807 SparcV8TargetLowering V8Lowering; 808public: 809 SparcV8DAGToDAGISel(TargetMachine &TM) 810 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 811 812 SDOperand Select(SDOperand Op); 813 814 // Complex Pattern Selectors. 815 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 816 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 817 818 /// InstructionSelectBasicBlock - This callback is invoked by 819 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 820 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 821 822 virtual const char *getPassName() const { 823 return "PowerPC DAG->DAG Pattern Instruction Selection"; 824 } 825 826 // Include the pieces autogenerated from the target description. 827#include "SparcV8GenDAGISel.inc" 828}; 829} // end anonymous namespace 830 831/// InstructionSelectBasicBlock - This callback is invoked by 832/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 833void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 834 DEBUG(BB->dump()); 835 836 // Select target instructions for the DAG. 837 DAG.setRoot(Select(DAG.getRoot())); 838 CodeGenMap.clear(); 839 DAG.RemoveDeadNodes(); 840 841 // Emit machine code to BB. 842 ScheduleAndEmitDAG(DAG); 843} 844 845bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 846 SDOperand &Offset) { 847 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 848 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 849 Offset = CurDAG->getTargetConstant(0, MVT::i32); 850 return true; 851 } 852 853 if (Addr.getOpcode() == ISD::ADD) { 854 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 855 if (Predicate_simm13(CN)) { 856 if (FrameIndexSDNode *FIN = 857 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 858 // Constant offset from frame ref. 859 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 860 } else { 861 Base = Select(Addr.getOperand(0)); 862 } 863 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 864 return true; 865 } 866 } 867 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 868 Base = Select(Addr.getOperand(1)); 869 Offset = Addr.getOperand(0).getOperand(0); 870 return true; 871 } 872 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 873 Base = Select(Addr.getOperand(0)); 874 Offset = Addr.getOperand(1).getOperand(0); 875 return true; 876 } 877 } 878 Base = Select(Addr); 879 Offset = CurDAG->getTargetConstant(0, MVT::i32); 880 return true; 881} 882 883bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 884 SDOperand &R2) { 885 if (Addr.getOpcode() == ISD::FrameIndex) return false; 886 if (Addr.getOpcode() == ISD::ADD) { 887 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 888 Predicate_simm13(Addr.getOperand(1).Val)) 889 return false; // Let the reg+imm pattern catch this! 890 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 891 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 892 return false; // Let the reg+imm pattern catch this! 893 R1 = Select(Addr.getOperand(0)); 894 R2 = Select(Addr.getOperand(1)); 895 return true; 896 } 897 898 R1 = Select(Addr); 899 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 900 return true; 901} 902 903SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 904 SDNode *N = Op.Val; 905 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 906 N->getOpcode() < V8ISD::FIRST_NUMBER) 907 return Op; // Already selected. 908 // If this has already been converted, use it. 909 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 910 if (CGMI != CodeGenMap.end()) return CGMI->second; 911 912 switch (N->getOpcode()) { 913 default: break; 914 case ISD::FrameIndex: { 915 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 916 if (N->hasOneUse()) 917 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 918 CurDAG->getTargetFrameIndex(FI, MVT::i32), 919 CurDAG->getTargetConstant(0, MVT::i32)); 920 return CodeGenMap[Op] = 921 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 922 CurDAG->getTargetFrameIndex(FI, MVT::i32), 923 CurDAG->getTargetConstant(0, MVT::i32)); 924 } 925 case ISD::ADD_PARTS: { 926 SDOperand LHSL = Select(N->getOperand(0)); 927 SDOperand LHSH = Select(N->getOperand(1)); 928 SDOperand RHSL = Select(N->getOperand(2)); 929 SDOperand RHSH = Select(N->getOperand(3)); 930 // FIXME, handle immediate RHS. 931 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 932 LHSL, RHSL); 933 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 934 Low.getValue(1)); 935 CodeGenMap[SDOperand(N, 0)] = Low; 936 CodeGenMap[SDOperand(N, 1)] = Hi; 937 return Op.ResNo ? Hi : Low; 938 } 939 case ISD::SUB_PARTS: { 940 SDOperand LHSL = Select(N->getOperand(0)); 941 SDOperand LHSH = Select(N->getOperand(1)); 942 SDOperand RHSL = Select(N->getOperand(2)); 943 SDOperand RHSH = Select(N->getOperand(3)); 944 // FIXME, handle immediate RHS. 945 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 946 LHSL, RHSL); 947 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 948 Low.getValue(1)); 949 CodeGenMap[SDOperand(N, 0)] = Low; 950 CodeGenMap[SDOperand(N, 1)] = Hi; 951 return Op.ResNo ? Hi : Low; 952 } 953 case ISD::SDIV: 954 case ISD::UDIV: { 955 // FIXME: should use a custom expander to expose the SRA to the dag. 956 SDOperand DivLHS = Select(N->getOperand(0)); 957 SDOperand DivRHS = Select(N->getOperand(1)); 958 959 // Set the Y register to the high-part. 960 SDOperand TopPart; 961 if (N->getOpcode() == ISD::SDIV) { 962 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 963 CurDAG->getTargetConstant(31, MVT::i32)); 964 } else { 965 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 966 } 967 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 968 CurDAG->getRegister(V8::G0, MVT::i32)); 969 970 // FIXME: Handle div by immediate. 971 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 972 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 973 } 974 case ISD::MULHU: 975 case ISD::MULHS: { 976 // FIXME: Handle mul by immediate. 977 SDOperand MulLHS = Select(N->getOperand(0)); 978 SDOperand MulRHS = Select(N->getOperand(1)); 979 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 980 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 981 MulLHS, MulRHS); 982 // The high part is in the Y register. 983 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 984 } 985 case ISD::CALL: 986 // FIXME: This is a workaround for a bug in tblgen. 987 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 988 // Emits: (CALL:void (tglobaladdr:i32):$dst) 989 // Pattern complexity = 2 cost = 1 990 SDOperand N1 = N->getOperand(1); 991 if (N1.getOpcode() != ISD::TargetGlobalAddress && 992 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 993 SDOperand InFlag = SDOperand(0, 0); 994 SDOperand Chain = N->getOperand(0); 995 SDOperand Tmp0 = N1; 996 Chain = Select(Chain); 997 SDOperand Result; 998 if (N->getNumOperands() == 3) { 999 InFlag = Select(N->getOperand(2)); 1000 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1001 Chain, InFlag); 1002 } else { 1003 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1004 Chain); 1005 } 1006 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1007 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1008 return Result.getValue(Op.ResNo); 1009 } 1010 P47Fail:; 1011 1012 } 1013 1014 return SelectCode(Op); 1015} 1016 1017 1018/// createPPCISelDag - This pass converts a legalized DAG into a 1019/// PowerPC-specific DAG, ready for instruction scheduling. 1020/// 1021FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1022 return new SparcV8DAGToDAGISel(TM); 1023} 1024