SparcISelDAGToDAG.cpp revision bd564bfc63163e31f320c3da9749db70992dc35e
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/CodeGen/SSARegMap.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Debug.h" 27#include <iostream> 28#include <queue> 29#include <set> 30using namespace llvm; 31 32//===----------------------------------------------------------------------===// 33// TargetLowering Implementation 34//===----------------------------------------------------------------------===// 35 36namespace SPISD { 37 enum { 38 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 39 CMPICC, // Compare two GPR operands, set icc. 40 CMPFCC, // Compare two FP operands, set fcc. 41 BRICC, // Branch to dest on icc condition 42 BRFCC, // Branch to dest on fcc condition 43 SELECT_ICC, // Select between two values using the current ICC flags. 44 SELECT_FCC, // Select between two values using the current FCC flags. 45 46 Hi, Lo, // Hi/Lo operations, typically on a global address. 47 48 FTOI, // FP to Int within a FP register. 49 ITOF, // Int to FP within a FP register. 50 51 CALL, // A call instruction. 52 RET_FLAG // Return with a flag operand. 53 }; 54} 55 56/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 57/// condition. 58static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 59 switch (CC) { 60 default: assert(0 && "Unknown integer condition code!"); 61 case ISD::SETEQ: return SPCC::ICC_E; 62 case ISD::SETNE: return SPCC::ICC_NE; 63 case ISD::SETLT: return SPCC::ICC_L; 64 case ISD::SETGT: return SPCC::ICC_G; 65 case ISD::SETLE: return SPCC::ICC_LE; 66 case ISD::SETGE: return SPCC::ICC_GE; 67 case ISD::SETULT: return SPCC::ICC_CS; 68 case ISD::SETULE: return SPCC::ICC_LEU; 69 case ISD::SETUGT: return SPCC::ICC_GU; 70 case ISD::SETUGE: return SPCC::ICC_CC; 71 } 72} 73 74/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 75/// FCC condition. 76static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 77 switch (CC) { 78 default: assert(0 && "Unknown fp condition code!"); 79 case ISD::SETEQ: 80 case ISD::SETOEQ: return SPCC::FCC_E; 81 case ISD::SETNE: 82 case ISD::SETUNE: return SPCC::FCC_NE; 83 case ISD::SETLT: 84 case ISD::SETOLT: return SPCC::FCC_L; 85 case ISD::SETGT: 86 case ISD::SETOGT: return SPCC::FCC_G; 87 case ISD::SETLE: 88 case ISD::SETOLE: return SPCC::FCC_LE; 89 case ISD::SETGE: 90 case ISD::SETOGE: return SPCC::FCC_GE; 91 case ISD::SETULT: return SPCC::FCC_UL; 92 case ISD::SETULE: return SPCC::FCC_ULE; 93 case ISD::SETUGT: return SPCC::FCC_UG; 94 case ISD::SETUGE: return SPCC::FCC_UGE; 95 case ISD::SETUO: return SPCC::FCC_U; 96 case ISD::SETO: return SPCC::FCC_O; 97 case ISD::SETONE: return SPCC::FCC_LG; 98 case ISD::SETUEQ: return SPCC::FCC_UE; 99 } 100} 101 102namespace { 103 class SparcTargetLowering : public TargetLowering { 104 int VarArgsFrameOffset; // Frame offset to start of varargs area. 105 public: 106 SparcTargetLowering(TargetMachine &TM); 107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 108 109 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 110 /// in Mask are known to be either zero or one and return them in the 111 /// KnownZero/KnownOne bitsets. 112 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 113 uint64_t Mask, 114 uint64_t &KnownZero, 115 uint64_t &KnownOne, 116 unsigned Depth = 0) const; 117 118 virtual std::vector<SDOperand> 119 LowerArguments(Function &F, SelectionDAG &DAG); 120 virtual std::pair<SDOperand, SDOperand> 121 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 122 unsigned CC, 123 bool isTailCall, SDOperand Callee, ArgListTy &Args, 124 SelectionDAG &DAG); 125 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 126 MachineBasicBlock *MBB); 127 128 virtual const char *getTargetNodeName(unsigned Opcode) const; 129 }; 130} 131 132SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 133 : TargetLowering(TM) { 134 135 // Set up the register classes. 136 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 137 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 138 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 139 140 // Custom legalize GlobalAddress nodes into LO/HI parts. 141 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 142 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 143 144 // Sparc doesn't have sext_inreg, replace them with shl/sra 145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 148 149 // Sparc has no REM operation. 150 setOperationAction(ISD::UREM, MVT::i32, Expand); 151 setOperationAction(ISD::SREM, MVT::i32, Expand); 152 153 // Custom expand fp<->sint 154 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 155 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 156 157 // Expand fp<->uint 158 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 159 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 160 161 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 162 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 163 164 // Turn FP extload into load/fextend 165 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 166 167 // Sparc has no select or setcc: expand to SELECT_CC. 168 setOperationAction(ISD::SELECT, MVT::i32, Expand); 169 setOperationAction(ISD::SELECT, MVT::f32, Expand); 170 setOperationAction(ISD::SELECT, MVT::f64, Expand); 171 setOperationAction(ISD::SETCC, MVT::i32, Expand); 172 setOperationAction(ISD::SETCC, MVT::f32, Expand); 173 setOperationAction(ISD::SETCC, MVT::f64, Expand); 174 175 // Sparc doesn't have BRCOND either, it has BR_CC. 176 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 177 setOperationAction(ISD::BRIND, MVT::i32, Expand); 178 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 179 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 180 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 181 182 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 183 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 184 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 185 186 // SPARC has no intrinsics for these particular operations. 187 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 188 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 189 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 190 191 setOperationAction(ISD::FSIN , MVT::f64, Expand); 192 setOperationAction(ISD::FCOS , MVT::f64, Expand); 193 setOperationAction(ISD::FSIN , MVT::f32, Expand); 194 setOperationAction(ISD::FCOS , MVT::f32, Expand); 195 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 196 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 197 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 198 setOperationAction(ISD::ROTL , MVT::i32, Expand); 199 setOperationAction(ISD::ROTR , MVT::i32, Expand); 200 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 201 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 202 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 203 204 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 205 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 206 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 207 208 // We don't have line number support yet. 209 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 210 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 211 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 212 213 // RET must be custom lowered, to meet ABI requirements 214 setOperationAction(ISD::RET , MVT::Other, Custom); 215 216 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 217 setOperationAction(ISD::VASTART , MVT::Other, Custom); 218 // VAARG needs to be lowered to not do unaligned accesses for doubles. 219 setOperationAction(ISD::VAARG , MVT::Other, Custom); 220 221 // Use the default implementation. 222 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 223 setOperationAction(ISD::VAEND , MVT::Other, Expand); 224 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 225 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 227 228 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 229 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 230 231 setStackPointerRegisterToSaveRestore(SP::O6); 232 233 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 234 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 235 } 236 237 computeRegisterProperties(); 238} 239 240const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 241 switch (Opcode) { 242 default: return 0; 243 case SPISD::CMPICC: return "SPISD::CMPICC"; 244 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 245 case SPISD::BRICC: return "SPISD::BRICC"; 246 case SPISD::BRFCC: return "SPISD::BRFCC"; 247 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 248 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 249 case SPISD::Hi: return "SPISD::Hi"; 250 case SPISD::Lo: return "SPISD::Lo"; 251 case SPISD::FTOI: return "SPISD::FTOI"; 252 case SPISD::ITOF: return "SPISD::ITOF"; 253 case SPISD::CALL: return "SPISD::CALL"; 254 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 255 } 256} 257 258/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 259/// be zero. Op is expected to be a target specific node. Used by DAG 260/// combiner. 261void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 262 uint64_t Mask, 263 uint64_t &KnownZero, 264 uint64_t &KnownOne, 265 unsigned Depth) const { 266 uint64_t KnownZero2, KnownOne2; 267 KnownZero = KnownOne = 0; // Don't know anything. 268 269 switch (Op.getOpcode()) { 270 default: break; 271 case SPISD::SELECT_ICC: 272 case SPISD::SELECT_FCC: 273 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 274 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 275 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 276 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 277 278 // Only known if known in both the LHS and RHS. 279 KnownOne &= KnownOne2; 280 KnownZero &= KnownZero2; 281 break; 282 } 283} 284 285/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 286/// either one or two GPRs, including FP values. TODO: we should pass FP values 287/// in FP registers for fastcc functions. 288std::vector<SDOperand> 289SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 290 MachineFunction &MF = DAG.getMachineFunction(); 291 SSARegMap *RegMap = MF.getSSARegMap(); 292 std::vector<SDOperand> ArgValues; 293 294 static const unsigned ArgRegs[] = { 295 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 296 }; 297 298 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 299 unsigned ArgOffset = 68; 300 301 SDOperand Root = DAG.getRoot(); 302 std::vector<SDOperand> OutChains; 303 304 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 305 MVT::ValueType ObjectVT = getValueType(I->getType()); 306 307 switch (ObjectVT) { 308 default: assert(0 && "Unhandled argument type!"); 309 case MVT::i1: 310 case MVT::i8: 311 case MVT::i16: 312 case MVT::i32: 313 if (I->use_empty()) { // Argument is dead. 314 if (CurArgReg < ArgRegEnd) ++CurArgReg; 315 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 316 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 317 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 318 MF.addLiveIn(*CurArgReg++, VReg); 319 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 320 if (ObjectVT != MVT::i32) { 321 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 322 : ISD::AssertZext; 323 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 324 DAG.getValueType(ObjectVT)); 325 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 326 } 327 ArgValues.push_back(Arg); 328 } else { 329 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 330 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 331 SDOperand Load; 332 if (ObjectVT == MVT::i32) { 333 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 334 } else { 335 unsigned LoadOp = 336 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 337 338 // Sparc is big endian, so add an offset based on the ObjectVT. 339 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 340 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 341 DAG.getConstant(Offset, MVT::i32)); 342 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 343 DAG.getSrcValue(0), ObjectVT); 344 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 345 } 346 ArgValues.push_back(Load); 347 } 348 349 ArgOffset += 4; 350 break; 351 case MVT::f32: 352 if (I->use_empty()) { // Argument is dead. 353 if (CurArgReg < ArgRegEnd) ++CurArgReg; 354 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 355 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 356 // FP value is passed in an integer register. 357 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 358 MF.addLiveIn(*CurArgReg++, VReg); 359 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 360 361 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 362 ArgValues.push_back(Arg); 363 } else { 364 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 365 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 366 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); 367 ArgValues.push_back(Load); 368 } 369 ArgOffset += 4; 370 break; 371 372 case MVT::i64: 373 case MVT::f64: 374 if (I->use_empty()) { // Argument is dead. 375 if (CurArgReg < ArgRegEnd) ++CurArgReg; 376 if (CurArgReg < ArgRegEnd) ++CurArgReg; 377 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 378 } else if (/* FIXME: Apparently this isn't safe?? */ 379 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 380 ((CurArgReg-ArgRegs) & 1) == 0) { 381 // If this is a double argument and the whole thing lives on the stack, 382 // and the argument is aligned, load the double straight from the stack. 383 // We can't do a load in cases like void foo([6ints], int,double), 384 // because the double wouldn't be aligned! 385 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 386 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 387 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 388 DAG.getSrcValue(0))); 389 } else { 390 SDOperand HiVal; 391 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 392 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 393 MF.addLiveIn(*CurArgReg++, VRegHi); 394 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 395 } else { 396 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 397 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 398 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 399 } 400 401 SDOperand LoVal; 402 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 403 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 404 MF.addLiveIn(*CurArgReg++, VRegLo); 405 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 406 } else { 407 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 408 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 409 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 410 } 411 412 // Compose the two halves together into an i64 unit. 413 SDOperand WholeValue = 414 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 415 416 // If we want a double, do a bit convert. 417 if (ObjectVT == MVT::f64) 418 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 419 420 ArgValues.push_back(WholeValue); 421 } 422 ArgOffset += 8; 423 break; 424 } 425 } 426 427 // Store remaining ArgRegs to the stack if this is a varargs function. 428 if (F.getFunctionType()->isVarArg()) { 429 // Remember the vararg offset for the va_start implementation. 430 VarArgsFrameOffset = ArgOffset; 431 432 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 433 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 434 MF.addLiveIn(*CurArgReg, VReg); 435 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 436 437 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 438 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 439 440 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 441 Arg, FIPtr, DAG.getSrcValue(0))); 442 ArgOffset += 4; 443 } 444 } 445 446 if (!OutChains.empty()) 447 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 448 &OutChains[0], OutChains.size())); 449 450 // Finally, inform the code generator which regs we return values in. 451 switch (getValueType(F.getReturnType())) { 452 default: assert(0 && "Unknown type!"); 453 case MVT::isVoid: break; 454 case MVT::i1: 455 case MVT::i8: 456 case MVT::i16: 457 case MVT::i32: 458 MF.addLiveOut(SP::I0); 459 break; 460 case MVT::i64: 461 MF.addLiveOut(SP::I0); 462 MF.addLiveOut(SP::I1); 463 break; 464 case MVT::f32: 465 MF.addLiveOut(SP::F0); 466 break; 467 case MVT::f64: 468 MF.addLiveOut(SP::D0); 469 break; 470 } 471 472 return ArgValues; 473} 474 475std::pair<SDOperand, SDOperand> 476SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 477 bool isVarArg, unsigned CC, 478 bool isTailCall, SDOperand Callee, 479 ArgListTy &Args, SelectionDAG &DAG) { 480 // Count the size of the outgoing arguments. 481 unsigned ArgsSize = 0; 482 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 483 switch (getValueType(Args[i].second)) { 484 default: assert(0 && "Unknown value type!"); 485 case MVT::i1: 486 case MVT::i8: 487 case MVT::i16: 488 case MVT::i32: 489 case MVT::f32: 490 ArgsSize += 4; 491 break; 492 case MVT::i64: 493 case MVT::f64: 494 ArgsSize += 8; 495 break; 496 } 497 } 498 if (ArgsSize > 4*6) 499 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 500 else 501 ArgsSize = 0; 502 503 // Keep stack frames 8-byte aligned. 504 ArgsSize = (ArgsSize+7) & ~7; 505 506 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 507 508 SDOperand StackPtr, NullSV; 509 std::vector<SDOperand> Stores; 510 std::vector<SDOperand> RegValuesToPass; 511 unsigned ArgOffset = 68; 512 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 513 SDOperand Val = Args[i].first; 514 MVT::ValueType ObjectVT = Val.getValueType(); 515 SDOperand ValToStore(0, 0); 516 unsigned ObjSize; 517 switch (ObjectVT) { 518 default: assert(0 && "Unhandled argument type!"); 519 case MVT::i1: 520 case MVT::i8: 521 case MVT::i16: 522 // Promote the integer to 32-bits. If the input type is signed, use a 523 // sign extend, otherwise use a zero extend. 524 if (Args[i].second->isSigned()) 525 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 526 else 527 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 528 // FALL THROUGH 529 case MVT::i32: 530 ObjSize = 4; 531 532 if (RegValuesToPass.size() >= 6) { 533 ValToStore = Val; 534 } else { 535 RegValuesToPass.push_back(Val); 536 } 537 break; 538 case MVT::f32: 539 ObjSize = 4; 540 if (RegValuesToPass.size() >= 6) { 541 ValToStore = Val; 542 } else { 543 // Convert this to a FP value in an int reg. 544 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 545 RegValuesToPass.push_back(Val); 546 } 547 break; 548 case MVT::f64: 549 ObjSize = 8; 550 // If we can store this directly into the outgoing slot, do so. We can 551 // do this when all ArgRegs are used and if the outgoing slot is aligned. 552 // FIXME: McGill/misr fails with this. 553 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 554 ValToStore = Val; 555 break; 556 } 557 558 // Otherwise, convert this to a FP value in int regs. 559 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 560 // FALL THROUGH 561 case MVT::i64: 562 ObjSize = 8; 563 if (RegValuesToPass.size() >= 6) { 564 ValToStore = Val; // Whole thing is passed in memory. 565 break; 566 } 567 568 // Split the value into top and bottom part. Top part goes in a reg. 569 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 570 DAG.getConstant(1, MVT::i32)); 571 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 572 DAG.getConstant(0, MVT::i32)); 573 RegValuesToPass.push_back(Hi); 574 575 if (RegValuesToPass.size() >= 6) { 576 ValToStore = Lo; 577 ArgOffset += 4; 578 ObjSize = 4; 579 } else { 580 RegValuesToPass.push_back(Lo); 581 } 582 break; 583 } 584 585 if (ValToStore.Val) { 586 if (!StackPtr.Val) { 587 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 588 NullSV = DAG.getSrcValue(NULL); 589 } 590 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 591 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 592 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 593 ValToStore, PtrOff, NullSV)); 594 } 595 ArgOffset += ObjSize; 596 } 597 598 // Emit all stores, make sure the occur before any copies into physregs. 599 if (!Stores.empty()) 600 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 601 602 static const unsigned ArgRegs[] = { 603 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 604 }; 605 606 // Build a sequence of copy-to-reg nodes chained together with token chain 607 // and flag operands which copy the outgoing args into O[0-5]. 608 SDOperand InFlag; 609 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 610 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 611 InFlag = Chain.getValue(1); 612 } 613 614 // If the callee is a GlobalAddress node (quite common, every direct call is) 615 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 616 // Likewise ExternalSymbol -> TargetExternalSymbol. 617 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 618 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 619 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 620 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 621 622 std::vector<MVT::ValueType> NodeTys; 623 NodeTys.push_back(MVT::Other); // Returns a chain 624 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 625 SDOperand Ops[] = { Chain, Callee, InFlag }; 626 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 627 InFlag = Chain.getValue(1); 628 629 MVT::ValueType RetTyVT = getValueType(RetTy); 630 SDOperand RetVal; 631 if (RetTyVT != MVT::isVoid) { 632 switch (RetTyVT) { 633 default: assert(0 && "Unknown value type to return!"); 634 case MVT::i1: 635 case MVT::i8: 636 case MVT::i16: 637 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 638 Chain = RetVal.getValue(1); 639 640 // Add a note to keep track of whether it is sign or zero extended. 641 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 642 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 643 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 644 break; 645 case MVT::i32: 646 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 647 Chain = RetVal.getValue(1); 648 break; 649 case MVT::f32: 650 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 651 Chain = RetVal.getValue(1); 652 break; 653 case MVT::f64: 654 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 655 Chain = RetVal.getValue(1); 656 break; 657 case MVT::i64: 658 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 659 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 660 Lo.getValue(2)); 661 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 662 Chain = Hi.getValue(1); 663 break; 664 } 665 } 666 667 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 668 DAG.getConstant(ArgsSize, getPointerTy())); 669 670 return std::make_pair(RetVal, Chain); 671} 672 673// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 674// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 675static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 676 ISD::CondCode CC, unsigned &SPCC) { 677 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 678 CC == ISD::SETNE && 679 ((LHS.getOpcode() == SPISD::SELECT_ICC && 680 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 681 (LHS.getOpcode() == SPISD::SELECT_FCC && 682 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 683 isa<ConstantSDNode>(LHS.getOperand(0)) && 684 isa<ConstantSDNode>(LHS.getOperand(1)) && 685 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 686 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 687 SDOperand CMPCC = LHS.getOperand(3); 688 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 689 LHS = CMPCC.getOperand(0); 690 RHS = CMPCC.getOperand(1); 691 } 692} 693 694 695SDOperand SparcTargetLowering:: 696LowerOperation(SDOperand Op, SelectionDAG &DAG) { 697 switch (Op.getOpcode()) { 698 default: assert(0 && "Should not custom lower this!"); 699 case ISD::GlobalAddress: { 700 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 701 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 702 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 703 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 704 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 705 } 706 case ISD::ConstantPool: { 707 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 708 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 709 cast<ConstantPoolSDNode>(Op)->getAlignment()); 710 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 711 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 712 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 713 } 714 case ISD::FP_TO_SINT: 715 // Convert the fp value to integer in an FP register. 716 assert(Op.getValueType() == MVT::i32); 717 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 718 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 719 case ISD::SINT_TO_FP: { 720 assert(Op.getOperand(0).getValueType() == MVT::i32); 721 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 722 // Convert the int value to FP in an FP register. 723 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 724 } 725 case ISD::BR_CC: { 726 SDOperand Chain = Op.getOperand(0); 727 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 728 SDOperand LHS = Op.getOperand(2); 729 SDOperand RHS = Op.getOperand(3); 730 SDOperand Dest = Op.getOperand(4); 731 unsigned Opc, SPCC = ~0U; 732 733 // If this is a br_cc of a "setcc", and if the setcc got lowered into 734 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 735 LookThroughSetCC(LHS, RHS, CC, SPCC); 736 737 // Get the condition flag. 738 SDOperand CompareFlag; 739 if (LHS.getValueType() == MVT::i32) { 740 std::vector<MVT::ValueType> VTs; 741 VTs.push_back(MVT::i32); 742 VTs.push_back(MVT::Flag); 743 SDOperand Ops[2] = { LHS, RHS }; 744 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 745 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 746 Opc = SPISD::BRICC; 747 } else { 748 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 749 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 750 Opc = SPISD::BRFCC; 751 } 752 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 753 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 754 } 755 case ISD::SELECT_CC: { 756 SDOperand LHS = Op.getOperand(0); 757 SDOperand RHS = Op.getOperand(1); 758 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 759 SDOperand TrueVal = Op.getOperand(2); 760 SDOperand FalseVal = Op.getOperand(3); 761 unsigned Opc, SPCC = ~0U; 762 763 // If this is a select_cc of a "setcc", and if the setcc got lowered into 764 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 765 LookThroughSetCC(LHS, RHS, CC, SPCC); 766 767 SDOperand CompareFlag; 768 if (LHS.getValueType() == MVT::i32) { 769 std::vector<MVT::ValueType> VTs; 770 VTs.push_back(LHS.getValueType()); // subcc returns a value 771 VTs.push_back(MVT::Flag); 772 SDOperand Ops[2] = { LHS, RHS }; 773 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 774 Opc = SPISD::SELECT_ICC; 775 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 776 } else { 777 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 778 Opc = SPISD::SELECT_FCC; 779 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 780 } 781 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 782 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 783 } 784 case ISD::VASTART: { 785 // vastart just stores the address of the VarArgsFrameIndex slot into the 786 // memory location argument. 787 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 788 DAG.getRegister(SP::I6, MVT::i32), 789 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 790 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 791 Op.getOperand(1), Op.getOperand(2)); 792 } 793 case ISD::VAARG: { 794 SDNode *Node = Op.Val; 795 MVT::ValueType VT = Node->getValueType(0); 796 SDOperand InChain = Node->getOperand(0); 797 SDOperand VAListPtr = Node->getOperand(1); 798 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 799 Node->getOperand(2)); 800 // Increment the pointer, VAList, to the next vaarg 801 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 802 DAG.getConstant(MVT::getSizeInBits(VT)/8, 803 getPointerTy())); 804 // Store the incremented VAList to the legalized pointer 805 InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr, 806 VAListPtr, Node->getOperand(2)); 807 // Load the actual argument out of the pointer VAList, unless this is an 808 // f64 load. 809 if (VT != MVT::f64) { 810 return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0)); 811 } else { 812 // Otherwise, load it as i64, then do a bitconvert. 813 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0)); 814 std::vector<MVT::ValueType> Tys; 815 Tys.push_back(MVT::f64); 816 Tys.push_back(MVT::Other); 817 // Bit-Convert the value to f64. 818 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 819 V.getValue(1) }; 820 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 821 } 822 } 823 case ISD::DYNAMIC_STACKALLOC: { 824 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 825 SDOperand Size = Op.getOperand(1); // Legalize the size. 826 827 unsigned SPReg = SP::O6; 828 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 829 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 830 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 831 832 // The resultant pointer is actually 16 words from the bottom of the stack, 833 // to provide a register spill area. 834 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 835 DAG.getConstant(96, MVT::i32)); 836 std::vector<MVT::ValueType> Tys; 837 Tys.push_back(MVT::i32); 838 Tys.push_back(MVT::Other); 839 SDOperand Ops[2] = { NewVal, Chain }; 840 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 841 } 842 case ISD::RET: { 843 SDOperand Copy; 844 845 switch(Op.getNumOperands()) { 846 default: 847 assert(0 && "Do not know how to return this many arguments!"); 848 abort(); 849 case 1: 850 return SDOperand(); // ret void is legal 851 case 3: { 852 unsigned ArgReg; 853 switch(Op.getOperand(1).getValueType()) { 854 default: assert(0 && "Unknown type to return!"); 855 case MVT::i32: ArgReg = SP::I0; break; 856 case MVT::f32: ArgReg = SP::F0; break; 857 case MVT::f64: ArgReg = SP::D0; break; 858 } 859 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 860 SDOperand()); 861 break; 862 } 863 case 5: 864 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 865 SDOperand()); 866 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 867 break; 868 } 869 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 870 } 871 } 872} 873 874MachineBasicBlock * 875SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 876 MachineBasicBlock *BB) { 877 unsigned BROpcode; 878 unsigned CC; 879 // Figure out the conditional branch opcode to use for this select_cc. 880 switch (MI->getOpcode()) { 881 default: assert(0 && "Unknown SELECT_CC!"); 882 case SP::SELECT_CC_Int_ICC: 883 case SP::SELECT_CC_FP_ICC: 884 case SP::SELECT_CC_DFP_ICC: 885 BROpcode = SP::BCOND; 886 break; 887 case SP::SELECT_CC_Int_FCC: 888 case SP::SELECT_CC_FP_FCC: 889 case SP::SELECT_CC_DFP_FCC: 890 BROpcode = SP::FBCOND; 891 break; 892 } 893 894 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 895 896 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 897 // control-flow pattern. The incoming instruction knows the destination vreg 898 // to set, the condition code register to branch on, the true/false values to 899 // select between, and a branch opcode to use. 900 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 901 ilist<MachineBasicBlock>::iterator It = BB; 902 ++It; 903 904 // thisMBB: 905 // ... 906 // TrueVal = ... 907 // [f]bCC copy1MBB 908 // fallthrough --> copy0MBB 909 MachineBasicBlock *thisMBB = BB; 910 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 911 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 912 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC); 913 MachineFunction *F = BB->getParent(); 914 F->getBasicBlockList().insert(It, copy0MBB); 915 F->getBasicBlockList().insert(It, sinkMBB); 916 // Update machine-CFG edges by first adding all successors of the current 917 // block to the new block which will contain the Phi node for the select. 918 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 919 e = BB->succ_end(); i != e; ++i) 920 sinkMBB->addSuccessor(*i); 921 // Next, remove all successors of the current block, and add the true 922 // and fallthrough blocks as its successors. 923 while(!BB->succ_empty()) 924 BB->removeSuccessor(BB->succ_begin()); 925 BB->addSuccessor(copy0MBB); 926 BB->addSuccessor(sinkMBB); 927 928 // copy0MBB: 929 // %FalseValue = ... 930 // # fallthrough to sinkMBB 931 BB = copy0MBB; 932 933 // Update machine-CFG edges 934 BB->addSuccessor(sinkMBB); 935 936 // sinkMBB: 937 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 938 // ... 939 BB = sinkMBB; 940 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg()) 941 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 942 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 943 944 delete MI; // The pseudo instruction is gone now. 945 return BB; 946} 947 948//===----------------------------------------------------------------------===// 949// Instruction Selector Implementation 950//===----------------------------------------------------------------------===// 951 952//===--------------------------------------------------------------------===// 953/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 954/// instructions for SelectionDAG operations. 955/// 956namespace { 957class SparcDAGToDAGISel : public SelectionDAGISel { 958 SparcTargetLowering Lowering; 959 960 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 961 /// make the right decision when generating code for different targets. 962 const SparcSubtarget &Subtarget; 963public: 964 SparcDAGToDAGISel(TargetMachine &TM) 965 : SelectionDAGISel(Lowering), Lowering(TM), 966 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 967 } 968 969 void Select(SDOperand &Result, SDOperand Op); 970 971 // Complex Pattern Selectors. 972 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 973 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 974 975 /// InstructionSelectBasicBlock - This callback is invoked by 976 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 977 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 978 979 virtual const char *getPassName() const { 980 return "SPARC DAG->DAG Pattern Instruction Selection"; 981 } 982 983 // Include the pieces autogenerated from the target description. 984#include "SparcGenDAGISel.inc" 985}; 986} // end anonymous namespace 987 988/// InstructionSelectBasicBlock - This callback is invoked by 989/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 990void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 991 DEBUG(BB->dump()); 992 993 // Select target instructions for the DAG. 994 DAG.setRoot(SelectRoot(DAG.getRoot())); 995 DAG.RemoveDeadNodes(); 996 997 // Emit machine code to BB. 998 ScheduleAndEmitDAG(DAG); 999} 1000 1001bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 1002 SDOperand &Offset) { 1003 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1004 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1005 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1006 return true; 1007 } 1008 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1009 Addr.getOpcode() == ISD::TargetGlobalAddress) 1010 return false; // direct calls. 1011 1012 if (Addr.getOpcode() == ISD::ADD) { 1013 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1014 if (Predicate_simm13(CN)) { 1015 if (FrameIndexSDNode *FIN = 1016 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1017 // Constant offset from frame ref. 1018 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1019 } else { 1020 Base = Addr.getOperand(0); 1021 } 1022 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1023 return true; 1024 } 1025 } 1026 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1027 Base = Addr.getOperand(1); 1028 Offset = Addr.getOperand(0).getOperand(0); 1029 return true; 1030 } 1031 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1032 Base = Addr.getOperand(0); 1033 Offset = Addr.getOperand(1).getOperand(0); 1034 return true; 1035 } 1036 } 1037 Base = Addr; 1038 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1039 return true; 1040} 1041 1042bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 1043 SDOperand &R2) { 1044 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1045 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1046 Addr.getOpcode() == ISD::TargetGlobalAddress) 1047 return false; // direct calls. 1048 1049 if (Addr.getOpcode() == ISD::ADD) { 1050 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1051 Predicate_simm13(Addr.getOperand(1).Val)) 1052 return false; // Let the reg+imm pattern catch this! 1053 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1054 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1055 return false; // Let the reg+imm pattern catch this! 1056 R1 = Addr.getOperand(0); 1057 R2 = Addr.getOperand(1); 1058 return true; 1059 } 1060 1061 R1 = Addr; 1062 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1063 return true; 1064} 1065 1066void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { 1067 SDNode *N = Op.Val; 1068 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1069 N->getOpcode() < SPISD::FIRST_NUMBER) { 1070 Result = Op; 1071 return; // Already selected. 1072 } 1073 1074 switch (N->getOpcode()) { 1075 default: break; 1076 case ISD::SDIV: 1077 case ISD::UDIV: { 1078 // FIXME: should use a custom expander to expose the SRA to the dag. 1079 SDOperand DivLHS, DivRHS; 1080 AddToQueue(DivLHS, N->getOperand(0)); 1081 AddToQueue(DivRHS, N->getOperand(1)); 1082 1083 // Set the Y register to the high-part. 1084 SDOperand TopPart; 1085 if (N->getOpcode() == ISD::SDIV) { 1086 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1087 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1088 } else { 1089 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1090 } 1091 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1092 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1093 1094 // FIXME: Handle div by immediate. 1095 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1096 Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 1097 return; 1098 } 1099 case ISD::MULHU: 1100 case ISD::MULHS: { 1101 // FIXME: Handle mul by immediate. 1102 SDOperand MulLHS, MulRHS; 1103 AddToQueue(MulLHS, N->getOperand(0)); 1104 AddToQueue(MulRHS, N->getOperand(1)); 1105 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1106 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1107 MulLHS, MulRHS); 1108 // The high part is in the Y register. 1109 Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1110 return; 1111 } 1112 } 1113 1114 SelectCode(Result, Op); 1115} 1116 1117 1118/// createSparcISelDag - This pass converts a legalized DAG into a 1119/// SPARC-specific DAG, ready for instruction scheduling. 1120/// 1121FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1122 return new SparcDAGToDAGISel(TM); 1123} 1124