SparcISelDAGToDAG.cpp revision c26017a4ae14ec63bc99831dd3edbb0362f56d06
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27#include <set> 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// TargetLowering Implementation 32//===----------------------------------------------------------------------===// 33 34namespace SPISD { 35 enum { 36 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 37 CMPICC, // Compare two GPR operands, set icc. 38 CMPFCC, // Compare two FP operands, set fcc. 39 BRICC, // Branch to dest on icc condition 40 BRFCC, // Branch to dest on fcc condition 41 SELECT_ICC, // Select between two values using the current ICC flags. 42 SELECT_FCC, // Select between two values using the current FCC flags. 43 44 Hi, Lo, // Hi/Lo operations, typically on a global address. 45 46 FTOI, // FP to Int within a FP register. 47 ITOF, // Int to FP within a FP register. 48 49 CALL, // A call instruction. 50 RET_FLAG, // Return with a flag operand. 51 }; 52} 53 54/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 55/// condition. 56static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 57 switch (CC) { 58 default: assert(0 && "Unknown integer condition code!"); 59 case ISD::SETEQ: return SPCC::ICC_E; 60 case ISD::SETNE: return SPCC::ICC_NE; 61 case ISD::SETLT: return SPCC::ICC_L; 62 case ISD::SETGT: return SPCC::ICC_G; 63 case ISD::SETLE: return SPCC::ICC_LE; 64 case ISD::SETGE: return SPCC::ICC_GE; 65 case ISD::SETULT: return SPCC::ICC_CS; 66 case ISD::SETULE: return SPCC::ICC_LEU; 67 case ISD::SETUGT: return SPCC::ICC_GU; 68 case ISD::SETUGE: return SPCC::ICC_CC; 69 } 70} 71 72/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 73/// FCC condition. 74static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 75 switch (CC) { 76 default: assert(0 && "Unknown fp condition code!"); 77 case ISD::SETEQ: return SPCC::FCC_E; 78 case ISD::SETNE: return SPCC::FCC_NE; 79 case ISD::SETLT: return SPCC::FCC_L; 80 case ISD::SETGT: return SPCC::FCC_G; 81 case ISD::SETLE: return SPCC::FCC_LE; 82 case ISD::SETGE: return SPCC::FCC_GE; 83 case ISD::SETULT: return SPCC::FCC_UL; 84 case ISD::SETULE: return SPCC::FCC_ULE; 85 case ISD::SETUGT: return SPCC::FCC_UG; 86 case ISD::SETUGE: return SPCC::FCC_UGE; 87 case ISD::SETUO: return SPCC::FCC_U; 88 case ISD::SETO: return SPCC::FCC_O; 89 case ISD::SETONE: return SPCC::FCC_LG; 90 case ISD::SETUEQ: return SPCC::FCC_UE; 91 } 92} 93 94namespace { 95 class SparcTargetLowering : public TargetLowering { 96 int VarArgsFrameOffset; // Frame offset to start of varargs area. 97 public: 98 SparcTargetLowering(TargetMachine &TM); 99 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 100 101 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 102 /// be zero. Op is expected to be a target specific node. Used by DAG 103 /// combiner. 104 virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op, 105 uint64_t Mask) const; 106 107 virtual std::vector<SDOperand> 108 LowerArguments(Function &F, SelectionDAG &DAG); 109 virtual std::pair<SDOperand, SDOperand> 110 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 111 unsigned CC, 112 bool isTailCall, SDOperand Callee, ArgListTy &Args, 113 SelectionDAG &DAG); 114 virtual std::pair<SDOperand, SDOperand> 115 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 116 SelectionDAG &DAG); 117 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 118 MachineBasicBlock *MBB); 119 120 virtual const char *getTargetNodeName(unsigned Opcode) const; 121 }; 122} 123 124SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 125 : TargetLowering(TM) { 126 127 // Set up the register classes. 128 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 129 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 130 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 131 132 // Custom legalize GlobalAddress nodes into LO/HI parts. 133 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 134 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 135 136 // Sparc doesn't have sext_inreg, replace them with shl/sra 137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 140 141 // Sparc has no REM operation. 142 setOperationAction(ISD::UREM, MVT::i32, Expand); 143 setOperationAction(ISD::SREM, MVT::i32, Expand); 144 145 // Custom expand fp<->sint 146 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 147 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 148 149 // Expand fp<->uint 150 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 151 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 152 153 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 154 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 155 156 // Turn FP extload into load/fextend 157 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 158 159 // Sparc has no select or setcc: expand to SELECT_CC. 160 setOperationAction(ISD::SELECT, MVT::i32, Expand); 161 setOperationAction(ISD::SELECT, MVT::f32, Expand); 162 setOperationAction(ISD::SELECT, MVT::f64, Expand); 163 setOperationAction(ISD::SETCC, MVT::i32, Expand); 164 setOperationAction(ISD::SETCC, MVT::f32, Expand); 165 setOperationAction(ISD::SETCC, MVT::f64, Expand); 166 167 // Sparc doesn't have BRCOND either, it has BR_CC. 168 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 169 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 170 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 171 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 172 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 173 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 174 175 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 176 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 177 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 178 179 // SPARC has no intrinsics for these particular operations. 180 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 181 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 182 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 183 184 setOperationAction(ISD::FSIN , MVT::f64, Expand); 185 setOperationAction(ISD::FCOS , MVT::f64, Expand); 186 setOperationAction(ISD::FSIN , MVT::f32, Expand); 187 setOperationAction(ISD::FCOS , MVT::f32, Expand); 188 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 189 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 190 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 191 setOperationAction(ISD::ROTL , MVT::i32, Expand); 192 setOperationAction(ISD::ROTR , MVT::i32, Expand); 193 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 194 195 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 196 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 197 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 198 199 // We don't have line number support yet. 200 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 201 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 202 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 203 204 // RET must be custom lowered, to meet ABI requirements 205 setOperationAction(ISD::RET , MVT::Other, Custom); 206 207 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 208 setOperationAction(ISD::VASTART , MVT::Other, Custom); 209 // VAARG needs to be lowered to not do unaligned accesses for doubles. 210 setOperationAction(ISD::VAARG , MVT::Other, Custom); 211 212 // Use the default implementation. 213 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 214 setOperationAction(ISD::VAEND , MVT::Other, Expand); 215 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 216 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 217 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 218 219 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 220 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 221 222 setStackPointerRegisterToSaveRestore(SP::O6); 223 224 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 225 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 226 } 227 228 computeRegisterProperties(); 229} 230 231const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 232 switch (Opcode) { 233 default: return 0; 234 case SPISD::CMPICC: return "SPISD::CMPICC"; 235 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 236 case SPISD::BRICC: return "SPISD::BRICC"; 237 case SPISD::BRFCC: return "SPISD::BRFCC"; 238 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 239 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 240 case SPISD::Hi: return "SPISD::Hi"; 241 case SPISD::Lo: return "SPISD::Lo"; 242 case SPISD::FTOI: return "SPISD::FTOI"; 243 case SPISD::ITOF: return "SPISD::ITOF"; 244 case SPISD::CALL: return "SPISD::CALL"; 245 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 246 } 247} 248 249/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 250/// be zero. Op is expected to be a target specific node. Used by DAG 251/// combiner. 252bool SparcTargetLowering:: 253isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const { 254 switch (Op.getOpcode()) { 255 default: return false; 256 case SPISD::SELECT_ICC: 257 case SPISD::SELECT_FCC: 258 assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!"); 259 // These operations are masked zero if both the left and the right are zero. 260 return MaskedValueIsZero(Op.getOperand(0), Mask) && 261 MaskedValueIsZero(Op.getOperand(1), Mask); 262 } 263} 264 265 266/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 267/// either one or two GPRs, including FP values. TODO: we should pass FP values 268/// in FP registers for fastcc functions. 269std::vector<SDOperand> 270SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 271 MachineFunction &MF = DAG.getMachineFunction(); 272 SSARegMap *RegMap = MF.getSSARegMap(); 273 std::vector<SDOperand> ArgValues; 274 275 static const unsigned ArgRegs[] = { 276 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 277 }; 278 279 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 280 unsigned ArgOffset = 68; 281 282 SDOperand Root = DAG.getRoot(); 283 std::vector<SDOperand> OutChains; 284 285 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 286 MVT::ValueType ObjectVT = getValueType(I->getType()); 287 288 switch (ObjectVT) { 289 default: assert(0 && "Unhandled argument type!"); 290 case MVT::i1: 291 case MVT::i8: 292 case MVT::i16: 293 case MVT::i32: 294 if (I->use_empty()) { // Argument is dead. 295 if (CurArgReg < ArgRegEnd) ++CurArgReg; 296 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 297 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 298 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 299 MF.addLiveIn(*CurArgReg++, VReg); 300 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 301 if (ObjectVT != MVT::i32) { 302 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 303 : ISD::AssertZext; 304 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 305 DAG.getValueType(ObjectVT)); 306 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 307 } 308 ArgValues.push_back(Arg); 309 } else { 310 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 311 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 312 SDOperand Load; 313 if (ObjectVT == MVT::i32) { 314 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 315 } else { 316 unsigned LoadOp = 317 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 318 319 // Sparc is big endian, so add an offset based on the ObjectVT. 320 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 321 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 322 DAG.getConstant(Offset, MVT::i32)); 323 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 324 DAG.getSrcValue(0), ObjectVT); 325 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 326 } 327 ArgValues.push_back(Load); 328 } 329 330 ArgOffset += 4; 331 break; 332 case MVT::f32: 333 if (I->use_empty()) { // Argument is dead. 334 if (CurArgReg < ArgRegEnd) ++CurArgReg; 335 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 336 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 337 // FP value is passed in an integer register. 338 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 339 MF.addLiveIn(*CurArgReg++, VReg); 340 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 341 342 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 343 ArgValues.push_back(Arg); 344 } else { 345 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 346 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 347 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); 348 ArgValues.push_back(Load); 349 } 350 ArgOffset += 4; 351 break; 352 353 case MVT::i64: 354 case MVT::f64: 355 if (I->use_empty()) { // Argument is dead. 356 if (CurArgReg < ArgRegEnd) ++CurArgReg; 357 if (CurArgReg < ArgRegEnd) ++CurArgReg; 358 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 359 } else if (/* FIXME: Apparently this isn't safe?? */ 360 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 361 ((CurArgReg-ArgRegs) & 1) == 0) { 362 // If this is a double argument and the whole thing lives on the stack, 363 // and the argument is aligned, load the double straight from the stack. 364 // We can't do a load in cases like void foo([6ints], int,double), 365 // because the double wouldn't be aligned! 366 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 367 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 368 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 369 DAG.getSrcValue(0))); 370 } else { 371 SDOperand HiVal; 372 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 373 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 374 MF.addLiveIn(*CurArgReg++, VRegHi); 375 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 376 } else { 377 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 378 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 379 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 380 } 381 382 SDOperand LoVal; 383 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 384 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 385 MF.addLiveIn(*CurArgReg++, VRegLo); 386 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 387 } else { 388 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 389 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 390 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 391 } 392 393 // Compose the two halves together into an i64 unit. 394 SDOperand WholeValue = 395 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 396 397 // If we want a double, do a bit convert. 398 if (ObjectVT == MVT::f64) 399 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 400 401 ArgValues.push_back(WholeValue); 402 } 403 ArgOffset += 8; 404 break; 405 } 406 } 407 408 // Store remaining ArgRegs to the stack if this is a varargs function. 409 if (F.getFunctionType()->isVarArg()) { 410 // Remember the vararg offset for the va_start implementation. 411 VarArgsFrameOffset = ArgOffset; 412 413 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 414 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 415 MF.addLiveIn(*CurArgReg, VReg); 416 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 417 418 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 419 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 420 421 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 422 Arg, FIPtr, DAG.getSrcValue(0))); 423 ArgOffset += 4; 424 } 425 } 426 427 if (!OutChains.empty()) 428 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 429 430 // Finally, inform the code generator which regs we return values in. 431 switch (getValueType(F.getReturnType())) { 432 default: assert(0 && "Unknown type!"); 433 case MVT::isVoid: break; 434 case MVT::i1: 435 case MVT::i8: 436 case MVT::i16: 437 case MVT::i32: 438 MF.addLiveOut(SP::I0); 439 break; 440 case MVT::i64: 441 MF.addLiveOut(SP::I0); 442 MF.addLiveOut(SP::I1); 443 break; 444 case MVT::f32: 445 MF.addLiveOut(SP::F0); 446 break; 447 case MVT::f64: 448 MF.addLiveOut(SP::D0); 449 break; 450 } 451 452 return ArgValues; 453} 454 455std::pair<SDOperand, SDOperand> 456SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 457 bool isVarArg, unsigned CC, 458 bool isTailCall, SDOperand Callee, 459 ArgListTy &Args, SelectionDAG &DAG) { 460 MachineFunction &MF = DAG.getMachineFunction(); 461 // Count the size of the outgoing arguments. 462 unsigned ArgsSize = 0; 463 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 464 switch (getValueType(Args[i].second)) { 465 default: assert(0 && "Unknown value type!"); 466 case MVT::i1: 467 case MVT::i8: 468 case MVT::i16: 469 case MVT::i32: 470 case MVT::f32: 471 ArgsSize += 4; 472 break; 473 case MVT::i64: 474 case MVT::f64: 475 ArgsSize += 8; 476 break; 477 } 478 } 479 if (ArgsSize > 4*6) 480 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 481 else 482 ArgsSize = 0; 483 484 // Keep stack frames 8-byte aligned. 485 ArgsSize = (ArgsSize+7) & ~7; 486 487 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 488 DAG.getConstant(ArgsSize, getPointerTy())); 489 490 SDOperand StackPtr, NullSV; 491 std::vector<SDOperand> Stores; 492 std::vector<SDOperand> RegValuesToPass; 493 unsigned ArgOffset = 68; 494 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 495 SDOperand Val = Args[i].first; 496 MVT::ValueType ObjectVT = Val.getValueType(); 497 SDOperand ValToStore(0, 0); 498 unsigned ObjSize; 499 switch (ObjectVT) { 500 default: assert(0 && "Unhandled argument type!"); 501 case MVT::i1: 502 case MVT::i8: 503 case MVT::i16: 504 // Promote the integer to 32-bits. If the input type is signed, use a 505 // sign extend, otherwise use a zero extend. 506 if (Args[i].second->isSigned()) 507 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 508 else 509 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 510 // FALL THROUGH 511 case MVT::i32: 512 ObjSize = 4; 513 514 if (RegValuesToPass.size() >= 6) { 515 ValToStore = Val; 516 } else { 517 RegValuesToPass.push_back(Val); 518 } 519 break; 520 case MVT::f32: 521 ObjSize = 4; 522 if (RegValuesToPass.size() >= 6) { 523 ValToStore = Val; 524 } else { 525 // Convert this to a FP value in an int reg. 526 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 527 RegValuesToPass.push_back(Val); 528 } 529 break; 530 case MVT::f64: 531 ObjSize = 8; 532 // If we can store this directly into the outgoing slot, do so. We can 533 // do this when all ArgRegs are used and if the outgoing slot is aligned. 534 // FIXME: McGill/misr fails with this. 535 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 536 ValToStore = Val; 537 break; 538 } 539 540 // Otherwise, convert this to a FP value in int regs. 541 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 542 // FALL THROUGH 543 case MVT::i64: 544 ObjSize = 8; 545 if (RegValuesToPass.size() >= 6) { 546 ValToStore = Val; // Whole thing is passed in memory. 547 break; 548 } 549 550 // Split the value into top and bottom part. Top part goes in a reg. 551 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 552 DAG.getConstant(1, MVT::i32)); 553 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 554 DAG.getConstant(0, MVT::i32)); 555 RegValuesToPass.push_back(Hi); 556 557 if (RegValuesToPass.size() >= 6) { 558 ValToStore = Lo; 559 ArgOffset += 4; 560 ObjSize = 4; 561 } else { 562 RegValuesToPass.push_back(Lo); 563 } 564 break; 565 } 566 567 if (ValToStore.Val) { 568 if (!StackPtr.Val) { 569 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 570 NullSV = DAG.getSrcValue(NULL); 571 } 572 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 573 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 574 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 575 ValToStore, PtrOff, NullSV)); 576 } 577 ArgOffset += ObjSize; 578 } 579 580 // Emit all stores, make sure the occur before any copies into physregs. 581 if (!Stores.empty()) 582 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 583 584 static const unsigned ArgRegs[] = { 585 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 586 }; 587 588 // Build a sequence of copy-to-reg nodes chained together with token chain 589 // and flag operands which copy the outgoing args into O[0-5]. 590 SDOperand InFlag; 591 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 592 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 593 InFlag = Chain.getValue(1); 594 } 595 596 // If the callee is a GlobalAddress node (quite common, every direct call is) 597 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 598 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 599 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 600 601 std::vector<MVT::ValueType> NodeTys; 602 NodeTys.push_back(MVT::Other); // Returns a chain 603 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 604 std::vector<SDOperand> Ops; 605 Ops.push_back(Chain); 606 Ops.push_back(Callee); 607 if (InFlag.Val) 608 Ops.push_back(InFlag); 609 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops); 610 InFlag = Chain.getValue(1); 611 612 MVT::ValueType RetTyVT = getValueType(RetTy); 613 SDOperand RetVal; 614 if (RetTyVT != MVT::isVoid) { 615 switch (RetTyVT) { 616 default: assert(0 && "Unknown value type to return!"); 617 case MVT::i1: 618 case MVT::i8: 619 case MVT::i16: 620 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 621 Chain = RetVal.getValue(1); 622 623 // Add a note to keep track of whether it is sign or zero extended. 624 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 625 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 626 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 627 break; 628 case MVT::i32: 629 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 630 Chain = RetVal.getValue(1); 631 break; 632 case MVT::f32: 633 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 634 Chain = RetVal.getValue(1); 635 break; 636 case MVT::f64: 637 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 638 Chain = RetVal.getValue(1); 639 break; 640 case MVT::i64: 641 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 642 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 643 Lo.getValue(2)); 644 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 645 Chain = Hi.getValue(1); 646 break; 647 } 648 } 649 650 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 651 DAG.getConstant(ArgsSize, getPointerTy())); 652 653 return std::make_pair(RetVal, Chain); 654} 655 656std::pair<SDOperand, SDOperand> SparcTargetLowering:: 657LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 658 SelectionDAG &DAG) { 659 assert(0 && "Unimp"); 660 abort(); 661} 662 663// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 664// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 665static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 666 ISD::CondCode CC, unsigned &SPCC) { 667 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 668 CC == ISD::SETNE && 669 ((LHS.getOpcode() == SPISD::SELECT_ICC && 670 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 671 (LHS.getOpcode() == SPISD::SELECT_FCC && 672 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 673 isa<ConstantSDNode>(LHS.getOperand(0)) && 674 isa<ConstantSDNode>(LHS.getOperand(1)) && 675 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 676 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 677 SDOperand CMPCC = LHS.getOperand(3); 678 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 679 LHS = CMPCC.getOperand(0); 680 RHS = CMPCC.getOperand(1); 681 } 682} 683 684 685SDOperand SparcTargetLowering:: 686LowerOperation(SDOperand Op, SelectionDAG &DAG) { 687 switch (Op.getOpcode()) { 688 default: assert(0 && "Should not custom lower this!"); 689 case ISD::GlobalAddress: { 690 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 691 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 692 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 693 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 694 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 695 } 696 case ISD::ConstantPool: { 697 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 698 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 699 cast<ConstantPoolSDNode>(Op)->getAlignment()); 700 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 701 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 702 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 703 } 704 case ISD::FP_TO_SINT: 705 // Convert the fp value to integer in an FP register. 706 assert(Op.getValueType() == MVT::i32); 707 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 708 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 709 case ISD::SINT_TO_FP: { 710 assert(Op.getOperand(0).getValueType() == MVT::i32); 711 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 712 // Convert the int value to FP in an FP register. 713 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 714 } 715 case ISD::BR_CC: { 716 SDOperand Chain = Op.getOperand(0); 717 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 718 SDOperand LHS = Op.getOperand(2); 719 SDOperand RHS = Op.getOperand(3); 720 SDOperand Dest = Op.getOperand(4); 721 unsigned Opc, SPCC = ~0U; 722 723 // If this is a br_cc of a "setcc", and if the setcc got lowered into 724 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 725 LookThroughSetCC(LHS, RHS, CC, SPCC); 726 727 // Get the condition flag. 728 SDOperand CompareFlag; 729 if (LHS.getValueType() == MVT::i32) { 730 std::vector<MVT::ValueType> VTs; 731 VTs.push_back(MVT::i32); 732 VTs.push_back(MVT::Flag); 733 std::vector<SDOperand> Ops; 734 Ops.push_back(LHS); 735 Ops.push_back(RHS); 736 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1); 737 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 738 Opc = SPISD::BRICC; 739 } else { 740 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 741 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 742 Opc = SPISD::BRFCC; 743 } 744 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 745 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 746 } 747 case ISD::SELECT_CC: { 748 SDOperand LHS = Op.getOperand(0); 749 SDOperand RHS = Op.getOperand(1); 750 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 751 SDOperand TrueVal = Op.getOperand(2); 752 SDOperand FalseVal = Op.getOperand(3); 753 unsigned Opc, SPCC = ~0U; 754 755 // If this is a select_cc of a "setcc", and if the setcc got lowered into 756 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 757 LookThroughSetCC(LHS, RHS, CC, SPCC); 758 759 SDOperand CompareFlag; 760 if (LHS.getValueType() == MVT::i32) { 761 std::vector<MVT::ValueType> VTs; 762 VTs.push_back(LHS.getValueType()); // subcc returns a value 763 VTs.push_back(MVT::Flag); 764 std::vector<SDOperand> Ops; 765 Ops.push_back(LHS); 766 Ops.push_back(RHS); 767 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1); 768 Opc = SPISD::SELECT_ICC; 769 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 770 } else { 771 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 772 Opc = SPISD::SELECT_FCC; 773 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 774 } 775 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 776 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 777 } 778 case ISD::VASTART: { 779 // vastart just stores the address of the VarArgsFrameIndex slot into the 780 // memory location argument. 781 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 782 DAG.getRegister(SP::I6, MVT::i32), 783 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 784 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 785 Op.getOperand(1), Op.getOperand(2)); 786 } 787 case ISD::VAARG: { 788 SDNode *Node = Op.Val; 789 MVT::ValueType VT = Node->getValueType(0); 790 SDOperand InChain = Node->getOperand(0); 791 SDOperand VAListPtr = Node->getOperand(1); 792 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 793 Node->getOperand(2)); 794 // Increment the pointer, VAList, to the next vaarg 795 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 796 DAG.getConstant(MVT::getSizeInBits(VT)/8, 797 getPointerTy())); 798 // Store the incremented VAList to the legalized pointer 799 InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr, 800 VAListPtr, Node->getOperand(2)); 801 // Load the actual argument out of the pointer VAList, unless this is an 802 // f64 load. 803 if (VT != MVT::f64) { 804 return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0)); 805 } else { 806 // Otherwise, load it as i64, then do a bitconvert. 807 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0)); 808 std::vector<MVT::ValueType> Tys; 809 Tys.push_back(MVT::f64); 810 Tys.push_back(MVT::Other); 811 std::vector<SDOperand> Ops; 812 // Bit-Convert the value to f64. 813 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V)); 814 Ops.push_back(V.getValue(1)); 815 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 816 } 817 } 818 case ISD::RET: { 819 SDOperand Copy; 820 821 switch(Op.getNumOperands()) { 822 default: 823 assert(0 && "Do not know how to return this many arguments!"); 824 abort(); 825 case 1: 826 return SDOperand(); // ret void is legal 827 case 2: { 828 unsigned ArgReg; 829 switch(Op.getOperand(1).getValueType()) { 830 default: assert(0 && "Unknown type to return!"); 831 case MVT::i32: ArgReg = SP::I0; break; 832 case MVT::f32: ArgReg = SP::F0; break; 833 case MVT::f64: ArgReg = SP::D0; break; 834 } 835 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 836 SDOperand()); 837 break; 838 } 839 case 3: 840 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2), 841 SDOperand()); 842 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 843 break; 844 } 845 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 846 } 847 } 848} 849 850MachineBasicBlock * 851SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 852 MachineBasicBlock *BB) { 853 unsigned BROpcode; 854 unsigned CC; 855 // Figure out the conditional branch opcode to use for this select_cc. 856 switch (MI->getOpcode()) { 857 default: assert(0 && "Unknown SELECT_CC!"); 858 case SP::SELECT_CC_Int_ICC: 859 case SP::SELECT_CC_FP_ICC: 860 case SP::SELECT_CC_DFP_ICC: 861 BROpcode = SP::BCOND; 862 break; 863 case SP::SELECT_CC_Int_FCC: 864 case SP::SELECT_CC_FP_FCC: 865 case SP::SELECT_CC_DFP_FCC: 866 BROpcode = SP::FBCOND; 867 break; 868 } 869 870 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 871 872 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 873 // control-flow pattern. The incoming instruction knows the destination vreg 874 // to set, the condition code register to branch on, the true/false values to 875 // select between, and a branch opcode to use. 876 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 877 ilist<MachineBasicBlock>::iterator It = BB; 878 ++It; 879 880 // thisMBB: 881 // ... 882 // TrueVal = ... 883 // [f]bCC copy1MBB 884 // fallthrough --> copy0MBB 885 MachineBasicBlock *thisMBB = BB; 886 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 887 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 888 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC); 889 MachineFunction *F = BB->getParent(); 890 F->getBasicBlockList().insert(It, copy0MBB); 891 F->getBasicBlockList().insert(It, sinkMBB); 892 // Update machine-CFG edges 893 BB->addSuccessor(copy0MBB); 894 BB->addSuccessor(sinkMBB); 895 896 // copy0MBB: 897 // %FalseValue = ... 898 // # fallthrough to sinkMBB 899 BB = copy0MBB; 900 901 // Update machine-CFG edges 902 BB->addSuccessor(sinkMBB); 903 904 // sinkMBB: 905 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 906 // ... 907 BB = sinkMBB; 908 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg()) 909 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 910 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 911 912 delete MI; // The pseudo instruction is gone now. 913 return BB; 914} 915 916//===----------------------------------------------------------------------===// 917// Instruction Selector Implementation 918//===----------------------------------------------------------------------===// 919 920//===--------------------------------------------------------------------===// 921/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 922/// instructions for SelectionDAG operations. 923/// 924namespace { 925class SparcDAGToDAGISel : public SelectionDAGISel { 926 SparcTargetLowering Lowering; 927 928 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 929 /// make the right decision when generating code for different targets. 930 const SparcSubtarget &Subtarget; 931public: 932 SparcDAGToDAGISel(TargetMachine &TM) 933 : SelectionDAGISel(Lowering), Lowering(TM), 934 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 935 } 936 937 SDOperand Select(SDOperand Op); 938 939 // Complex Pattern Selectors. 940 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 941 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 942 943 /// InstructionSelectBasicBlock - This callback is invoked by 944 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 945 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 946 947 virtual const char *getPassName() const { 948 return "SPARC DAG->DAG Pattern Instruction Selection"; 949 } 950 951 // Include the pieces autogenerated from the target description. 952#include "SparcGenDAGISel.inc" 953}; 954} // end anonymous namespace 955 956/// InstructionSelectBasicBlock - This callback is invoked by 957/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 958void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 959 DEBUG(BB->dump()); 960 961 // Select target instructions for the DAG. 962 DAG.setRoot(SelectRoot(DAG.getRoot())); 963 CodeGenMap.clear(); 964 DAG.RemoveDeadNodes(); 965 966 // Emit machine code to BB. 967 ScheduleAndEmitDAG(DAG); 968} 969 970bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 971 SDOperand &Offset) { 972 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 973 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 974 Offset = CurDAG->getTargetConstant(0, MVT::i32); 975 return true; 976 } 977 978 if (Addr.getOpcode() == ISD::ADD) { 979 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 980 if (Predicate_simm13(CN)) { 981 if (FrameIndexSDNode *FIN = 982 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 983 // Constant offset from frame ref. 984 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 985 } else { 986 Base = Addr.getOperand(0); 987 } 988 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 989 return true; 990 } 991 } 992 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 993 Base = Addr.getOperand(1); 994 Offset = Addr.getOperand(0).getOperand(0); 995 return true; 996 } 997 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 998 Base = Addr.getOperand(0); 999 Offset = Addr.getOperand(1).getOperand(0); 1000 return true; 1001 } 1002 } 1003 Base = Addr; 1004 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1005 return true; 1006} 1007 1008bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 1009 SDOperand &R2) { 1010 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1011 if (Addr.getOpcode() == ISD::ADD) { 1012 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1013 Predicate_simm13(Addr.getOperand(1).Val)) 1014 return false; // Let the reg+imm pattern catch this! 1015 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1016 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1017 return false; // Let the reg+imm pattern catch this! 1018 R1 = Addr.getOperand(0); 1019 R2 = Addr.getOperand(1); 1020 return true; 1021 } 1022 1023 R1 = Addr; 1024 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1025 return true; 1026} 1027 1028SDOperand SparcDAGToDAGISel::Select(SDOperand Op) { 1029 SDNode *N = Op.Val; 1030 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1031 N->getOpcode() < SPISD::FIRST_NUMBER) 1032 return Op; // Already selected. 1033 // If this has already been converted, use it. 1034 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 1035 if (CGMI != CodeGenMap.end()) return CGMI->second; 1036 1037 switch (N->getOpcode()) { 1038 default: break; 1039 case ISD::FrameIndex: { 1040 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 1041 if (N->hasOneUse()) 1042 return CurDAG->SelectNodeTo(N, SP::ADDri, MVT::i32, 1043 CurDAG->getTargetFrameIndex(FI, MVT::i32), 1044 CurDAG->getTargetConstant(0, MVT::i32)); 1045 return CodeGenMap[Op] = 1046 CurDAG->getTargetNode(SP::ADDri, MVT::i32, 1047 CurDAG->getTargetFrameIndex(FI, MVT::i32), 1048 CurDAG->getTargetConstant(0, MVT::i32)); 1049 } 1050 case ISD::ADD_PARTS: { 1051 SDOperand LHSL = Select(N->getOperand(0)); 1052 SDOperand LHSH = Select(N->getOperand(1)); 1053 SDOperand RHSL = Select(N->getOperand(2)); 1054 SDOperand RHSH = Select(N->getOperand(3)); 1055 // FIXME, handle immediate RHS. 1056 SDOperand Low = CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag, 1057 LHSL, RHSL); 1058 SDOperand Hi = CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, 1059 Low.getValue(1)); 1060 CodeGenMap[SDOperand(N, 0)] = Low; 1061 CodeGenMap[SDOperand(N, 1)] = Hi; 1062 return Op.ResNo ? Hi : Low; 1063 } 1064 case ISD::SUB_PARTS: { 1065 SDOperand LHSL = Select(N->getOperand(0)); 1066 SDOperand LHSH = Select(N->getOperand(1)); 1067 SDOperand RHSL = Select(N->getOperand(2)); 1068 SDOperand RHSH = Select(N->getOperand(3)); 1069 // FIXME, handle immediate RHS. 1070 SDOperand Low = CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag, 1071 LHSL, RHSL); 1072 SDOperand Hi = CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, 1073 Low.getValue(1)); 1074 CodeGenMap[SDOperand(N, 0)] = Low; 1075 CodeGenMap[SDOperand(N, 1)] = Hi; 1076 return Op.ResNo ? Hi : Low; 1077 } 1078 case ISD::SDIV: 1079 case ISD::UDIV: { 1080 // FIXME: should use a custom expander to expose the SRA to the dag. 1081 SDOperand DivLHS = Select(N->getOperand(0)); 1082 SDOperand DivRHS = Select(N->getOperand(1)); 1083 1084 // Set the Y register to the high-part. 1085 SDOperand TopPart; 1086 if (N->getOpcode() == ISD::SDIV) { 1087 TopPart = CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1088 CurDAG->getTargetConstant(31, MVT::i32)); 1089 } else { 1090 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1091 } 1092 TopPart = CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1093 CurDAG->getRegister(SP::G0, MVT::i32)); 1094 1095 // FIXME: Handle div by immediate. 1096 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1097 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 1098 } 1099 case ISD::MULHU: 1100 case ISD::MULHS: { 1101 // FIXME: Handle mul by immediate. 1102 SDOperand MulLHS = Select(N->getOperand(0)); 1103 SDOperand MulRHS = Select(N->getOperand(1)); 1104 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1105 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1106 MulLHS, MulRHS); 1107 // The high part is in the Y register. 1108 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, Mul.getValue(1)); 1109 } 1110 case SPISD::CALL: 1111 // FIXME: This is a workaround for a bug in tblgen. 1112 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 1113 // Emits: (CALL:void (tglobaladdr:i32):$dst) 1114 // Pattern complexity = 2 cost = 1 1115 SDOperand N1 = N->getOperand(1); 1116 if (N1.getOpcode() != ISD::TargetGlobalAddress && 1117 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 1118 SDOperand InFlag = SDOperand(0, 0); 1119 SDOperand Chain = N->getOperand(0); 1120 SDOperand Tmp0 = N1; 1121 Chain = Select(Chain); 1122 SDOperand Result; 1123 if (N->getNumOperands() == 3) { 1124 InFlag = Select(N->getOperand(2)); 1125 Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, 1126 Chain, InFlag); 1127 } else { 1128 Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, 1129 Chain); 1130 } 1131 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1132 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1133 return Result.getValue(Op.ResNo); 1134 } 1135 P47Fail:; 1136 1137 } 1138 1139 return SelectCode(Op); 1140} 1141 1142 1143/// createSparcISelDag - This pass converts a legalized DAG into a 1144/// SPARC-specific DAG, ready for instruction scheduling. 1145/// 1146FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1147 return new SparcDAGToDAGISel(TM); 1148} 1149