SparcISelDAGToDAG.cpp revision c35497fc2a8b984dbacede5b75b7be74c6756948
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/CodeGen/SSARegMap.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Debug.h" 27#include <iostream> 28#include <queue> 29#include <set> 30using namespace llvm; 31 32//===----------------------------------------------------------------------===// 33// TargetLowering Implementation 34//===----------------------------------------------------------------------===// 35 36namespace SPISD { 37 enum { 38 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 39 CMPICC, // Compare two GPR operands, set icc. 40 CMPFCC, // Compare two FP operands, set fcc. 41 BRICC, // Branch to dest on icc condition 42 BRFCC, // Branch to dest on fcc condition 43 SELECT_ICC, // Select between two values using the current ICC flags. 44 SELECT_FCC, // Select between two values using the current FCC flags. 45 46 Hi, Lo, // Hi/Lo operations, typically on a global address. 47 48 FTOI, // FP to Int within a FP register. 49 ITOF, // Int to FP within a FP register. 50 51 CALL, // A call instruction. 52 RET_FLAG // Return with a flag operand. 53 }; 54} 55 56/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 57/// condition. 58static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 59 switch (CC) { 60 default: assert(0 && "Unknown integer condition code!"); 61 case ISD::SETEQ: return SPCC::ICC_E; 62 case ISD::SETNE: return SPCC::ICC_NE; 63 case ISD::SETLT: return SPCC::ICC_L; 64 case ISD::SETGT: return SPCC::ICC_G; 65 case ISD::SETLE: return SPCC::ICC_LE; 66 case ISD::SETGE: return SPCC::ICC_GE; 67 case ISD::SETULT: return SPCC::ICC_CS; 68 case ISD::SETULE: return SPCC::ICC_LEU; 69 case ISD::SETUGT: return SPCC::ICC_GU; 70 case ISD::SETUGE: return SPCC::ICC_CC; 71 } 72} 73 74/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 75/// FCC condition. 76static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 77 switch (CC) { 78 default: assert(0 && "Unknown fp condition code!"); 79 case ISD::SETEQ: 80 case ISD::SETOEQ: return SPCC::FCC_E; 81 case ISD::SETNE: 82 case ISD::SETUNE: return SPCC::FCC_NE; 83 case ISD::SETLT: 84 case ISD::SETOLT: return SPCC::FCC_L; 85 case ISD::SETGT: 86 case ISD::SETOGT: return SPCC::FCC_G; 87 case ISD::SETLE: 88 case ISD::SETOLE: return SPCC::FCC_LE; 89 case ISD::SETGE: 90 case ISD::SETOGE: return SPCC::FCC_GE; 91 case ISD::SETULT: return SPCC::FCC_UL; 92 case ISD::SETULE: return SPCC::FCC_ULE; 93 case ISD::SETUGT: return SPCC::FCC_UG; 94 case ISD::SETUGE: return SPCC::FCC_UGE; 95 case ISD::SETUO: return SPCC::FCC_U; 96 case ISD::SETO: return SPCC::FCC_O; 97 case ISD::SETONE: return SPCC::FCC_LG; 98 case ISD::SETUEQ: return SPCC::FCC_UE; 99 } 100} 101 102namespace { 103 class SparcTargetLowering : public TargetLowering { 104 int VarArgsFrameOffset; // Frame offset to start of varargs area. 105 public: 106 SparcTargetLowering(TargetMachine &TM); 107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 108 109 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 110 /// in Mask are known to be either zero or one and return them in the 111 /// KnownZero/KnownOne bitsets. 112 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 113 uint64_t Mask, 114 uint64_t &KnownZero, 115 uint64_t &KnownOne, 116 unsigned Depth = 0) const; 117 118 virtual std::vector<SDOperand> 119 LowerArguments(Function &F, SelectionDAG &DAG); 120 virtual std::pair<SDOperand, SDOperand> 121 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 122 unsigned CC, 123 bool isTailCall, SDOperand Callee, ArgListTy &Args, 124 SelectionDAG &DAG); 125 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 126 MachineBasicBlock *MBB); 127 128 virtual const char *getTargetNodeName(unsigned Opcode) const; 129 }; 130} 131 132SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 133 : TargetLowering(TM) { 134 135 // Set up the register classes. 136 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 137 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 138 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 139 140 // Turn FP extload into load/fextend 141 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 142 143 // Custom legalize GlobalAddress nodes into LO/HI parts. 144 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 145 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 146 147 // Sparc doesn't have sext_inreg, replace them with shl/sra 148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 151 152 // Sparc has no REM operation. 153 setOperationAction(ISD::UREM, MVT::i32, Expand); 154 setOperationAction(ISD::SREM, MVT::i32, Expand); 155 156 // Custom expand fp<->sint 157 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 158 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 159 160 // Expand fp<->uint 161 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 162 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 163 164 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 165 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 166 167 // Sparc has no select or setcc: expand to SELECT_CC. 168 setOperationAction(ISD::SELECT, MVT::i32, Expand); 169 setOperationAction(ISD::SELECT, MVT::f32, Expand); 170 setOperationAction(ISD::SELECT, MVT::f64, Expand); 171 setOperationAction(ISD::SETCC, MVT::i32, Expand); 172 setOperationAction(ISD::SETCC, MVT::f32, Expand); 173 setOperationAction(ISD::SETCC, MVT::f64, Expand); 174 175 // Sparc doesn't have BRCOND either, it has BR_CC. 176 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 177 setOperationAction(ISD::BRIND, MVT::Other, Expand); 178 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 179 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 180 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 181 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 182 183 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 184 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 185 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 186 187 // SPARC has no intrinsics for these particular operations. 188 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 189 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 190 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 191 192 setOperationAction(ISD::FSIN , MVT::f64, Expand); 193 setOperationAction(ISD::FCOS , MVT::f64, Expand); 194 setOperationAction(ISD::FSIN , MVT::f32, Expand); 195 setOperationAction(ISD::FCOS , MVT::f32, Expand); 196 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 197 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 198 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 199 setOperationAction(ISD::ROTL , MVT::i32, Expand); 200 setOperationAction(ISD::ROTR , MVT::i32, Expand); 201 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 202 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 203 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 204 205 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 206 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 207 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 208 209 // We don't have line number support yet. 210 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 211 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 212 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 213 214 // RET must be custom lowered, to meet ABI requirements 215 setOperationAction(ISD::RET , MVT::Other, Custom); 216 217 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 218 setOperationAction(ISD::VASTART , MVT::Other, Custom); 219 // VAARG needs to be lowered to not do unaligned accesses for doubles. 220 setOperationAction(ISD::VAARG , MVT::Other, Custom); 221 222 // Use the default implementation. 223 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 224 setOperationAction(ISD::VAEND , MVT::Other, Expand); 225 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 226 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 227 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 228 229 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 230 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 231 232 setStackPointerRegisterToSaveRestore(SP::O6); 233 234 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 235 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 236 } 237 238 computeRegisterProperties(); 239} 240 241const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 242 switch (Opcode) { 243 default: return 0; 244 case SPISD::CMPICC: return "SPISD::CMPICC"; 245 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 246 case SPISD::BRICC: return "SPISD::BRICC"; 247 case SPISD::BRFCC: return "SPISD::BRFCC"; 248 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 249 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 250 case SPISD::Hi: return "SPISD::Hi"; 251 case SPISD::Lo: return "SPISD::Lo"; 252 case SPISD::FTOI: return "SPISD::FTOI"; 253 case SPISD::ITOF: return "SPISD::ITOF"; 254 case SPISD::CALL: return "SPISD::CALL"; 255 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 256 } 257} 258 259/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 260/// be zero. Op is expected to be a target specific node. Used by DAG 261/// combiner. 262void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 263 uint64_t Mask, 264 uint64_t &KnownZero, 265 uint64_t &KnownOne, 266 unsigned Depth) const { 267 uint64_t KnownZero2, KnownOne2; 268 KnownZero = KnownOne = 0; // Don't know anything. 269 270 switch (Op.getOpcode()) { 271 default: break; 272 case SPISD::SELECT_ICC: 273 case SPISD::SELECT_FCC: 274 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 275 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 276 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 277 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 278 279 // Only known if known in both the LHS and RHS. 280 KnownOne &= KnownOne2; 281 KnownZero &= KnownZero2; 282 break; 283 } 284} 285 286/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 287/// either one or two GPRs, including FP values. TODO: we should pass FP values 288/// in FP registers for fastcc functions. 289std::vector<SDOperand> 290SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 291 MachineFunction &MF = DAG.getMachineFunction(); 292 SSARegMap *RegMap = MF.getSSARegMap(); 293 std::vector<SDOperand> ArgValues; 294 295 static const unsigned ArgRegs[] = { 296 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 297 }; 298 299 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 300 unsigned ArgOffset = 68; 301 302 SDOperand Root = DAG.getRoot(); 303 std::vector<SDOperand> OutChains; 304 305 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 306 MVT::ValueType ObjectVT = getValueType(I->getType()); 307 308 switch (ObjectVT) { 309 default: assert(0 && "Unhandled argument type!"); 310 case MVT::i1: 311 case MVT::i8: 312 case MVT::i16: 313 case MVT::i32: 314 if (I->use_empty()) { // Argument is dead. 315 if (CurArgReg < ArgRegEnd) ++CurArgReg; 316 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 317 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 318 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 319 MF.addLiveIn(*CurArgReg++, VReg); 320 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 321 if (ObjectVT != MVT::i32) { 322 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 323 : ISD::AssertZext; 324 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 325 DAG.getValueType(ObjectVT)); 326 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 327 } 328 ArgValues.push_back(Arg); 329 } else { 330 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 331 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 332 SDOperand Load; 333 if (ObjectVT == MVT::i32) { 334 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 335 } else { 336 ISD::LoadExtType LoadOp = 337 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 338 339 // Sparc is big endian, so add an offset based on the ObjectVT. 340 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 341 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 342 DAG.getConstant(Offset, MVT::i32)); 343 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 344 NULL, 0, ObjectVT); 345 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 346 } 347 ArgValues.push_back(Load); 348 } 349 350 ArgOffset += 4; 351 break; 352 case MVT::f32: 353 if (I->use_empty()) { // Argument is dead. 354 if (CurArgReg < ArgRegEnd) ++CurArgReg; 355 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 356 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 357 // FP value is passed in an integer register. 358 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 359 MF.addLiveIn(*CurArgReg++, VReg); 360 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 361 362 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 363 ArgValues.push_back(Arg); 364 } else { 365 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 366 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 367 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 368 ArgValues.push_back(Load); 369 } 370 ArgOffset += 4; 371 break; 372 373 case MVT::i64: 374 case MVT::f64: 375 if (I->use_empty()) { // Argument is dead. 376 if (CurArgReg < ArgRegEnd) ++CurArgReg; 377 if (CurArgReg < ArgRegEnd) ++CurArgReg; 378 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 379 } else if (/* FIXME: Apparently this isn't safe?? */ 380 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 381 ((CurArgReg-ArgRegs) & 1) == 0) { 382 // If this is a double argument and the whole thing lives on the stack, 383 // and the argument is aligned, load the double straight from the stack. 384 // We can't do a load in cases like void foo([6ints], int,double), 385 // because the double wouldn't be aligned! 386 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 387 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 388 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 389 } else { 390 SDOperand HiVal; 391 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 392 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 393 MF.addLiveIn(*CurArgReg++, VRegHi); 394 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 395 } else { 396 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 397 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 398 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 399 } 400 401 SDOperand LoVal; 402 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 403 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 404 MF.addLiveIn(*CurArgReg++, VRegLo); 405 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 406 } else { 407 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 408 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 409 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 410 } 411 412 // Compose the two halves together into an i64 unit. 413 SDOperand WholeValue = 414 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 415 416 // If we want a double, do a bit convert. 417 if (ObjectVT == MVT::f64) 418 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 419 420 ArgValues.push_back(WholeValue); 421 } 422 ArgOffset += 8; 423 break; 424 } 425 } 426 427 // Store remaining ArgRegs to the stack if this is a varargs function. 428 if (F.getFunctionType()->isVarArg()) { 429 // Remember the vararg offset for the va_start implementation. 430 VarArgsFrameOffset = ArgOffset; 431 432 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 433 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 434 MF.addLiveIn(*CurArgReg, VReg); 435 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 436 437 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 438 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 439 440 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 441 ArgOffset += 4; 442 } 443 } 444 445 if (!OutChains.empty()) 446 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 447 &OutChains[0], OutChains.size())); 448 449 // Finally, inform the code generator which regs we return values in. 450 switch (getValueType(F.getReturnType())) { 451 default: assert(0 && "Unknown type!"); 452 case MVT::isVoid: break; 453 case MVT::i1: 454 case MVT::i8: 455 case MVT::i16: 456 case MVT::i32: 457 MF.addLiveOut(SP::I0); 458 break; 459 case MVT::i64: 460 MF.addLiveOut(SP::I0); 461 MF.addLiveOut(SP::I1); 462 break; 463 case MVT::f32: 464 MF.addLiveOut(SP::F0); 465 break; 466 case MVT::f64: 467 MF.addLiveOut(SP::D0); 468 break; 469 } 470 471 return ArgValues; 472} 473 474std::pair<SDOperand, SDOperand> 475SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 476 bool isVarArg, unsigned CC, 477 bool isTailCall, SDOperand Callee, 478 ArgListTy &Args, SelectionDAG &DAG) { 479 // Count the size of the outgoing arguments. 480 unsigned ArgsSize = 0; 481 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 482 switch (getValueType(Args[i].second)) { 483 default: assert(0 && "Unknown value type!"); 484 case MVT::i1: 485 case MVT::i8: 486 case MVT::i16: 487 case MVT::i32: 488 case MVT::f32: 489 ArgsSize += 4; 490 break; 491 case MVT::i64: 492 case MVT::f64: 493 ArgsSize += 8; 494 break; 495 } 496 } 497 if (ArgsSize > 4*6) 498 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 499 else 500 ArgsSize = 0; 501 502 // Keep stack frames 8-byte aligned. 503 ArgsSize = (ArgsSize+7) & ~7; 504 505 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 506 507 SDOperand StackPtr; 508 std::vector<SDOperand> Stores; 509 std::vector<SDOperand> RegValuesToPass; 510 unsigned ArgOffset = 68; 511 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 512 SDOperand Val = Args[i].first; 513 MVT::ValueType ObjectVT = Val.getValueType(); 514 SDOperand ValToStore(0, 0); 515 unsigned ObjSize; 516 switch (ObjectVT) { 517 default: assert(0 && "Unhandled argument type!"); 518 case MVT::i1: 519 case MVT::i8: 520 case MVT::i16: 521 // Promote the integer to 32-bits. If the input type is signed, use a 522 // sign extend, otherwise use a zero extend. 523 if (Args[i].second->isSigned()) 524 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 525 else 526 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 527 // FALL THROUGH 528 case MVT::i32: 529 ObjSize = 4; 530 531 if (RegValuesToPass.size() >= 6) { 532 ValToStore = Val; 533 } else { 534 RegValuesToPass.push_back(Val); 535 } 536 break; 537 case MVT::f32: 538 ObjSize = 4; 539 if (RegValuesToPass.size() >= 6) { 540 ValToStore = Val; 541 } else { 542 // Convert this to a FP value in an int reg. 543 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 544 RegValuesToPass.push_back(Val); 545 } 546 break; 547 case MVT::f64: 548 ObjSize = 8; 549 // If we can store this directly into the outgoing slot, do so. We can 550 // do this when all ArgRegs are used and if the outgoing slot is aligned. 551 // FIXME: McGill/misr fails with this. 552 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 553 ValToStore = Val; 554 break; 555 } 556 557 // Otherwise, convert this to a FP value in int regs. 558 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 559 // FALL THROUGH 560 case MVT::i64: 561 ObjSize = 8; 562 if (RegValuesToPass.size() >= 6) { 563 ValToStore = Val; // Whole thing is passed in memory. 564 break; 565 } 566 567 // Split the value into top and bottom part. Top part goes in a reg. 568 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 569 DAG.getConstant(1, MVT::i32)); 570 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 571 DAG.getConstant(0, MVT::i32)); 572 RegValuesToPass.push_back(Hi); 573 574 if (RegValuesToPass.size() >= 6) { 575 ValToStore = Lo; 576 ArgOffset += 4; 577 ObjSize = 4; 578 } else { 579 RegValuesToPass.push_back(Lo); 580 } 581 break; 582 } 583 584 if (ValToStore.Val) { 585 if (!StackPtr.Val) { 586 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 587 } 588 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 589 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 590 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 591 } 592 ArgOffset += ObjSize; 593 } 594 595 // Emit all stores, make sure the occur before any copies into physregs. 596 if (!Stores.empty()) 597 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 598 599 static const unsigned ArgRegs[] = { 600 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 601 }; 602 603 // Build a sequence of copy-to-reg nodes chained together with token chain 604 // and flag operands which copy the outgoing args into O[0-5]. 605 SDOperand InFlag; 606 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 607 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 608 InFlag = Chain.getValue(1); 609 } 610 611 // If the callee is a GlobalAddress node (quite common, every direct call is) 612 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 613 // Likewise ExternalSymbol -> TargetExternalSymbol. 614 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 615 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 616 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 617 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 618 619 std::vector<MVT::ValueType> NodeTys; 620 NodeTys.push_back(MVT::Other); // Returns a chain 621 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 622 SDOperand Ops[] = { Chain, Callee, InFlag }; 623 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 624 InFlag = Chain.getValue(1); 625 626 MVT::ValueType RetTyVT = getValueType(RetTy); 627 SDOperand RetVal; 628 if (RetTyVT != MVT::isVoid) { 629 switch (RetTyVT) { 630 default: assert(0 && "Unknown value type to return!"); 631 case MVT::i1: 632 case MVT::i8: 633 case MVT::i16: 634 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 635 Chain = RetVal.getValue(1); 636 637 // Add a note to keep track of whether it is sign or zero extended. 638 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 639 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 640 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 641 break; 642 case MVT::i32: 643 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 644 Chain = RetVal.getValue(1); 645 break; 646 case MVT::f32: 647 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 648 Chain = RetVal.getValue(1); 649 break; 650 case MVT::f64: 651 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 652 Chain = RetVal.getValue(1); 653 break; 654 case MVT::i64: 655 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 656 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 657 Lo.getValue(2)); 658 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 659 Chain = Hi.getValue(1); 660 break; 661 } 662 } 663 664 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 665 DAG.getConstant(ArgsSize, getPointerTy())); 666 667 return std::make_pair(RetVal, Chain); 668} 669 670// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 671// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 672static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 673 ISD::CondCode CC, unsigned &SPCC) { 674 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 675 CC == ISD::SETNE && 676 ((LHS.getOpcode() == SPISD::SELECT_ICC && 677 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 678 (LHS.getOpcode() == SPISD::SELECT_FCC && 679 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 680 isa<ConstantSDNode>(LHS.getOperand(0)) && 681 isa<ConstantSDNode>(LHS.getOperand(1)) && 682 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 683 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 684 SDOperand CMPCC = LHS.getOperand(3); 685 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 686 LHS = CMPCC.getOperand(0); 687 RHS = CMPCC.getOperand(1); 688 } 689} 690 691 692SDOperand SparcTargetLowering:: 693LowerOperation(SDOperand Op, SelectionDAG &DAG) { 694 switch (Op.getOpcode()) { 695 default: assert(0 && "Should not custom lower this!"); 696 case ISD::GlobalAddress: { 697 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 698 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 699 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 700 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 701 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 702 } 703 case ISD::ConstantPool: { 704 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 705 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 706 cast<ConstantPoolSDNode>(Op)->getAlignment()); 707 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 708 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 709 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 710 } 711 case ISD::FP_TO_SINT: 712 // Convert the fp value to integer in an FP register. 713 assert(Op.getValueType() == MVT::i32); 714 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 715 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 716 case ISD::SINT_TO_FP: { 717 assert(Op.getOperand(0).getValueType() == MVT::i32); 718 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 719 // Convert the int value to FP in an FP register. 720 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 721 } 722 case ISD::BR_CC: { 723 SDOperand Chain = Op.getOperand(0); 724 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 725 SDOperand LHS = Op.getOperand(2); 726 SDOperand RHS = Op.getOperand(3); 727 SDOperand Dest = Op.getOperand(4); 728 unsigned Opc, SPCC = ~0U; 729 730 // If this is a br_cc of a "setcc", and if the setcc got lowered into 731 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 732 LookThroughSetCC(LHS, RHS, CC, SPCC); 733 734 // Get the condition flag. 735 SDOperand CompareFlag; 736 if (LHS.getValueType() == MVT::i32) { 737 std::vector<MVT::ValueType> VTs; 738 VTs.push_back(MVT::i32); 739 VTs.push_back(MVT::Flag); 740 SDOperand Ops[2] = { LHS, RHS }; 741 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 742 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 743 Opc = SPISD::BRICC; 744 } else { 745 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 746 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 747 Opc = SPISD::BRFCC; 748 } 749 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 750 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 751 } 752 case ISD::SELECT_CC: { 753 SDOperand LHS = Op.getOperand(0); 754 SDOperand RHS = Op.getOperand(1); 755 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 756 SDOperand TrueVal = Op.getOperand(2); 757 SDOperand FalseVal = Op.getOperand(3); 758 unsigned Opc, SPCC = ~0U; 759 760 // If this is a select_cc of a "setcc", and if the setcc got lowered into 761 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 762 LookThroughSetCC(LHS, RHS, CC, SPCC); 763 764 SDOperand CompareFlag; 765 if (LHS.getValueType() == MVT::i32) { 766 std::vector<MVT::ValueType> VTs; 767 VTs.push_back(LHS.getValueType()); // subcc returns a value 768 VTs.push_back(MVT::Flag); 769 SDOperand Ops[2] = { LHS, RHS }; 770 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 771 Opc = SPISD::SELECT_ICC; 772 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 773 } else { 774 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 775 Opc = SPISD::SELECT_FCC; 776 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 777 } 778 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 779 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 780 } 781 case ISD::VASTART: { 782 // vastart just stores the address of the VarArgsFrameIndex slot into the 783 // memory location argument. 784 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 785 DAG.getRegister(SP::I6, MVT::i32), 786 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 787 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 788 return DAG.getStore(Op.getOperand(0), Offset, 789 Op.getOperand(1), SV->getValue(), SV->getOffset()); 790 } 791 case ISD::VAARG: { 792 SDNode *Node = Op.Val; 793 MVT::ValueType VT = Node->getValueType(0); 794 SDOperand InChain = Node->getOperand(0); 795 SDOperand VAListPtr = Node->getOperand(1); 796 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 797 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 798 SV->getValue(), SV->getOffset()); 799 // Increment the pointer, VAList, to the next vaarg 800 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 801 DAG.getConstant(MVT::getSizeInBits(VT)/8, 802 getPointerTy())); 803 // Store the incremented VAList to the legalized pointer 804 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 805 VAListPtr, SV->getValue(), SV->getOffset()); 806 // Load the actual argument out of the pointer VAList, unless this is an 807 // f64 load. 808 if (VT != MVT::f64) { 809 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 810 } else { 811 // Otherwise, load it as i64, then do a bitconvert. 812 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 813 std::vector<MVT::ValueType> Tys; 814 Tys.push_back(MVT::f64); 815 Tys.push_back(MVT::Other); 816 // Bit-Convert the value to f64. 817 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 818 V.getValue(1) }; 819 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 820 } 821 } 822 case ISD::DYNAMIC_STACKALLOC: { 823 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 824 SDOperand Size = Op.getOperand(1); // Legalize the size. 825 826 unsigned SPReg = SP::O6; 827 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 828 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 829 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 830 831 // The resultant pointer is actually 16 words from the bottom of the stack, 832 // to provide a register spill area. 833 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 834 DAG.getConstant(96, MVT::i32)); 835 std::vector<MVT::ValueType> Tys; 836 Tys.push_back(MVT::i32); 837 Tys.push_back(MVT::Other); 838 SDOperand Ops[2] = { NewVal, Chain }; 839 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 840 } 841 case ISD::RET: { 842 SDOperand Copy; 843 844 switch(Op.getNumOperands()) { 845 default: 846 assert(0 && "Do not know how to return this many arguments!"); 847 abort(); 848 case 1: 849 return SDOperand(); // ret void is legal 850 case 3: { 851 unsigned ArgReg; 852 switch(Op.getOperand(1).getValueType()) { 853 default: assert(0 && "Unknown type to return!"); 854 case MVT::i32: ArgReg = SP::I0; break; 855 case MVT::f32: ArgReg = SP::F0; break; 856 case MVT::f64: ArgReg = SP::D0; break; 857 } 858 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 859 SDOperand()); 860 break; 861 } 862 case 5: 863 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 864 SDOperand()); 865 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 866 break; 867 } 868 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 869 } 870 } 871} 872 873MachineBasicBlock * 874SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 875 MachineBasicBlock *BB) { 876 unsigned BROpcode; 877 unsigned CC; 878 // Figure out the conditional branch opcode to use for this select_cc. 879 switch (MI->getOpcode()) { 880 default: assert(0 && "Unknown SELECT_CC!"); 881 case SP::SELECT_CC_Int_ICC: 882 case SP::SELECT_CC_FP_ICC: 883 case SP::SELECT_CC_DFP_ICC: 884 BROpcode = SP::BCOND; 885 break; 886 case SP::SELECT_CC_Int_FCC: 887 case SP::SELECT_CC_FP_FCC: 888 case SP::SELECT_CC_DFP_FCC: 889 BROpcode = SP::FBCOND; 890 break; 891 } 892 893 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 894 895 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 896 // control-flow pattern. The incoming instruction knows the destination vreg 897 // to set, the condition code register to branch on, the true/false values to 898 // select between, and a branch opcode to use. 899 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 900 ilist<MachineBasicBlock>::iterator It = BB; 901 ++It; 902 903 // thisMBB: 904 // ... 905 // TrueVal = ... 906 // [f]bCC copy1MBB 907 // fallthrough --> copy0MBB 908 MachineBasicBlock *thisMBB = BB; 909 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 910 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 911 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC); 912 MachineFunction *F = BB->getParent(); 913 F->getBasicBlockList().insert(It, copy0MBB); 914 F->getBasicBlockList().insert(It, sinkMBB); 915 // Update machine-CFG edges by first adding all successors of the current 916 // block to the new block which will contain the Phi node for the select. 917 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 918 e = BB->succ_end(); i != e; ++i) 919 sinkMBB->addSuccessor(*i); 920 // Next, remove all successors of the current block, and add the true 921 // and fallthrough blocks as its successors. 922 while(!BB->succ_empty()) 923 BB->removeSuccessor(BB->succ_begin()); 924 BB->addSuccessor(copy0MBB); 925 BB->addSuccessor(sinkMBB); 926 927 // copy0MBB: 928 // %FalseValue = ... 929 // # fallthrough to sinkMBB 930 BB = copy0MBB; 931 932 // Update machine-CFG edges 933 BB->addSuccessor(sinkMBB); 934 935 // sinkMBB: 936 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 937 // ... 938 BB = sinkMBB; 939 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg()) 940 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 941 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 942 943 delete MI; // The pseudo instruction is gone now. 944 return BB; 945} 946 947//===----------------------------------------------------------------------===// 948// Instruction Selector Implementation 949//===----------------------------------------------------------------------===// 950 951//===--------------------------------------------------------------------===// 952/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 953/// instructions for SelectionDAG operations. 954/// 955namespace { 956class SparcDAGToDAGISel : public SelectionDAGISel { 957 SparcTargetLowering Lowering; 958 959 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 960 /// make the right decision when generating code for different targets. 961 const SparcSubtarget &Subtarget; 962public: 963 SparcDAGToDAGISel(TargetMachine &TM) 964 : SelectionDAGISel(Lowering), Lowering(TM), 965 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 966 } 967 968 SDNode *Select(SDOperand Op); 969 970 // Complex Pattern Selectors. 971 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 972 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 973 974 /// InstructionSelectBasicBlock - This callback is invoked by 975 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 976 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 977 978 virtual const char *getPassName() const { 979 return "SPARC DAG->DAG Pattern Instruction Selection"; 980 } 981 982 // Include the pieces autogenerated from the target description. 983#include "SparcGenDAGISel.inc" 984}; 985} // end anonymous namespace 986 987/// InstructionSelectBasicBlock - This callback is invoked by 988/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 989void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 990 DEBUG(BB->dump()); 991 992 // Select target instructions for the DAG. 993 DAG.setRoot(SelectRoot(DAG.getRoot())); 994 DAG.RemoveDeadNodes(); 995 996 // Emit machine code to BB. 997 ScheduleAndEmitDAG(DAG); 998} 999 1000bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 1001 SDOperand &Offset) { 1002 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1003 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1004 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1005 return true; 1006 } 1007 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1008 Addr.getOpcode() == ISD::TargetGlobalAddress) 1009 return false; // direct calls. 1010 1011 if (Addr.getOpcode() == ISD::ADD) { 1012 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1013 if (Predicate_simm13(CN)) { 1014 if (FrameIndexSDNode *FIN = 1015 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1016 // Constant offset from frame ref. 1017 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1018 } else { 1019 Base = Addr.getOperand(0); 1020 } 1021 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1022 return true; 1023 } 1024 } 1025 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1026 Base = Addr.getOperand(1); 1027 Offset = Addr.getOperand(0).getOperand(0); 1028 return true; 1029 } 1030 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1031 Base = Addr.getOperand(0); 1032 Offset = Addr.getOperand(1).getOperand(0); 1033 return true; 1034 } 1035 } 1036 Base = Addr; 1037 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1038 return true; 1039} 1040 1041bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 1042 SDOperand &R2) { 1043 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1044 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1045 Addr.getOpcode() == ISD::TargetGlobalAddress) 1046 return false; // direct calls. 1047 1048 if (Addr.getOpcode() == ISD::ADD) { 1049 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1050 Predicate_simm13(Addr.getOperand(1).Val)) 1051 return false; // Let the reg+imm pattern catch this! 1052 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1053 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1054 return false; // Let the reg+imm pattern catch this! 1055 R1 = Addr.getOperand(0); 1056 R2 = Addr.getOperand(1); 1057 return true; 1058 } 1059 1060 R1 = Addr; 1061 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1062 return true; 1063} 1064 1065SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1066 SDNode *N = Op.Val; 1067 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1068 N->getOpcode() < SPISD::FIRST_NUMBER) 1069 return NULL; // Already selected. 1070 1071 switch (N->getOpcode()) { 1072 default: break; 1073 case ISD::SDIV: 1074 case ISD::UDIV: { 1075 // FIXME: should use a custom expander to expose the SRA to the dag. 1076 SDOperand DivLHS = N->getOperand(0); 1077 SDOperand DivRHS = N->getOperand(1); 1078 AddToISelQueue(DivLHS); 1079 AddToISelQueue(DivRHS); 1080 1081 // Set the Y register to the high-part. 1082 SDOperand TopPart; 1083 if (N->getOpcode() == ISD::SDIV) { 1084 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1085 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1086 } else { 1087 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1088 } 1089 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1090 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1091 1092 // FIXME: Handle div by immediate. 1093 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1094 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1095 TopPart); 1096 } 1097 case ISD::MULHU: 1098 case ISD::MULHS: { 1099 // FIXME: Handle mul by immediate. 1100 SDOperand MulLHS = N->getOperand(0); 1101 SDOperand MulRHS = N->getOperand(1); 1102 AddToISelQueue(MulLHS); 1103 AddToISelQueue(MulRHS); 1104 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1105 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1106 MulLHS, MulRHS); 1107 // The high part is in the Y register. 1108 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1109 return NULL; 1110 } 1111 } 1112 1113 return SelectCode(Op); 1114} 1115 1116 1117/// createSparcISelDag - This pass converts a legalized DAG into a 1118/// SPARC-specific DAG, ready for instruction scheduling. 1119/// 1120FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1121 return new SparcDAGToDAGISel(TM); 1122} 1123