SparcISelDAGToDAG.cpp revision c6fd6cd65c88ef1f11da43c11be0152cb69013a7
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 CALL, // A V8 call instruction. 50 RET_FLAG, // Return with a flag operand. 51 }; 52} 53 54namespace { 55 class SparcV8TargetLowering : public TargetLowering { 56 int VarArgsFrameOffset; // Frame offset to start of varargs area. 57 public: 58 SparcV8TargetLowering(TargetMachine &TM); 59 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 60 61 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 62 /// be zero. Op is expected to be a target specific node. Used by DAG 63 /// combiner. 64 virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op, 65 uint64_t Mask) const; 66 67 virtual std::vector<SDOperand> 68 LowerArguments(Function &F, SelectionDAG &DAG); 69 virtual std::pair<SDOperand, SDOperand> 70 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 71 unsigned CC, 72 bool isTailCall, SDOperand Callee, ArgListTy &Args, 73 SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 80 virtual const char *getTargetNodeName(unsigned Opcode) const; 81 }; 82} 83 84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 85 : TargetLowering(TM) { 86 87 // Set up the register classes. 88 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 89 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 90 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 91 92 // Custom legalize GlobalAddress nodes into LO/HI parts. 93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 94 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 95 96 // Sparc doesn't have sext_inreg, replace them with shl/sra 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 100 101 // Sparc has no REM operation. 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i32, Expand); 104 105 // Custom expand fp<->sint 106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 107 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 108 109 // Expand fp<->uint 110 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 111 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 112 113 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 114 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 115 116 // Turn FP extload into load/fextend 117 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 118 119 // Sparc has no select or setcc: expand to SELECT_CC. 120 setOperationAction(ISD::SELECT, MVT::i32, Expand); 121 setOperationAction(ISD::SELECT, MVT::f32, Expand); 122 setOperationAction(ISD::SELECT, MVT::f64, Expand); 123 setOperationAction(ISD::SETCC, MVT::i32, Expand); 124 setOperationAction(ISD::SETCC, MVT::f32, Expand); 125 setOperationAction(ISD::SETCC, MVT::f64, Expand); 126 127 // Sparc doesn't have BRCOND either, it has BR_CC. 128 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 129 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 130 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 131 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 132 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 133 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 134 135 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 138 139 // V8 has no intrinsics for these particular operations. 140 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 141 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 142 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 143 144 setOperationAction(ISD::FSIN , MVT::f64, Expand); 145 setOperationAction(ISD::FCOS , MVT::f64, Expand); 146 setOperationAction(ISD::FSIN , MVT::f32, Expand); 147 setOperationAction(ISD::FCOS , MVT::f32, Expand); 148 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 149 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 150 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 151 setOperationAction(ISD::ROTL , MVT::i32, Expand); 152 setOperationAction(ISD::ROTR , MVT::i32, Expand); 153 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 154 155 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 156 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 157 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 158 159 // We don't have line number support yet. 160 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 161 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 162 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 163 164 // RET must be custom lowered, to meet ABI requirements 165 setOperationAction(ISD::RET , MVT::Other, Custom); 166 167 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 168 setOperationAction(ISD::VASTART , MVT::Other, Custom); 169 170 // Use the default implementation. 171 setOperationAction(ISD::VAARG , MVT::Other, Expand); 172 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 173 setOperationAction(ISD::VAEND , MVT::Other, Expand); 174 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 175 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 176 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 177 178 setStackPointerRegisterToSaveRestore(V8::O6); 179 180 computeRegisterProperties(); 181} 182 183const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { 184 switch (Opcode) { 185 default: return 0; 186 case V8ISD::CMPICC: return "V8ISD::CMPICC"; 187 case V8ISD::CMPFCC: return "V8ISD::CMPFCC"; 188 case V8ISD::BRICC: return "V8ISD::BRICC"; 189 case V8ISD::BRFCC: return "V8ISD::BRFCC"; 190 case V8ISD::Hi: return "V8ISD::Hi"; 191 case V8ISD::Lo: return "V8ISD::Lo"; 192 case V8ISD::FTOI: return "V8ISD::FTOI"; 193 case V8ISD::ITOF: return "V8ISD::ITOF"; 194 case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC"; 195 case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC"; 196 case V8ISD::CALL: return "V8ISD::CALL"; 197 case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG"; 198 } 199} 200 201/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 202/// be zero. Op is expected to be a target specific node. Used by DAG 203/// combiner. 204bool SparcV8TargetLowering:: 205isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const { 206 switch (Op.getOpcode()) { 207 default: return false; 208 case V8ISD::SELECT_ICC: 209 case V8ISD::SELECT_FCC: 210 assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!"); 211 // These operations are masked zero if both the left and the right are zero. 212 return MaskedValueIsZero(Op.getOperand(0), Mask) && 213 MaskedValueIsZero(Op.getOperand(1), Mask); 214 } 215} 216 217 218/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 219/// either one or two GPRs, including FP values. TODO: we should pass FP values 220/// in FP registers for fastcc functions. 221std::vector<SDOperand> 222SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 223 MachineFunction &MF = DAG.getMachineFunction(); 224 SSARegMap *RegMap = MF.getSSARegMap(); 225 std::vector<SDOperand> ArgValues; 226 227 static const unsigned ArgRegs[] = { 228 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 229 }; 230 231 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 232 unsigned ArgOffset = 68; 233 234 SDOperand Root = DAG.getRoot(); 235 std::vector<SDOperand> OutChains; 236 237 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 238 MVT::ValueType ObjectVT = getValueType(I->getType()); 239 240 switch (ObjectVT) { 241 default: assert(0 && "Unhandled argument type!"); 242 case MVT::i1: 243 case MVT::i8: 244 case MVT::i16: 245 case MVT::i32: 246 if (I->use_empty()) { // Argument is dead. 247 if (CurArgReg < ArgRegEnd) ++CurArgReg; 248 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 249 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 250 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 251 MF.addLiveIn(*CurArgReg++, VReg); 252 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 253 if (ObjectVT != MVT::i32) { 254 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 255 : ISD::AssertZext; 256 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 257 DAG.getValueType(ObjectVT)); 258 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 259 } 260 ArgValues.push_back(Arg); 261 } else { 262 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 263 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 264 SDOperand Load; 265 if (ObjectVT == MVT::i32) { 266 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 267 } else { 268 unsigned LoadOp = 269 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 270 271 // Sparc is big endian, so add an offset based on the ObjectVT. 272 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 273 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 274 DAG.getConstant(Offset, MVT::i32)); 275 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 276 DAG.getSrcValue(0), ObjectVT); 277 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 278 } 279 ArgValues.push_back(Load); 280 } 281 282 ArgOffset += 4; 283 break; 284 case MVT::f32: 285 if (I->use_empty()) { // Argument is dead. 286 if (CurArgReg < ArgRegEnd) ++CurArgReg; 287 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 288 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 289 // FP value is passed in an integer register. 290 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 291 MF.addLiveIn(*CurArgReg++, VReg); 292 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 293 294 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 295 ArgValues.push_back(Arg); 296 } else { 297 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 298 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 299 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); 300 ArgValues.push_back(Load); 301 } 302 ArgOffset += 4; 303 break; 304 305 case MVT::i64: 306 case MVT::f64: 307 if (I->use_empty()) { // Argument is dead. 308 if (CurArgReg < ArgRegEnd) ++CurArgReg; 309 if (CurArgReg < ArgRegEnd) ++CurArgReg; 310 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 311 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 312 ((CurArgReg-ArgRegs) & 1) == 0) { 313 // If this is a double argument and the whole thing lives on the stack, 314 // and the argument is aligned, load the double straight from the stack. 315 // We can't do a load in cases like void foo([6ints], int,double), 316 // because the double wouldn't be aligned! 317 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 318 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 319 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 320 DAG.getSrcValue(0))); 321 } else { 322 SDOperand HiVal; 323 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 324 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 325 MF.addLiveIn(*CurArgReg++, VRegHi); 326 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 327 } else { 328 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 329 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 330 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 331 } 332 333 SDOperand LoVal; 334 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 335 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 336 MF.addLiveIn(*CurArgReg++, VRegLo); 337 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 338 } else { 339 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 340 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 341 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 342 } 343 344 // Compose the two halves together into an i64 unit. 345 SDOperand WholeValue = 346 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 347 348 // If we want a double, do a bit convert. 349 if (ObjectVT == MVT::f64) 350 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 351 352 ArgValues.push_back(WholeValue); 353 } 354 ArgOffset += 8; 355 break; 356 } 357 } 358 359 // Store remaining ArgRegs to the stack if this is a varargs function. 360 if (F.getFunctionType()->isVarArg()) { 361 // Remember the vararg offset for the va_start implementation. 362 VarArgsFrameOffset = ArgOffset; 363 364 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 365 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 366 MF.addLiveIn(*CurArgReg, VReg); 367 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 368 369 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 370 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 371 372 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 373 Arg, FIPtr, DAG.getSrcValue(0))); 374 ArgOffset += 4; 375 } 376 } 377 378 if (!OutChains.empty()) 379 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 380 381 // Finally, inform the code generator which regs we return values in. 382 switch (getValueType(F.getReturnType())) { 383 default: assert(0 && "Unknown type!"); 384 case MVT::isVoid: break; 385 case MVT::i1: 386 case MVT::i8: 387 case MVT::i16: 388 case MVT::i32: 389 MF.addLiveOut(V8::I0); 390 break; 391 case MVT::i64: 392 MF.addLiveOut(V8::I0); 393 MF.addLiveOut(V8::I1); 394 break; 395 case MVT::f32: 396 MF.addLiveOut(V8::F0); 397 break; 398 case MVT::f64: 399 MF.addLiveOut(V8::D0); 400 break; 401 } 402 403 return ArgValues; 404} 405 406std::pair<SDOperand, SDOperand> 407SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 408 bool isVarArg, unsigned CC, 409 bool isTailCall, SDOperand Callee, 410 ArgListTy &Args, SelectionDAG &DAG) { 411 MachineFunction &MF = DAG.getMachineFunction(); 412 // Count the size of the outgoing arguments. 413 unsigned ArgsSize = 0; 414 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 415 switch (getValueType(Args[i].second)) { 416 default: assert(0 && "Unknown value type!"); 417 case MVT::i1: 418 case MVT::i8: 419 case MVT::i16: 420 case MVT::i32: 421 case MVT::f32: 422 ArgsSize += 4; 423 break; 424 case MVT::i64: 425 case MVT::f64: 426 ArgsSize += 8; 427 break; 428 } 429 } 430 if (ArgsSize > 4*6) 431 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 432 else 433 ArgsSize = 0; 434 435 // Keep stack frames 8-byte aligned. 436 ArgsSize = (ArgsSize+7) & ~7; 437 438 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 439 DAG.getConstant(ArgsSize, getPointerTy())); 440 441 SDOperand StackPtr, NullSV; 442 std::vector<SDOperand> Stores; 443 std::vector<SDOperand> RegValuesToPass; 444 unsigned ArgOffset = 68; 445 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 446 SDOperand Val = Args[i].first; 447 MVT::ValueType ObjectVT = Val.getValueType(); 448 SDOperand ValToStore(0, 0); 449 unsigned ObjSize; 450 switch (ObjectVT) { 451 default: assert(0 && "Unhandled argument type!"); 452 case MVT::i1: 453 case MVT::i8: 454 case MVT::i16: 455 // Promote the integer to 32-bits. If the input type is signed, use a 456 // sign extend, otherwise use a zero extend. 457 if (Args[i].second->isSigned()) 458 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 459 else 460 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 461 // FALL THROUGH 462 case MVT::i32: 463 ObjSize = 4; 464 465 if (RegValuesToPass.size() >= 6) { 466 ValToStore = Val; 467 } else { 468 RegValuesToPass.push_back(Val); 469 } 470 break; 471 case MVT::f32: 472 ObjSize = 4; 473 if (RegValuesToPass.size() >= 6) { 474 ValToStore = Val; 475 } else { 476 // Convert this to a FP value in an int reg. 477 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 478 RegValuesToPass.push_back(Val); 479 } 480 break; 481 case MVT::f64: 482 ObjSize = 8; 483 // If we can store this directly into the outgoing slot, do so. We can 484 // do this when all ArgRegs are used and if the outgoing slot is aligned. 485 // FIXME: McGill/misr fails with this. 486 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 487 ValToStore = Val; 488 break; 489 } 490 491 // Otherwise, convert this to a FP value in int regs. 492 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 493 // FALL THROUGH 494 case MVT::i64: 495 ObjSize = 8; 496 if (RegValuesToPass.size() >= 6) { 497 ValToStore = Val; // Whole thing is passed in memory. 498 break; 499 } 500 501 // Split the value into top and bottom part. Top part goes in a reg. 502 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 503 DAG.getConstant(1, MVT::i32)); 504 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 505 DAG.getConstant(0, MVT::i32)); 506 RegValuesToPass.push_back(Hi); 507 508 if (RegValuesToPass.size() >= 6) { 509 ValToStore = Lo; 510 ArgOffset += 4; 511 ObjSize = 4; 512 } else { 513 RegValuesToPass.push_back(Lo); 514 } 515 break; 516 } 517 518 if (ValToStore.Val) { 519 if (!StackPtr.Val) { 520 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 521 NullSV = DAG.getSrcValue(NULL); 522 } 523 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 524 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 525 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 526 ValToStore, PtrOff, NullSV)); 527 } 528 ArgOffset += ObjSize; 529 } 530 531 // Emit all stores, make sure the occur before any copies into physregs. 532 if (!Stores.empty()) 533 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 534 535 static const unsigned ArgRegs[] = { 536 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 537 }; 538 539 // Build a sequence of copy-to-reg nodes chained together with token chain 540 // and flag operands which copy the outgoing args into O[0-5]. 541 SDOperand InFlag; 542 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 543 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 544 InFlag = Chain.getValue(1); 545 } 546 547 // If the callee is a GlobalAddress node (quite common, every direct call is) 548 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 549 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 550 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 551 552 std::vector<MVT::ValueType> NodeTys; 553 NodeTys.push_back(MVT::Other); // Returns a chain 554 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 555 std::vector<SDOperand> Ops; 556 Ops.push_back(Chain); 557 Ops.push_back(Callee); 558 if (InFlag.Val) 559 Ops.push_back(InFlag); 560 Chain = DAG.getNode(V8ISD::CALL, NodeTys, Ops); 561 InFlag = Chain.getValue(1); 562 563 MVT::ValueType RetTyVT = getValueType(RetTy); 564 SDOperand RetVal; 565 if (RetTyVT != MVT::isVoid) { 566 switch (RetTyVT) { 567 default: assert(0 && "Unknown value type to return!"); 568 case MVT::i1: 569 case MVT::i8: 570 case MVT::i16: 571 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 572 Chain = RetVal.getValue(1); 573 574 // Add a note to keep track of whether it is sign or zero extended. 575 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 576 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 577 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 578 break; 579 case MVT::i32: 580 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 581 Chain = RetVal.getValue(1); 582 break; 583 case MVT::f32: 584 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 585 Chain = RetVal.getValue(1); 586 break; 587 case MVT::f64: 588 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 589 Chain = RetVal.getValue(1); 590 break; 591 case MVT::i64: 592 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 593 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 594 Lo.getValue(2)); 595 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 596 Chain = Hi.getValue(1); 597 break; 598 } 599 } 600 601 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 602 DAG.getConstant(ArgsSize, getPointerTy())); 603 604 return std::make_pair(RetVal, Chain); 605} 606 607std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 608LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 609 SelectionDAG &DAG) { 610 assert(0 && "Unimp"); 611 abort(); 612} 613 614SDOperand SparcV8TargetLowering:: 615LowerOperation(SDOperand Op, SelectionDAG &DAG) { 616 switch (Op.getOpcode()) { 617 default: assert(0 && "Should not custom lower this!"); 618 case ISD::GlobalAddress: { 619 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 620 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 621 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 622 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 623 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 624 } 625 case ISD::ConstantPool: { 626 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 627 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 628 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 629 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 630 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 631 } 632 case ISD::FP_TO_SINT: 633 // Convert the fp value to integer in an FP register. 634 assert(Op.getValueType() == MVT::i32); 635 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 636 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 637 case ISD::SINT_TO_FP: { 638 assert(Op.getOperand(0).getValueType() == MVT::i32); 639 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 640 // Convert the int value to FP in an FP register. 641 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp); 642 } 643 case ISD::BR_CC: { 644 SDOperand Chain = Op.getOperand(0); 645 SDOperand CC = Op.getOperand(1); 646 SDOperand LHS = Op.getOperand(2); 647 SDOperand RHS = Op.getOperand(3); 648 SDOperand Dest = Op.getOperand(4); 649 650 // Get the condition flag. 651 if (LHS.getValueType() == MVT::i32) { 652 std::vector<MVT::ValueType> VTs; 653 VTs.push_back(MVT::i32); 654 VTs.push_back(MVT::Flag); 655 std::vector<SDOperand> Ops; 656 Ops.push_back(LHS); 657 Ops.push_back(RHS); 658 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 659 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 660 } else { 661 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 662 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 663 } 664 } 665 case ISD::SELECT_CC: { 666 SDOperand LHS = Op.getOperand(0); 667 SDOperand RHS = Op.getOperand(1); 668 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 669 SDOperand TrueVal = Op.getOperand(2); 670 SDOperand FalseVal = Op.getOperand(3); 671 672 SDOperand CompareFlag; 673 unsigned Opc; 674 if (LHS.getValueType() == MVT::i32) { 675 std::vector<MVT::ValueType> VTs; 676 VTs.push_back(LHS.getValueType()); // subcc returns a value 677 VTs.push_back(MVT::Flag); 678 std::vector<SDOperand> Ops; 679 Ops.push_back(LHS); 680 Ops.push_back(RHS); 681 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 682 Opc = V8ISD::SELECT_ICC; 683 } else { 684 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 685 Opc = V8ISD::SELECT_FCC; 686 } 687 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 688 DAG.getConstant(CC, MVT::i32), CompareFlag); 689 } 690 case ISD::VASTART: { 691 // vastart just stores the address of the VarArgsFrameIndex slot into the 692 // memory location argument. 693 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 694 DAG.getRegister(V8::I6, MVT::i32), 695 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 696 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 697 Op.getOperand(1), Op.getOperand(2)); 698 } 699 case ISD::RET: { 700 SDOperand Copy; 701 702 switch(Op.getNumOperands()) { 703 default: 704 assert(0 && "Do not know how to return this many arguments!"); 705 abort(); 706 case 1: 707 return SDOperand(); // ret void is legal 708 case 2: { 709 unsigned ArgReg; 710 switch(Op.getOperand(1).getValueType()) { 711 default: assert(0 && "Unknown type to return!"); 712 case MVT::i32: ArgReg = V8::I0; break; 713 case MVT::f32: ArgReg = V8::F0; break; 714 case MVT::f64: ArgReg = V8::D0; break; 715 } 716 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 717 SDOperand()); 718 break; 719 } 720 case 3: 721 Copy = DAG.getCopyToReg(Op.getOperand(0), V8::I0, Op.getOperand(2), 722 SDOperand()); 723 Copy = DAG.getCopyToReg(Copy, V8::I1, Op.getOperand(1), Copy.getValue(1)); 724 break; 725 } 726 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 727 } 728 } 729} 730 731MachineBasicBlock * 732SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 733 MachineBasicBlock *BB) { 734 unsigned BROpcode; 735 // Figure out the conditional branch opcode to use for this select_cc. 736 switch (MI->getOpcode()) { 737 default: assert(0 && "Unknown SELECT_CC!"); 738 case V8::SELECT_CC_Int_ICC: 739 case V8::SELECT_CC_FP_ICC: 740 case V8::SELECT_CC_DFP_ICC: 741 // Integer compare. 742 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 743 default: assert(0 && "Unknown integer condition code!"); 744 case ISD::SETEQ: BROpcode = V8::BE; break; 745 case ISD::SETNE: BROpcode = V8::BNE; break; 746 case ISD::SETLT: BROpcode = V8::BL; break; 747 case ISD::SETGT: BROpcode = V8::BG; break; 748 case ISD::SETLE: BROpcode = V8::BLE; break; 749 case ISD::SETGE: BROpcode = V8::BGE; break; 750 case ISD::SETULT: BROpcode = V8::BCS; break; 751 case ISD::SETULE: BROpcode = V8::BLEU; break; 752 case ISD::SETUGT: BROpcode = V8::BGU; break; 753 case ISD::SETUGE: BROpcode = V8::BCC; break; 754 } 755 break; 756 case V8::SELECT_CC_Int_FCC: 757 case V8::SELECT_CC_FP_FCC: 758 case V8::SELECT_CC_DFP_FCC: 759 // FP compare. 760 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 761 default: assert(0 && "Unknown fp condition code!"); 762 case ISD::SETEQ: BROpcode = V8::FBE; break; 763 case ISD::SETNE: BROpcode = V8::FBNE; break; 764 case ISD::SETLT: BROpcode = V8::FBL; break; 765 case ISD::SETGT: BROpcode = V8::FBG; break; 766 case ISD::SETLE: BROpcode = V8::FBLE; break; 767 case ISD::SETGE: BROpcode = V8::FBGE; break; 768 case ISD::SETULT: BROpcode = V8::FBUL; break; 769 case ISD::SETULE: BROpcode = V8::FBULE; break; 770 case ISD::SETUGT: BROpcode = V8::FBUG; break; 771 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 772 case ISD::SETUO: BROpcode = V8::FBU; break; 773 case ISD::SETO: BROpcode = V8::FBO; break; 774 case ISD::SETONE: BROpcode = V8::FBLG; break; 775 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 776 } 777 break; 778 } 779 780 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 781 // control-flow pattern. The incoming instruction knows the destination vreg 782 // to set, the condition code register to branch on, the true/false values to 783 // select between, and a branch opcode to use. 784 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 785 ilist<MachineBasicBlock>::iterator It = BB; 786 ++It; 787 788 // thisMBB: 789 // ... 790 // TrueVal = ... 791 // [f]bCC copy1MBB 792 // fallthrough --> copy0MBB 793 MachineBasicBlock *thisMBB = BB; 794 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 795 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 796 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 797 MachineFunction *F = BB->getParent(); 798 F->getBasicBlockList().insert(It, copy0MBB); 799 F->getBasicBlockList().insert(It, sinkMBB); 800 // Update machine-CFG edges 801 BB->addSuccessor(copy0MBB); 802 BB->addSuccessor(sinkMBB); 803 804 // copy0MBB: 805 // %FalseValue = ... 806 // # fallthrough to sinkMBB 807 BB = copy0MBB; 808 809 // Update machine-CFG edges 810 BB->addSuccessor(sinkMBB); 811 812 // sinkMBB: 813 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 814 // ... 815 BB = sinkMBB; 816 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 817 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 818 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 819 820 delete MI; // The pseudo instruction is gone now. 821 return BB; 822} 823 824//===----------------------------------------------------------------------===// 825// Instruction Selector Implementation 826//===----------------------------------------------------------------------===// 827 828//===--------------------------------------------------------------------===// 829/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine 830/// instructions for SelectionDAG operations. 831/// 832namespace { 833class SparcV8DAGToDAGISel : public SelectionDAGISel { 834 SparcV8TargetLowering V8Lowering; 835public: 836 SparcV8DAGToDAGISel(TargetMachine &TM) 837 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 838 839 SDOperand Select(SDOperand Op); 840 841 // Complex Pattern Selectors. 842 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 843 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 844 845 /// InstructionSelectBasicBlock - This callback is invoked by 846 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 847 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 848 849 virtual const char *getPassName() const { 850 return "SparcV8 DAG->DAG Pattern Instruction Selection"; 851 } 852 853 // Include the pieces autogenerated from the target description. 854#include "SparcV8GenDAGISel.inc" 855}; 856} // end anonymous namespace 857 858/// InstructionSelectBasicBlock - This callback is invoked by 859/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 860void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 861 DEBUG(BB->dump()); 862 863 // Select target instructions for the DAG. 864 DAG.setRoot(Select(DAG.getRoot())); 865 CodeGenMap.clear(); 866 DAG.RemoveDeadNodes(); 867 868 // Emit machine code to BB. 869 ScheduleAndEmitDAG(DAG); 870} 871 872bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 873 SDOperand &Offset) { 874 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 875 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 876 Offset = CurDAG->getTargetConstant(0, MVT::i32); 877 return true; 878 } 879 880 if (Addr.getOpcode() == ISD::ADD) { 881 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 882 if (Predicate_simm13(CN)) { 883 if (FrameIndexSDNode *FIN = 884 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 885 // Constant offset from frame ref. 886 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 887 } else { 888 Base = Select(Addr.getOperand(0)); 889 } 890 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 891 return true; 892 } 893 } 894 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 895 Base = Select(Addr.getOperand(1)); 896 Offset = Addr.getOperand(0).getOperand(0); 897 return true; 898 } 899 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 900 Base = Select(Addr.getOperand(0)); 901 Offset = Addr.getOperand(1).getOperand(0); 902 return true; 903 } 904 } 905 Base = Select(Addr); 906 Offset = CurDAG->getTargetConstant(0, MVT::i32); 907 return true; 908} 909 910bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 911 SDOperand &R2) { 912 if (Addr.getOpcode() == ISD::FrameIndex) return false; 913 if (Addr.getOpcode() == ISD::ADD) { 914 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 915 Predicate_simm13(Addr.getOperand(1).Val)) 916 return false; // Let the reg+imm pattern catch this! 917 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 918 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 919 return false; // Let the reg+imm pattern catch this! 920 R1 = Select(Addr.getOperand(0)); 921 R2 = Select(Addr.getOperand(1)); 922 return true; 923 } 924 925 R1 = Select(Addr); 926 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 927 return true; 928} 929 930SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 931 SDNode *N = Op.Val; 932 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 933 N->getOpcode() < V8ISD::FIRST_NUMBER) 934 return Op; // Already selected. 935 // If this has already been converted, use it. 936 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 937 if (CGMI != CodeGenMap.end()) return CGMI->second; 938 939 switch (N->getOpcode()) { 940 default: break; 941 case ISD::FrameIndex: { 942 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 943 if (N->hasOneUse()) 944 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 945 CurDAG->getTargetFrameIndex(FI, MVT::i32), 946 CurDAG->getTargetConstant(0, MVT::i32)); 947 return CodeGenMap[Op] = 948 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 949 CurDAG->getTargetFrameIndex(FI, MVT::i32), 950 CurDAG->getTargetConstant(0, MVT::i32)); 951 } 952 case ISD::ADD_PARTS: { 953 SDOperand LHSL = Select(N->getOperand(0)); 954 SDOperand LHSH = Select(N->getOperand(1)); 955 SDOperand RHSL = Select(N->getOperand(2)); 956 SDOperand RHSH = Select(N->getOperand(3)); 957 // FIXME, handle immediate RHS. 958 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 959 LHSL, RHSL); 960 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 961 Low.getValue(1)); 962 CodeGenMap[SDOperand(N, 0)] = Low; 963 CodeGenMap[SDOperand(N, 1)] = Hi; 964 return Op.ResNo ? Hi : Low; 965 } 966 case ISD::SUB_PARTS: { 967 SDOperand LHSL = Select(N->getOperand(0)); 968 SDOperand LHSH = Select(N->getOperand(1)); 969 SDOperand RHSL = Select(N->getOperand(2)); 970 SDOperand RHSH = Select(N->getOperand(3)); 971 // FIXME, handle immediate RHS. 972 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 973 LHSL, RHSL); 974 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 975 Low.getValue(1)); 976 CodeGenMap[SDOperand(N, 0)] = Low; 977 CodeGenMap[SDOperand(N, 1)] = Hi; 978 return Op.ResNo ? Hi : Low; 979 } 980 case ISD::SDIV: 981 case ISD::UDIV: { 982 // FIXME: should use a custom expander to expose the SRA to the dag. 983 SDOperand DivLHS = Select(N->getOperand(0)); 984 SDOperand DivRHS = Select(N->getOperand(1)); 985 986 // Set the Y register to the high-part. 987 SDOperand TopPart; 988 if (N->getOpcode() == ISD::SDIV) { 989 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 990 CurDAG->getTargetConstant(31, MVT::i32)); 991 } else { 992 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 993 } 994 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 995 CurDAG->getRegister(V8::G0, MVT::i32)); 996 997 // FIXME: Handle div by immediate. 998 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 999 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 1000 } 1001 case ISD::MULHU: 1002 case ISD::MULHS: { 1003 // FIXME: Handle mul by immediate. 1004 SDOperand MulLHS = Select(N->getOperand(0)); 1005 SDOperand MulRHS = Select(N->getOperand(1)); 1006 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 1007 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1008 MulLHS, MulRHS); 1009 // The high part is in the Y register. 1010 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 1011 } 1012 case V8ISD::CALL: 1013 // FIXME: This is a workaround for a bug in tblgen. 1014 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 1015 // Emits: (CALL:void (tglobaladdr:i32):$dst) 1016 // Pattern complexity = 2 cost = 1 1017 SDOperand N1 = N->getOperand(1); 1018 if (N1.getOpcode() != ISD::TargetGlobalAddress && 1019 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 1020 SDOperand InFlag = SDOperand(0, 0); 1021 SDOperand Chain = N->getOperand(0); 1022 SDOperand Tmp0 = N1; 1023 Chain = Select(Chain); 1024 SDOperand Result; 1025 if (N->getNumOperands() == 3) { 1026 InFlag = Select(N->getOperand(2)); 1027 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1028 Chain, InFlag); 1029 } else { 1030 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1031 Chain); 1032 } 1033 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1034 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1035 return Result.getValue(Op.ResNo); 1036 } 1037 P47Fail:; 1038 1039 } 1040 1041 return SelectCode(Op); 1042} 1043 1044 1045/// createSparcV8ISelDag - This pass converts a legalized DAG into a 1046/// SPARC-specific DAG, ready for instruction scheduling. 1047/// 1048FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1049 return new SparcV8DAGToDAGISel(TM); 1050} 1051