SparcISelDAGToDAG.cpp revision d88fc03602947b5baa35c8b09fe8bcfa2b4a03c1
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 80 virtual const char *getTargetNodeName(unsigned Opcode) const; 81 }; 82} 83 84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 85 : TargetLowering(TM) { 86 87 // Set up the register classes. 88 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 89 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 90 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 91 92 // Custom legalize GlobalAddress nodes into LO/HI parts. 93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 94 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 95 96 // Sparc doesn't have sext_inreg, replace them with shl/sra 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 100 101 // Sparc has no REM operation. 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i32, Expand); 104 105 // Custom expand fp<->sint 106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 107 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 108 109 // Expand fp<->uint 110 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 111 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 112 113 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 114 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 115 116 // Turn FP extload into load/fextend 117 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 118 119 // Sparc has no select or setcc: expand to SELECT_CC. 120 setOperationAction(ISD::SELECT, MVT::i32, Expand); 121 setOperationAction(ISD::SELECT, MVT::f32, Expand); 122 setOperationAction(ISD::SELECT, MVT::f64, Expand); 123 setOperationAction(ISD::SETCC, MVT::i32, Expand); 124 setOperationAction(ISD::SETCC, MVT::f32, Expand); 125 setOperationAction(ISD::SETCC, MVT::f64, Expand); 126 127 // Sparc doesn't have BRCOND either, it has BR_CC. 128 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 129 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 130 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 131 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 132 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 133 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 134 135 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 138 139 // V8 has no intrinsics for these particular operations. 140 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 141 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 142 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 143 144 setOperationAction(ISD::FSIN , MVT::f64, Expand); 145 setOperationAction(ISD::FCOS , MVT::f64, Expand); 146 setOperationAction(ISD::FSIN , MVT::f32, Expand); 147 setOperationAction(ISD::FCOS , MVT::f32, Expand); 148 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 149 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 150 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 151 setOperationAction(ISD::ROTL , MVT::i32, Expand); 152 setOperationAction(ISD::ROTR , MVT::i32, Expand); 153 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 154 155 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 156 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 157 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 158 159 // We don't have line number support yet. 160 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 161 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 162 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 163 164 // Not implemented yet. 165 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 166 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 167 168 computeRegisterProperties(); 169} 170 171const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { 172 switch (Opcode) { 173 default: return 0; 174 case V8ISD::CMPICC: return "V8ISD::CMPICC"; 175 case V8ISD::CMPFCC: return "V8ISD::CMPFCC"; 176 case V8ISD::BRICC: return "V8ISD::BRICC"; 177 case V8ISD::BRFCC: return "V8ISD::BRFCC"; 178 case V8ISD::Hi: return "V8ISD::Hi"; 179 case V8ISD::Lo: return "V8ISD::Lo"; 180 case V8ISD::FTOI: return "V8ISD::FTOI"; 181 case V8ISD::ITOF: return "V8ISD::ITOF"; 182 case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC"; 183 case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC"; 184 case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG"; 185 } 186} 187 188/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 189/// either one or two GPRs, including FP values. TODO: we should pass FP values 190/// in FP registers for fastcc functions. 191std::vector<SDOperand> 192SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 193 MachineFunction &MF = DAG.getMachineFunction(); 194 SSARegMap *RegMap = MF.getSSARegMap(); 195 std::vector<SDOperand> ArgValues; 196 197 static const unsigned ArgRegs[] = { 198 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 199 }; 200 201 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 202 unsigned ArgOffset = 68; 203 204 SDOperand Root = DAG.getRoot(); 205 std::vector<SDOperand> OutChains; 206 207 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 208 MVT::ValueType ObjectVT = getValueType(I->getType()); 209 210 switch (ObjectVT) { 211 default: assert(0 && "Unhandled argument type!"); 212 case MVT::i1: 213 case MVT::i8: 214 case MVT::i16: 215 case MVT::i32: 216 if (I->use_empty()) { // Argument is dead. 217 if (CurArgReg < ArgRegEnd) ++CurArgReg; 218 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 219 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 220 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 221 MF.addLiveIn(*CurArgReg++, VReg); 222 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 223 if (ObjectVT != MVT::i32) { 224 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 225 : ISD::AssertZext; 226 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 227 DAG.getValueType(ObjectVT)); 228 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 229 } 230 ArgValues.push_back(Arg); 231 } else { 232 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 233 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 234 SDOperand Load; 235 if (ObjectVT == MVT::i32) { 236 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 237 } else { 238 unsigned LoadOp = 239 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 240 241 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 242 DAG.getSrcValue(0), ObjectVT); 243 } 244 ArgValues.push_back(Load); 245 } 246 247 ArgOffset += 4; 248 break; 249 case MVT::f32: 250 if (I->use_empty()) { // Argument is dead. 251 if (CurArgReg < ArgRegEnd) ++CurArgReg; 252 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 253 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 254 // FP value is passed in an integer register. 255 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 256 MF.addLiveIn(*CurArgReg++, VReg); 257 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 258 259 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 260 ArgValues.push_back(Arg); 261 } 262 ArgOffset += 4; 263 break; 264 265 case MVT::i64: 266 case MVT::f64: 267 if (I->use_empty()) { // Argument is dead. 268 if (CurArgReg < ArgRegEnd) ++CurArgReg; 269 if (CurArgReg < ArgRegEnd) ++CurArgReg; 270 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 271 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 272 ((CurArgReg-ArgRegs) & 1) == 0) { 273 // If this is a double argument and the whole thing lives on the stack, 274 // and the argument is aligned, load the double straight from the stack. 275 // We can't do a load in cases like void foo([6ints], int,double), 276 // because the double wouldn't be aligned! 277 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 278 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 279 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 280 DAG.getSrcValue(0))); 281 } else { 282 SDOperand HiVal; 283 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 284 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 285 MF.addLiveIn(*CurArgReg++, VRegHi); 286 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 287 } else { 288 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 289 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 290 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 291 } 292 293 SDOperand LoVal; 294 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 295 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 296 MF.addLiveIn(*CurArgReg++, VRegLo); 297 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 298 } else { 299 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 300 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 301 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 302 } 303 304 // Compose the two halves together into an i64 unit. 305 SDOperand WholeValue = 306 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 307 308 // If we want a double, do a bit convert. 309 if (ObjectVT == MVT::f64) 310 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 311 312 ArgValues.push_back(WholeValue); 313 } 314 ArgOffset += 8; 315 break; 316 } 317 } 318 319 // Store remaining ArgRegs to the stack if this is a varargs function. 320 if (F.getFunctionType()->isVarArg()) { 321 // Remember the vararg offset for the va_start implementation. 322 VarArgsFrameOffset = ArgOffset; 323 324 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 325 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 326 MF.addLiveIn(*CurArgReg, VReg); 327 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 328 329 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 330 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 331 332 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 333 Arg, FIPtr, DAG.getSrcValue(0))); 334 ArgOffset += 4; 335 } 336 } 337 338 if (!OutChains.empty()) 339 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 340 341 // Finally, inform the code generator which regs we return values in. 342 switch (getValueType(F.getReturnType())) { 343 default: assert(0 && "Unknown type!"); 344 case MVT::isVoid: break; 345 case MVT::i1: 346 case MVT::i8: 347 case MVT::i16: 348 case MVT::i32: 349 MF.addLiveOut(V8::I0); 350 break; 351 case MVT::i64: 352 MF.addLiveOut(V8::I0); 353 MF.addLiveOut(V8::I1); 354 break; 355 case MVT::f32: 356 MF.addLiveOut(V8::F0); 357 break; 358 case MVT::f64: 359 MF.addLiveOut(V8::D0); 360 break; 361 } 362 363 return ArgValues; 364} 365 366std::pair<SDOperand, SDOperand> 367SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 368 bool isVarArg, unsigned CC, 369 bool isTailCall, SDOperand Callee, 370 ArgListTy &Args, SelectionDAG &DAG) { 371 MachineFunction &MF = DAG.getMachineFunction(); 372 // Count the size of the outgoing arguments. 373 unsigned ArgsSize = 0; 374 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 375 switch (getValueType(Args[i].second)) { 376 default: assert(0 && "Unknown value type!"); 377 case MVT::i1: 378 case MVT::i8: 379 case MVT::i16: 380 case MVT::i32: 381 case MVT::f32: 382 ArgsSize += 4; 383 break; 384 case MVT::i64: 385 case MVT::f64: 386 ArgsSize += 8; 387 break; 388 } 389 } 390 if (ArgsSize > 4*6) 391 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 392 else 393 ArgsSize = 0; 394 395 // Keep stack frames 8-byte aligned. 396 ArgsSize = (ArgsSize+7) & ~7; 397 398 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 399 DAG.getConstant(ArgsSize, getPointerTy())); 400 401 SDOperand StackPtr, NullSV; 402 std::vector<SDOperand> Stores; 403 std::vector<SDOperand> RegValuesToPass; 404 unsigned ArgOffset = 68; 405 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 406 SDOperand Val = Args[i].first; 407 MVT::ValueType ObjectVT = Val.getValueType(); 408 SDOperand ValToStore(0, 0); 409 unsigned ObjSize; 410 switch (ObjectVT) { 411 default: assert(0 && "Unhandled argument type!"); 412 case MVT::i1: 413 case MVT::i8: 414 case MVT::i16: 415 // Promote the integer to 32-bits. If the input type is signed, use a 416 // sign extend, otherwise use a zero extend. 417 if (Args[i].second->isSigned()) 418 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 419 else 420 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 421 // FALL THROUGH 422 case MVT::i32: 423 ObjSize = 4; 424 425 if (RegValuesToPass.size() >= 6) { 426 ValToStore = Val; 427 } else { 428 RegValuesToPass.push_back(Val); 429 } 430 break; 431 case MVT::f32: 432 ObjSize = 4; 433 if (RegValuesToPass.size() >= 6) { 434 ValToStore = Val; 435 } else { 436 // Convert this to a FP value in an int reg. 437 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 438 RegValuesToPass.push_back(Val); 439 } 440 break; 441 case MVT::f64: 442 ObjSize = 8; 443 // If we can store this directly into the outgoing slot, do so. We can 444 // do this when all ArgRegs are used and if the outgoing slot is aligned. 445 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 446 ValToStore = Val; 447 break; 448 } 449 450 // Otherwise, convert this to a FP value in int regs. 451 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 452 // FALL THROUGH 453 case MVT::i64: 454 ObjSize = 8; 455 if (RegValuesToPass.size() >= 6) { 456 ValToStore = Val; // Whole thing is passed in memory. 457 break; 458 } 459 460 // Split the value into top and bottom part. Top part goes in a reg. 461 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 462 DAG.getConstant(1, MVT::i32)); 463 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 464 DAG.getConstant(0, MVT::i32)); 465 RegValuesToPass.push_back(Hi); 466 467 if (RegValuesToPass.size() >= 6) { 468 ValToStore = Lo; 469 ArgOffset += 4; 470 ObjSize = 4; 471 } else { 472 RegValuesToPass.push_back(Lo); 473 } 474 break; 475 } 476 477 if (ValToStore.Val) { 478 if (!StackPtr.Val) { 479 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 480 NullSV = DAG.getSrcValue(NULL); 481 } 482 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 483 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 484 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 485 ValToStore, PtrOff, NullSV)); 486 } 487 ArgOffset += ObjSize; 488 } 489 490 // Emit all stores, make sure the occur before any copies into physregs. 491 if (!Stores.empty()) 492 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 493 494 static const unsigned ArgRegs[] = { 495 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 496 }; 497 498 // Build a sequence of copy-to-reg nodes chained together with token chain 499 // and flag operands which copy the outgoing args into O[0-5]. 500 SDOperand InFlag; 501 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 502 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 503 InFlag = Chain.getValue(1); 504 } 505 506 // If the callee is a GlobalAddress node (quite common, every direct call is) 507 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 508 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 509 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 510 511 std::vector<MVT::ValueType> NodeTys; 512 NodeTys.push_back(MVT::Other); // Returns a chain 513 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 514 if (InFlag.Val) 515 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 516 else 517 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 518 InFlag = Chain.getValue(1); 519 520 MVT::ValueType RetTyVT = getValueType(RetTy); 521 SDOperand RetVal; 522 if (RetTyVT != MVT::isVoid) { 523 switch (RetTyVT) { 524 default: assert(0 && "Unknown value type to return!"); 525 case MVT::i1: 526 case MVT::i8: 527 case MVT::i16: 528 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 529 Chain = RetVal.getValue(1); 530 531 // Add a note to keep track of whether it is sign or zero extended. 532 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 533 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 534 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 535 break; 536 case MVT::i32: 537 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 538 Chain = RetVal.getValue(1); 539 break; 540 case MVT::f32: 541 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 542 Chain = RetVal.getValue(1); 543 break; 544 case MVT::f64: 545 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 546 Chain = RetVal.getValue(1); 547 break; 548 case MVT::i64: 549 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 550 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 551 Lo.getValue(2)); 552 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 553 Chain = Hi.getValue(1); 554 break; 555 } 556 } 557 558 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 559 DAG.getConstant(ArgsSize, getPointerTy())); 560 561 return std::make_pair(RetVal, Chain); 562} 563 564SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 565 SelectionDAG &DAG) { 566 SDOperand Copy; 567 switch (Op.getValueType()) { 568 default: assert(0 && "Unknown type to return!"); 569 case MVT::i32: 570 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 571 break; 572 case MVT::f32: 573 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 574 break; 575 case MVT::f64: 576 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 577 break; 578 case MVT::i64: 579 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 580 DAG.getConstant(1, MVT::i32)); 581 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 582 DAG.getConstant(0, MVT::i32)); 583 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 584 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 585 break; 586 } 587 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 588} 589 590SDOperand SparcV8TargetLowering:: 591LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 592 SelectionDAG &DAG) { 593 594 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 595 DAG.getRegister(V8::I6, MVT::i32), 596 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 597 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset, 598 VAListP, DAG.getSrcValue(VAListV)); 599} 600 601std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 602LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 603 const Type *ArgTy, SelectionDAG &DAG) { 604 // Load the pointer out of the valist. 605 SDOperand Ptr = DAG.getLoad(MVT::i32, Chain, 606 VAListP, DAG.getSrcValue(VAListV)); 607 MVT::ValueType ArgVT = getValueType(ArgTy); 608 SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1), 609 Ptr, DAG.getSrcValue(NULL)); 610 // Increment the pointer. 611 Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr, 612 DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32)); 613 // Store it back to the valist. 614 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr, 615 VAListP, DAG.getSrcValue(VAListV)); 616 return std::make_pair(Val, Chain); 617} 618 619std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 620LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 621 SelectionDAG &DAG) { 622 assert(0 && "Unimp"); 623 abort(); 624} 625 626SDOperand SparcV8TargetLowering:: 627LowerOperation(SDOperand Op, SelectionDAG &DAG) { 628 switch (Op.getOpcode()) { 629 default: assert(0 && "Should not custom lower this!"); 630 case ISD::GlobalAddress: { 631 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 632 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 633 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 634 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 635 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 636 } 637 case ISD::ConstantPool: { 638 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 639 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 640 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 641 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 642 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 643 } 644 case ISD::FP_TO_SINT: 645 // Convert the fp value to integer in an FP register. 646 assert(Op.getValueType() == MVT::i32); 647 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 648 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 649 case ISD::SINT_TO_FP: { 650 assert(Op.getOperand(0).getValueType() == MVT::i32); 651 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 652 // Convert the int value to FP in an FP register. 653 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp); 654 } 655 case ISD::BR_CC: { 656 SDOperand Chain = Op.getOperand(0); 657 SDOperand CC = Op.getOperand(1); 658 SDOperand LHS = Op.getOperand(2); 659 SDOperand RHS = Op.getOperand(3); 660 SDOperand Dest = Op.getOperand(4); 661 662 // Get the condition flag. 663 if (LHS.getValueType() == MVT::i32) { 664 std::vector<MVT::ValueType> VTs; 665 VTs.push_back(MVT::i32); 666 VTs.push_back(MVT::Flag); 667 std::vector<SDOperand> Ops; 668 Ops.push_back(LHS); 669 Ops.push_back(RHS); 670 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 671 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 672 } else { 673 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 674 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 675 } 676 } 677 case ISD::SELECT_CC: { 678 SDOperand LHS = Op.getOperand(0); 679 SDOperand RHS = Op.getOperand(1); 680 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 681 SDOperand TrueVal = Op.getOperand(2); 682 SDOperand FalseVal = Op.getOperand(3); 683 684 SDOperand CompareFlag; 685 unsigned Opc; 686 if (LHS.getValueType() == MVT::i32) { 687 std::vector<MVT::ValueType> VTs; 688 VTs.push_back(LHS.getValueType()); // subcc returns a value 689 VTs.push_back(MVT::Flag); 690 std::vector<SDOperand> Ops; 691 Ops.push_back(LHS); 692 Ops.push_back(RHS); 693 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 694 Opc = V8ISD::SELECT_ICC; 695 } else { 696 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 697 Opc = V8ISD::SELECT_FCC; 698 } 699 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 700 DAG.getConstant(CC, MVT::i32), CompareFlag); 701 } 702 } 703} 704 705MachineBasicBlock * 706SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 707 MachineBasicBlock *BB) { 708 unsigned BROpcode; 709 // Figure out the conditional branch opcode to use for this select_cc. 710 switch (MI->getOpcode()) { 711 default: assert(0 && "Unknown SELECT_CC!"); 712 case V8::SELECT_CC_Int_ICC: 713 case V8::SELECT_CC_FP_ICC: 714 case V8::SELECT_CC_DFP_ICC: 715 // Integer compare. 716 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 717 default: assert(0 && "Unknown integer condition code!"); 718 case ISD::SETEQ: BROpcode = V8::BE; break; 719 case ISD::SETNE: BROpcode = V8::BNE; break; 720 case ISD::SETLT: BROpcode = V8::BL; break; 721 case ISD::SETGT: BROpcode = V8::BG; break; 722 case ISD::SETLE: BROpcode = V8::BLE; break; 723 case ISD::SETGE: BROpcode = V8::BGE; break; 724 case ISD::SETULT: BROpcode = V8::BCS; break; 725 case ISD::SETULE: BROpcode = V8::BLEU; break; 726 case ISD::SETUGT: BROpcode = V8::BGU; break; 727 case ISD::SETUGE: BROpcode = V8::BCC; break; 728 } 729 break; 730 case V8::SELECT_CC_Int_FCC: 731 case V8::SELECT_CC_FP_FCC: 732 case V8::SELECT_CC_DFP_FCC: 733 // FP compare. 734 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 735 default: assert(0 && "Unknown fp condition code!"); 736 case ISD::SETEQ: BROpcode = V8::FBE; break; 737 case ISD::SETNE: BROpcode = V8::FBNE; break; 738 case ISD::SETLT: BROpcode = V8::FBL; break; 739 case ISD::SETGT: BROpcode = V8::FBG; break; 740 case ISD::SETLE: BROpcode = V8::FBLE; break; 741 case ISD::SETGE: BROpcode = V8::FBGE; break; 742 case ISD::SETULT: BROpcode = V8::FBUL; break; 743 case ISD::SETULE: BROpcode = V8::FBULE; break; 744 case ISD::SETUGT: BROpcode = V8::FBUG; break; 745 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 746 case ISD::SETUO: BROpcode = V8::FBU; break; 747 case ISD::SETO: BROpcode = V8::FBO; break; 748 case ISD::SETONE: BROpcode = V8::FBLG; break; 749 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 750 } 751 break; 752 } 753 754 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 755 // control-flow pattern. The incoming instruction knows the destination vreg 756 // to set, the condition code register to branch on, the true/false values to 757 // select between, and a branch opcode to use. 758 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 759 ilist<MachineBasicBlock>::iterator It = BB; 760 ++It; 761 762 // thisMBB: 763 // ... 764 // TrueVal = ... 765 // [f]bCC copy1MBB 766 // fallthrough --> copy0MBB 767 MachineBasicBlock *thisMBB = BB; 768 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 769 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 770 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 771 MachineFunction *F = BB->getParent(); 772 F->getBasicBlockList().insert(It, copy0MBB); 773 F->getBasicBlockList().insert(It, sinkMBB); 774 // Update machine-CFG edges 775 BB->addSuccessor(copy0MBB); 776 BB->addSuccessor(sinkMBB); 777 778 // copy0MBB: 779 // %FalseValue = ... 780 // # fallthrough to sinkMBB 781 BB = copy0MBB; 782 783 // Update machine-CFG edges 784 BB->addSuccessor(sinkMBB); 785 786 // sinkMBB: 787 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 788 // ... 789 BB = sinkMBB; 790 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 791 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 792 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 793 794 delete MI; // The pseudo instruction is gone now. 795 return BB; 796} 797 798//===----------------------------------------------------------------------===// 799// Instruction Selector Implementation 800//===----------------------------------------------------------------------===// 801 802//===--------------------------------------------------------------------===// 803/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 804/// instructions for SelectionDAG operations. 805/// 806namespace { 807class SparcV8DAGToDAGISel : public SelectionDAGISel { 808 SparcV8TargetLowering V8Lowering; 809public: 810 SparcV8DAGToDAGISel(TargetMachine &TM) 811 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 812 813 SDOperand Select(SDOperand Op); 814 815 // Complex Pattern Selectors. 816 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 817 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 818 819 /// InstructionSelectBasicBlock - This callback is invoked by 820 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 821 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 822 823 virtual const char *getPassName() const { 824 return "PowerPC DAG->DAG Pattern Instruction Selection"; 825 } 826 827 // Include the pieces autogenerated from the target description. 828#include "SparcV8GenDAGISel.inc" 829}; 830} // end anonymous namespace 831 832/// InstructionSelectBasicBlock - This callback is invoked by 833/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 834void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 835 DEBUG(BB->dump()); 836 837 // Select target instructions for the DAG. 838 DAG.setRoot(Select(DAG.getRoot())); 839 CodeGenMap.clear(); 840 DAG.RemoveDeadNodes(); 841 842 // Emit machine code to BB. 843 ScheduleAndEmitDAG(DAG); 844} 845 846bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 847 SDOperand &Offset) { 848 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 849 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 850 Offset = CurDAG->getTargetConstant(0, MVT::i32); 851 return true; 852 } 853 854 if (Addr.getOpcode() == ISD::ADD) { 855 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 856 if (Predicate_simm13(CN)) { 857 if (FrameIndexSDNode *FIN = 858 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 859 // Constant offset from frame ref. 860 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 861 } else { 862 Base = Select(Addr.getOperand(0)); 863 } 864 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 865 return true; 866 } 867 } 868 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 869 Base = Select(Addr.getOperand(1)); 870 Offset = Addr.getOperand(0).getOperand(0); 871 return true; 872 } 873 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 874 Base = Select(Addr.getOperand(0)); 875 Offset = Addr.getOperand(1).getOperand(0); 876 return true; 877 } 878 } 879 Base = Select(Addr); 880 Offset = CurDAG->getTargetConstant(0, MVT::i32); 881 return true; 882} 883 884bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 885 SDOperand &R2) { 886 if (Addr.getOpcode() == ISD::FrameIndex) return false; 887 if (Addr.getOpcode() == ISD::ADD) { 888 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 889 Predicate_simm13(Addr.getOperand(1).Val)) 890 return false; // Let the reg+imm pattern catch this! 891 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 892 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 893 return false; // Let the reg+imm pattern catch this! 894 R1 = Select(Addr.getOperand(0)); 895 R2 = Select(Addr.getOperand(1)); 896 return true; 897 } 898 899 R1 = Select(Addr); 900 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 901 return true; 902} 903 904SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 905 SDNode *N = Op.Val; 906 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 907 N->getOpcode() < V8ISD::FIRST_NUMBER) 908 return Op; // Already selected. 909 // If this has already been converted, use it. 910 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 911 if (CGMI != CodeGenMap.end()) return CGMI->second; 912 913 switch (N->getOpcode()) { 914 default: break; 915 case ISD::FrameIndex: { 916 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 917 if (N->hasOneUse()) 918 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 919 CurDAG->getTargetFrameIndex(FI, MVT::i32), 920 CurDAG->getTargetConstant(0, MVT::i32)); 921 return CodeGenMap[Op] = 922 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 923 CurDAG->getTargetFrameIndex(FI, MVT::i32), 924 CurDAG->getTargetConstant(0, MVT::i32)); 925 } 926 case ISD::ADD_PARTS: { 927 SDOperand LHSL = Select(N->getOperand(0)); 928 SDOperand LHSH = Select(N->getOperand(1)); 929 SDOperand RHSL = Select(N->getOperand(2)); 930 SDOperand RHSH = Select(N->getOperand(3)); 931 // FIXME, handle immediate RHS. 932 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 933 LHSL, RHSL); 934 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 935 Low.getValue(1)); 936 CodeGenMap[SDOperand(N, 0)] = Low; 937 CodeGenMap[SDOperand(N, 1)] = Hi; 938 return Op.ResNo ? Hi : Low; 939 } 940 case ISD::SUB_PARTS: { 941 SDOperand LHSL = Select(N->getOperand(0)); 942 SDOperand LHSH = Select(N->getOperand(1)); 943 SDOperand RHSL = Select(N->getOperand(2)); 944 SDOperand RHSH = Select(N->getOperand(3)); 945 // FIXME, handle immediate RHS. 946 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 947 LHSL, RHSL); 948 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 949 Low.getValue(1)); 950 CodeGenMap[SDOperand(N, 0)] = Low; 951 CodeGenMap[SDOperand(N, 1)] = Hi; 952 return Op.ResNo ? Hi : Low; 953 } 954 case ISD::SDIV: 955 case ISD::UDIV: { 956 // FIXME: should use a custom expander to expose the SRA to the dag. 957 SDOperand DivLHS = Select(N->getOperand(0)); 958 SDOperand DivRHS = Select(N->getOperand(1)); 959 960 // Set the Y register to the high-part. 961 SDOperand TopPart; 962 if (N->getOpcode() == ISD::SDIV) { 963 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 964 CurDAG->getTargetConstant(31, MVT::i32)); 965 } else { 966 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 967 } 968 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 969 CurDAG->getRegister(V8::G0, MVT::i32)); 970 971 // FIXME: Handle div by immediate. 972 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 973 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 974 } 975 case ISD::MULHU: 976 case ISD::MULHS: { 977 // FIXME: Handle mul by immediate. 978 SDOperand MulLHS = Select(N->getOperand(0)); 979 SDOperand MulRHS = Select(N->getOperand(1)); 980 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 981 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 982 MulLHS, MulRHS); 983 // The high part is in the Y register. 984 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 985 } 986 case ISD::CALL: 987 // FIXME: This is a workaround for a bug in tblgen. 988 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 989 // Emits: (CALL:void (tglobaladdr:i32):$dst) 990 // Pattern complexity = 2 cost = 1 991 SDOperand N1 = N->getOperand(1); 992 if (N1.getOpcode() != ISD::TargetGlobalAddress && 993 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 994 SDOperand InFlag = SDOperand(0, 0); 995 SDOperand Chain = N->getOperand(0); 996 SDOperand Tmp0 = N1; 997 Chain = Select(Chain); 998 SDOperand Result; 999 if (N->getNumOperands() == 3) { 1000 InFlag = Select(N->getOperand(2)); 1001 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1002 Chain, InFlag); 1003 } else { 1004 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1005 Chain); 1006 } 1007 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1008 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1009 return Result.getValue(Op.ResNo); 1010 } 1011 P47Fail:; 1012 1013 } 1014 1015 return SelectCode(Op); 1016} 1017 1018 1019/// createPPCISelDag - This pass converts a legalized DAG into a 1020/// PowerPC-specific DAG, ready for instruction scheduling. 1021/// 1022FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1023 return new SparcV8DAGToDAGISel(TM); 1024} 1025