SparcISelDAGToDAG.cpp revision e90ac3a3e7959143d7c92c50061b2c16e4124d9f
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 // Turn FP extload into load/fextend 112 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 113 114 // Sparc has no select or setcc: expand to SELECT_CC. 115 setOperationAction(ISD::SELECT, MVT::i32, Expand); 116 setOperationAction(ISD::SELECT, MVT::f32, Expand); 117 setOperationAction(ISD::SELECT, MVT::f64, Expand); 118 setOperationAction(ISD::SETCC, MVT::i32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f32, Expand); 120 setOperationAction(ISD::SETCC, MVT::f64, Expand); 121 122 // Sparc doesn't have BRCOND either, it has BR_CC. 123 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 124 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 125 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 126 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 127 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 128 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 129 130 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 131 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 132 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 133 134 // V8 has no intrinsics for these particular operations. 135 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 136 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 137 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 138 139 computeRegisterProperties(); 140} 141 142/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 143/// either one or two GPRs, including FP values. TODO: we should pass FP values 144/// in FP registers for fastcc functions. 145std::vector<SDOperand> 146SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 147 MachineFunction &MF = DAG.getMachineFunction(); 148 SSARegMap *RegMap = MF.getSSARegMap(); 149 std::vector<SDOperand> ArgValues; 150 151 static const unsigned ArgRegs[] = { 152 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 153 }; 154 155 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 156 unsigned ArgOffset = 68; 157 158 SDOperand Root = DAG.getRoot(); 159 std::vector<SDOperand> OutChains; 160 161 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 162 MVT::ValueType ObjectVT = getValueType(I->getType()); 163 164 switch (ObjectVT) { 165 default: assert(0 && "Unhandled argument type!"); 166 case MVT::i1: 167 case MVT::i8: 168 case MVT::i16: 169 case MVT::i32: 170 if (I->use_empty()) { // Argument is dead. 171 if (CurArgReg < ArgRegEnd) ++CurArgReg; 172 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 173 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 174 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 175 MF.addLiveIn(*CurArgReg++, VReg); 176 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 177 if (ObjectVT != MVT::i32) { 178 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 179 : ISD::AssertZext; 180 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 181 DAG.getValueType(ObjectVT)); 182 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 183 } 184 ArgValues.push_back(Arg); 185 } else { 186 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 187 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 188 SDOperand Load; 189 if (ObjectVT == MVT::i32) { 190 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 191 } else { 192 unsigned LoadOp = 193 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 194 195 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 196 DAG.getSrcValue(0), ObjectVT); 197 } 198 ArgValues.push_back(Load); 199 } 200 201 ArgOffset += 4; 202 break; 203 case MVT::f32: 204 if (I->use_empty()) { // Argument is dead. 205 if (CurArgReg < ArgRegEnd) ++CurArgReg; 206 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 207 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 208 // FP value is passed in an integer register. 209 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 210 MF.addLiveIn(*CurArgReg++, VReg); 211 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 212 213 // We use the stack space that is already reserved for this reg. 214 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 215 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 216 217 SDOperand SV = DAG.getSrcValue(0); 218 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 219 Arg, FIPtr, SV); 220 ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV)); 221 } 222 ArgOffset += 4; 223 break; 224 225 case MVT::i64: 226 case MVT::f64: 227 if (I->use_empty()) { // Argument is dead. 228 if (CurArgReg < ArgRegEnd) ++CurArgReg; 229 if (CurArgReg < ArgRegEnd) ++CurArgReg; 230 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 231 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 232 ((CurArgReg-ArgRegs) & 1) == 0) { 233 // If this is a double argument and the whole thing lives on the stack, 234 // and the argument is aligned, load the double straight from the stack. 235 // We can't do a load in cases like void foo([6ints], int,double), 236 // because the double wouldn't be aligned! 237 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 238 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 239 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 240 DAG.getSrcValue(0))); 241 } else { 242 SDOperand HiVal; 243 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 244 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 245 MF.addLiveIn(*CurArgReg++, VRegHi); 246 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 247 } else { 248 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 249 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 250 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 251 } 252 253 SDOperand LoVal; 254 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 255 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 256 MF.addLiveIn(*CurArgReg++, VRegLo); 257 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 258 } else { 259 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 260 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 261 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 262 } 263 264 // Compose the two halves together into an i64 unit. 265 SDOperand WholeValue = 266 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 267 268 if (ObjectVT == MVT::i64) { 269 // If we are emitting an i64, this is what we want. 270 ArgValues.push_back(WholeValue); 271 } else { 272 assert(ObjectVT == MVT::f64); 273 // Otherwise, emit a store to the stack and reload into FPR. 274 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 275 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 276 SDOperand SV = DAG.getSrcValue(0); 277 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 278 WholeValue, FIPtr, SV); 279 ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV)); 280 } 281 } 282 ArgOffset += 8; 283 break; 284 } 285 } 286 287 // Store remaining ArgRegs to the stack if this is a varargs function. 288 if (F.getFunctionType()->isVarArg()) { 289 // Remember the vararg offset for the va_start implementation. 290 VarArgsFrameOffset = ArgOffset; 291 292 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 293 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 294 MF.addLiveIn(*CurArgReg, VReg); 295 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 296 297 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 298 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 299 300 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 301 Arg, FIPtr, DAG.getSrcValue(0))); 302 ArgOffset += 4; 303 } 304 } 305 306 if (!OutChains.empty()) 307 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 308 309 // Finally, inform the code generator which regs we return values in. 310 switch (getValueType(F.getReturnType())) { 311 default: assert(0 && "Unknown type!"); 312 case MVT::isVoid: break; 313 case MVT::i1: 314 case MVT::i8: 315 case MVT::i16: 316 case MVT::i32: 317 MF.addLiveOut(V8::I0); 318 break; 319 case MVT::i64: 320 MF.addLiveOut(V8::I0); 321 MF.addLiveOut(V8::I1); 322 break; 323 case MVT::f32: 324 MF.addLiveOut(V8::F0); 325 break; 326 case MVT::f64: 327 MF.addLiveOut(V8::D0); 328 break; 329 } 330 331 return ArgValues; 332} 333 334std::pair<SDOperand, SDOperand> 335SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 336 bool isVarArg, unsigned CC, 337 bool isTailCall, SDOperand Callee, 338 ArgListTy &Args, SelectionDAG &DAG) { 339 MachineFunction &MF = DAG.getMachineFunction(); 340 // Count the size of the outgoing arguments. 341 unsigned ArgsSize = 0; 342 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 343 switch (getValueType(Args[i].second)) { 344 default: assert(0 && "Unknown value type!"); 345 case MVT::i1: 346 case MVT::i8: 347 case MVT::i16: 348 case MVT::i32: 349 case MVT::f32: 350 ArgsSize += 4; 351 break; 352 case MVT::i64: 353 case MVT::f64: 354 ArgsSize += 8; 355 break; 356 } 357 } 358 if (ArgsSize > 4*6) 359 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 360 else 361 ArgsSize = 0; 362 363 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 364 DAG.getConstant(ArgsSize, getPointerTy())); 365 366 SDOperand StackPtr, NullSV; 367 std::vector<SDOperand> Stores; 368 std::vector<SDOperand> RegValuesToPass; 369 unsigned ArgOffset = 68; 370 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 371 SDOperand Val = Args[i].first; 372 MVT::ValueType ObjectVT = Val.getValueType(); 373 SDOperand ValToStore; 374 unsigned ObjSize; 375 switch (ObjectVT) { 376 default: assert(0 && "Unhandled argument type!"); 377 case MVT::i1: 378 case MVT::i8: 379 case MVT::i16: 380 // Promote the integer to 32-bits. If the input type is signed, use a 381 // sign extend, otherwise use a zero extend. 382 if (Args[i].second->isSigned()) 383 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 384 else 385 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 386 // FALL THROUGH 387 case MVT::i32: 388 ObjSize = 4; 389 390 if (RegValuesToPass.size() >= 6) { 391 ValToStore = Val; 392 } else { 393 RegValuesToPass.push_back(Val); 394 } 395 break; 396 case MVT::f32: 397 ObjSize = 4; 398 if (RegValuesToPass.size() >= 6) { 399 ValToStore = Val; 400 } else { 401 // Convert this to a FP value in an int reg. 402 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); 403 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 404 SDOperand SV = DAG.getSrcValue(0); 405 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 406 Val, FIPtr, SV); 407 Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV); 408 RegValuesToPass.push_back(Val); 409 } 410 break; 411 case MVT::f64: { 412 ObjSize = 8; 413 // If we can store this directly into the outgoing slot, do so. We can 414 // do this when all ArgRegs are used and if the outgoing slot is aligned. 415 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 416 ValToStore = Val; 417 break; 418 } 419 420 // Otherwise, convert this to a FP value in int regs. 421 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 422 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 423 SDOperand SV = DAG.getSrcValue(0); 424 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 425 Val, FIPtr, SV); 426 Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV); 427 } 428 // FALL THROUGH 429 case MVT::i64: 430 ObjSize = 8; 431 if (RegValuesToPass.size() >= 6) { 432 ValToStore = Val; // Whole thing is passed in memory. 433 break; 434 } 435 436 // Split the value into top and bottom part. Top part goes in a reg. 437 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 438 DAG.getConstant(1, MVT::i32)); 439 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 440 DAG.getConstant(0, MVT::i32)); 441 RegValuesToPass.push_back(Hi); 442 443 if (RegValuesToPass.size() >= 6) { 444 ValToStore = Lo; 445 } else { 446 RegValuesToPass.push_back(Lo); 447 } 448 break; 449 } 450 451 if (ValToStore.Val) { 452 if (!StackPtr.Val) { 453 StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::SP, MVT::i32); 454 NullSV = DAG.getSrcValue(NULL); 455 } 456 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 457 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 458 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 459 ValToStore, PtrOff, NullSV)); 460 } 461 ArgOffset += ObjSize; 462 } 463 464 // Emit all stores, make sure the occur before any copies into physregs. 465 if (!Stores.empty()) 466 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 467 468 static const unsigned ArgRegs[] = { 469 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 470 }; 471 472 // Build a sequence of copy-to-reg nodes chained together with token chain 473 // and flag operands which copy the outgoing args into O[0-5]. 474 SDOperand InFlag; 475 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 476 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 477 InFlag = Chain.getValue(1); 478 } 479 480 std::vector<MVT::ValueType> RetVals; 481 RetVals.push_back(MVT::Other); 482 RetVals.push_back(MVT::Flag); 483 484 // If the callee is a GlobalAddress node (quite common, every direct call is) 485 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 486 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 487 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 488 489 std::vector<MVT::ValueType> NodeTys; 490 NodeTys.push_back(MVT::Other); // Returns a chain 491 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 492 if (InFlag.Val) 493 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 494 else 495 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 496 InFlag = Chain.getValue(1); 497 498 MVT::ValueType RetTyVT = getValueType(RetTy); 499 SDOperand RetVal; 500 if (RetTyVT != MVT::isVoid) { 501 switch (RetTyVT) { 502 default: assert(0 && "Unknown value type to return!"); 503 case MVT::i1: 504 case MVT::i8: 505 case MVT::i16: 506 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 507 Chain = RetVal.getValue(1); 508 509 // Add a note to keep track of whether it is sign or zero extended. 510 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 511 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 512 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 513 break; 514 case MVT::i32: 515 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 516 Chain = RetVal.getValue(1); 517 break; 518 case MVT::f32: 519 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 520 Chain = RetVal.getValue(1); 521 break; 522 case MVT::f64: 523 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 524 Chain = RetVal.getValue(1); 525 break; 526 case MVT::i64: 527 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 528 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 529 Lo.getValue(2)); 530 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 531 Chain = Hi.getValue(1); 532 break; 533 } 534 } 535 536 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 537 DAG.getConstant(ArgsSize, getPointerTy())); 538 539 MVT::ValueType ActualRetTyVT = RetTyVT; 540 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 541 ActualRetTyVT = MVT::i32; // Promote result to i32. 542 543 return std::make_pair(RetVal, Chain); 544} 545 546SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 547 SelectionDAG &DAG) { 548 SDOperand Copy; 549 switch (Op.getValueType()) { 550 default: assert(0 && "Unknown type to return!"); 551 case MVT::i32: 552 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 553 break; 554 case MVT::f32: 555 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 556 break; 557 case MVT::f64: 558 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 559 break; 560 case MVT::i64: 561 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 562 DAG.getConstant(1, MVT::i32)); 563 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 564 DAG.getConstant(0, MVT::i32)); 565 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 566 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 567 break; 568 } 569 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 570} 571 572SDOperand SparcV8TargetLowering:: 573LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 574 SelectionDAG &DAG) { 575 576 assert(0 && "Unimp"); 577 abort(); 578} 579 580std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 581LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 582 const Type *ArgTy, SelectionDAG &DAG) { 583 assert(0 && "Unimp"); 584 abort(); 585} 586 587std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 588LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 589 SelectionDAG &DAG) { 590 assert(0 && "Unimp"); 591 abort(); 592} 593 594SDOperand SparcV8TargetLowering:: 595LowerOperation(SDOperand Op, SelectionDAG &DAG) { 596 switch (Op.getOpcode()) { 597 default: assert(0 && "Should not custom lower this!"); 598 case ISD::GlobalAddress: { 599 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 600 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 601 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 602 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 603 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 604 } 605 case ISD::ConstantPool: { 606 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 607 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 608 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 609 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 610 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 611 } 612 case ISD::FP_TO_SINT: { 613 // Convert the fp value to integer in an FP register. 614 Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(), 615 Op.getOperand(0)); 616 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 617 int FrameIdx = 618 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 619 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 620 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 621 Op, FI, DAG.getSrcValue(0)); 622 return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0)); 623 } 624 case ISD::SINT_TO_FP: { 625 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 626 int FrameIdx = 627 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 628 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 629 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 630 Op.getOperand(0), FI, DAG.getSrcValue(0)); 631 632 Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0)); 633 634 // Convert the int value to FP in an FP register. 635 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op); 636 } 637 case ISD::BR_CC: { 638 SDOperand Chain = Op.getOperand(0); 639 SDOperand CC = Op.getOperand(1); 640 SDOperand LHS = Op.getOperand(2); 641 SDOperand RHS = Op.getOperand(3); 642 SDOperand Dest = Op.getOperand(4); 643 644 // Get the condition flag. 645 if (LHS.getValueType() == MVT::i32) { 646 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); 647 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 648 } else { 649 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 650 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 651 } 652 } 653 case ISD::SELECT_CC: { 654 SDOperand LHS = Op.getOperand(0); 655 SDOperand RHS = Op.getOperand(1); 656 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 657 SDOperand TrueVal = Op.getOperand(2); 658 SDOperand FalseVal = Op.getOperand(3); 659 660 unsigned Opc; 661 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 662 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); 663 664 Opc = LHS.getValueType() == MVT::i32 ? 665 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 666 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 667 DAG.getConstant(CC, MVT::i32), CompareFlag); 668 } 669 } 670} 671 672MachineBasicBlock * 673SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 674 MachineBasicBlock *BB) { 675 unsigned BROpcode; 676 // Figure out the conditional branch opcode to use for this select_cc. 677 switch (MI->getOpcode()) { 678 default: assert(0 && "Unknown SELECT_CC!"); 679 case V8::SELECT_CC_Int_ICC: 680 case V8::SELECT_CC_FP_ICC: 681 case V8::SELECT_CC_DFP_ICC: 682 // Integer compare. 683 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 684 default: assert(0 && "Unknown integer condition code!"); 685 case ISD::SETEQ: BROpcode = V8::BE; break; 686 case ISD::SETNE: BROpcode = V8::BNE; break; 687 case ISD::SETLT: BROpcode = V8::BL; break; 688 case ISD::SETGT: BROpcode = V8::BG; break; 689 case ISD::SETLE: BROpcode = V8::BLE; break; 690 case ISD::SETGE: BROpcode = V8::BGE; break; 691 case ISD::SETULT: BROpcode = V8::BCS; break; 692 case ISD::SETULE: BROpcode = V8::BLEU; break; 693 case ISD::SETUGT: BROpcode = V8::BGU; break; 694 case ISD::SETUGE: BROpcode = V8::BCC; break; 695 } 696 break; 697 case V8::SELECT_CC_Int_FCC: 698 case V8::SELECT_CC_FP_FCC: 699 case V8::SELECT_CC_DFP_FCC: 700 // FP compare. 701 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 702 default: assert(0 && "Unknown fp condition code!"); 703 case ISD::SETEQ: BROpcode = V8::FBE; break; 704 case ISD::SETNE: BROpcode = V8::FBNE; break; 705 case ISD::SETLT: BROpcode = V8::FBL; break; 706 case ISD::SETGT: BROpcode = V8::FBG; break; 707 case ISD::SETLE: BROpcode = V8::FBLE; break; 708 case ISD::SETGE: BROpcode = V8::FBGE; break; 709 case ISD::SETULT: BROpcode = V8::FBUL; break; 710 case ISD::SETULE: BROpcode = V8::FBULE; break; 711 case ISD::SETUGT: BROpcode = V8::FBUG; break; 712 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 713 case ISD::SETUO: BROpcode = V8::FBU; break; 714 case ISD::SETO: BROpcode = V8::FBO; break; 715 case ISD::SETONE: BROpcode = V8::FBLG; break; 716 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 717 } 718 break; 719 } 720 721 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 722 // control-flow pattern. The incoming instruction knows the destination vreg 723 // to set, the condition code register to branch on, the true/false values to 724 // select between, and a branch opcode to use. 725 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 726 ilist<MachineBasicBlock>::iterator It = BB; 727 ++It; 728 729 // thisMBB: 730 // ... 731 // TrueVal = ... 732 // [f]bCC copy1MBB 733 // fallthrough --> copy0MBB 734 MachineBasicBlock *thisMBB = BB; 735 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 736 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 737 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 738 MachineFunction *F = BB->getParent(); 739 F->getBasicBlockList().insert(It, copy0MBB); 740 F->getBasicBlockList().insert(It, sinkMBB); 741 // Update machine-CFG edges 742 BB->addSuccessor(copy0MBB); 743 BB->addSuccessor(sinkMBB); 744 745 // copy0MBB: 746 // %FalseValue = ... 747 // # fallthrough to sinkMBB 748 BB = copy0MBB; 749 750 // Update machine-CFG edges 751 BB->addSuccessor(sinkMBB); 752 753 // sinkMBB: 754 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 755 // ... 756 BB = sinkMBB; 757 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 758 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 759 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 760 761 delete MI; // The pseudo instruction is gone now. 762 return BB; 763} 764 765//===----------------------------------------------------------------------===// 766// Instruction Selector Implementation 767//===----------------------------------------------------------------------===// 768 769//===--------------------------------------------------------------------===// 770/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 771/// instructions for SelectionDAG operations. 772/// 773namespace { 774class SparcV8DAGToDAGISel : public SelectionDAGISel { 775 SparcV8TargetLowering V8Lowering; 776public: 777 SparcV8DAGToDAGISel(TargetMachine &TM) 778 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 779 780 SDOperand Select(SDOperand Op); 781 782 // Complex Pattern Selectors. 783 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 784 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 785 786 /// InstructionSelectBasicBlock - This callback is invoked by 787 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 788 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 789 790 virtual const char *getPassName() const { 791 return "PowerPC DAG->DAG Pattern Instruction Selection"; 792 } 793 794 // Include the pieces autogenerated from the target description. 795#include "SparcV8GenDAGISel.inc" 796}; 797} // end anonymous namespace 798 799/// InstructionSelectBasicBlock - This callback is invoked by 800/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 801void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 802 DEBUG(BB->dump()); 803 804 // Select target instructions for the DAG. 805 DAG.setRoot(Select(DAG.getRoot())); 806 CodeGenMap.clear(); 807 DAG.RemoveDeadNodes(); 808 809 // Emit machine code to BB. 810 ScheduleAndEmitDAG(DAG); 811} 812 813bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 814 SDOperand &Offset) { 815 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 816 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 817 Offset = CurDAG->getTargetConstant(0, MVT::i32); 818 return true; 819 } 820 821 if (Addr.getOpcode() == ISD::ADD) { 822 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 823 if (Predicate_simm13(CN)) { 824 if (FrameIndexSDNode *FIN = 825 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 826 // Constant offset from frame ref. 827 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 828 } else { 829 Base = Select(Addr.getOperand(0)); 830 } 831 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 832 return true; 833 } 834 } 835 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 836 Base = Select(Addr.getOperand(1)); 837 Offset = Addr.getOperand(0).getOperand(0); 838 return true; 839 } 840 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 841 Base = Select(Addr.getOperand(0)); 842 Offset = Addr.getOperand(1).getOperand(0); 843 return true; 844 } 845 } 846 Base = Select(Addr); 847 Offset = CurDAG->getTargetConstant(0, MVT::i32); 848 return true; 849} 850 851bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 852 SDOperand &R2) { 853 if (Addr.getOpcode() == ISD::FrameIndex) return false; 854 if (Addr.getOpcode() == ISD::ADD) { 855 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 856 Predicate_simm13(Addr.getOperand(1).Val)) 857 return false; // Let the reg+imm pattern catch this! 858 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 859 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 860 return false; // Let the reg+imm pattern catch this! 861 R1 = Select(Addr.getOperand(0)); 862 R2 = Select(Addr.getOperand(1)); 863 return true; 864 } 865 866 R1 = Select(Addr); 867 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 868 return true; 869} 870 871SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 872 SDNode *N = Op.Val; 873 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 874 N->getOpcode() < V8ISD::FIRST_NUMBER) 875 return Op; // Already selected. 876 // If this has already been converted, use it. 877 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 878 if (CGMI != CodeGenMap.end()) return CGMI->second; 879 880 switch (N->getOpcode()) { 881 default: break; 882 case ISD::FrameIndex: { 883 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 884 if (N->hasOneUse()) 885 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 886 CurDAG->getTargetFrameIndex(FI, MVT::i32), 887 CurDAG->getTargetConstant(0, MVT::i32)); 888 return CodeGenMap[Op] = 889 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 890 CurDAG->getTargetFrameIndex(FI, MVT::i32), 891 CurDAG->getTargetConstant(0, MVT::i32)); 892 } 893 case V8ISD::CMPICC: { 894 // FIXME: Handle compare with immediate. 895 SDOperand LHS = Select(N->getOperand(0)); 896 SDOperand RHS = Select(N->getOperand(1)); 897 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 898 LHS, RHS); 899 return CodeGenMap[Op] = Result.getValue(1); 900 } 901 case ISD::ADD_PARTS: { 902 SDOperand LHSL = Select(N->getOperand(0)); 903 SDOperand LHSH = Select(N->getOperand(1)); 904 SDOperand RHSL = Select(N->getOperand(2)); 905 SDOperand RHSH = Select(N->getOperand(3)); 906 // FIXME, handle immediate RHS. 907 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 908 LHSL, RHSL); 909 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 910 Low.getValue(1)); 911 CodeGenMap[SDOperand(N, 0)] = Low; 912 CodeGenMap[SDOperand(N, 1)] = Hi; 913 return Op.ResNo ? Hi : Low; 914 } 915 case ISD::SUB_PARTS: { 916 SDOperand LHSL = Select(N->getOperand(0)); 917 SDOperand LHSH = Select(N->getOperand(1)); 918 SDOperand RHSL = Select(N->getOperand(2)); 919 SDOperand RHSH = Select(N->getOperand(3)); 920 // FIXME, handle immediate RHS. 921 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 922 LHSL, RHSL); 923 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 924 Low.getValue(1)); 925 CodeGenMap[SDOperand(N, 0)] = Low; 926 CodeGenMap[SDOperand(N, 1)] = Hi; 927 return Op.ResNo ? Hi : Low; 928 } 929 case ISD::SDIV: 930 case ISD::UDIV: { 931 // FIXME: should use a custom expander to expose the SRA to the dag. 932 SDOperand DivLHS = Select(N->getOperand(0)); 933 SDOperand DivRHS = Select(N->getOperand(1)); 934 935 // Set the Y register to the high-part. 936 SDOperand TopPart; 937 if (N->getOpcode() == ISD::SDIV) { 938 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 939 CurDAG->getTargetConstant(31, MVT::i32)); 940 } else { 941 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 942 } 943 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 944 CurDAG->getRegister(V8::G0, MVT::i32)); 945 946 // FIXME: Handle div by immediate. 947 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 948 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 949 } 950 case ISD::MULHU: 951 case ISD::MULHS: { 952 // FIXME: Handle mul by immediate. 953 SDOperand MulLHS = Select(N->getOperand(0)); 954 SDOperand MulRHS = Select(N->getOperand(1)); 955 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 956 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 957 MulLHS, MulRHS); 958 // The high part is in the Y register. 959 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 960 } 961 case ISD::CALL: 962 // FIXME: This is a workaround for a bug in tblgen. 963 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 964 // Emits: (CALL:void (tglobaladdr:i32):$dst) 965 // Pattern complexity = 2 cost = 1 966 SDOperand N1 = N->getOperand(1); 967 if (N1.getOpcode() != ISD::TargetGlobalAddress) goto P47Fail; 968 SDOperand InFlag = SDOperand(0, 0); 969 SDOperand Chain = N->getOperand(0); 970 SDOperand Tmp0 = N1; 971 Chain = Select(Chain); 972 SDOperand Result; 973 if (N->getNumOperands() == 3) { 974 InFlag = Select(N->getOperand(2)); 975 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 976 Chain, InFlag); 977 } else { 978 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 979 Chain); 980 } 981 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 982 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 983 return Result.getValue(Op.ResNo); 984 } 985 P47Fail:; 986 987 } 988 989 return SelectCode(Op); 990} 991 992 993/// createPPCISelDag - This pass converts a legalized DAG into a 994/// PowerPC-specific DAG, ready for instruction scheduling. 995/// 996FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 997 return new SparcV8DAGToDAGISel(TM); 998} 999