SparcISelDAGToDAG.cpp revision ee625573b5b39b91441fc6ea23f3ba415abdc71f 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Support/Debug.h"
26#include <iostream>
27using namespace llvm;
28
29//===----------------------------------------------------------------------===//
30// TargetLowering Implementation
31//===----------------------------------------------------------------------===//
32
33namespace V8ISD {
34  enum {
35    FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36    CMPICC,   // Compare two GPR operands, set icc.
37    CMPFCC,   // Compare two FP operands, set fcc.
38    BRICC,    // Branch to dest on icc condition
39    BRFCC,    // Branch to dest on fcc condition
40
41    Hi, Lo,   // Hi/Lo operations, typically on a global address.
42
43    FTOI,     // FP to Int within a FP register.
44    ITOF,     // Int to FP within a FP register.
45
46    SELECT_ICC, // Select between two values using the current ICC flags.
47    SELECT_FCC, // Select between two values using the current FCC flags.
48
49    RET_FLAG,   // Return with a flag operand.
50  };
51}
52
53namespace {
54  class SparcV8TargetLowering : public TargetLowering {
55    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
56  public:
57    SparcV8TargetLowering(TargetMachine &TM);
58    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59    virtual std::vector<SDOperand>
60      LowerArguments(Function &F, SelectionDAG &DAG);
61    virtual std::pair<SDOperand, SDOperand>
62      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
63                  unsigned CC,
64                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
65                  SelectionDAG &DAG);
66    virtual std::pair<SDOperand, SDOperand>
67      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
68                              SelectionDAG &DAG);
69    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
70                                                       MachineBasicBlock *MBB);
71
72    virtual const char *getTargetNodeName(unsigned Opcode) const;
73  };
74}
75
76SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
77  : TargetLowering(TM) {
78
79  // Set up the register classes.
80  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
81  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
82  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
83
84  // Custom legalize GlobalAddress nodes into LO/HI parts.
85  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
86  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
87
88  // Sparc doesn't have sext_inreg, replace them with shl/sra
89  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
90  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
91  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
92
93  // Sparc has no REM operation.
94  setOperationAction(ISD::UREM, MVT::i32, Expand);
95  setOperationAction(ISD::SREM, MVT::i32, Expand);
96
97  // Custom expand fp<->sint
98  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
99  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
100
101  // Expand fp<->uint
102  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
103  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
104
105  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
106  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
107
108  // Turn FP extload into load/fextend
109  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
110
111  // Sparc has no select or setcc: expand to SELECT_CC.
112  setOperationAction(ISD::SELECT, MVT::i32, Expand);
113  setOperationAction(ISD::SELECT, MVT::f32, Expand);
114  setOperationAction(ISD::SELECT, MVT::f64, Expand);
115  setOperationAction(ISD::SETCC, MVT::i32, Expand);
116  setOperationAction(ISD::SETCC, MVT::f32, Expand);
117  setOperationAction(ISD::SETCC, MVT::f64, Expand);
118
119  // Sparc doesn't have BRCOND either, it has BR_CC.
120  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
121  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
122  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
123  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
124  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
125  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
126
127  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
128  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
129  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
130
131  // V8 has no intrinsics for these particular operations.
132  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
133  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
134  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
135
136  setOperationAction(ISD::FSIN , MVT::f64, Expand);
137  setOperationAction(ISD::FCOS , MVT::f64, Expand);
138  setOperationAction(ISD::FSIN , MVT::f32, Expand);
139  setOperationAction(ISD::FCOS , MVT::f32, Expand);
140  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
141  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
142  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
143  setOperationAction(ISD::ROTL , MVT::i32, Expand);
144  setOperationAction(ISD::ROTR , MVT::i32, Expand);
145  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
146
147  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
148  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
149  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
150
151  // We don't have line number support yet.
152  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
153  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
154  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
155
156  // RET must be custom lowered, to meet ABI requirements
157  setOperationAction(ISD::RET               , MVT::Other, Custom);
158
159  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
160  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
161
162  // Use the default implementation.
163  setOperationAction(ISD::VAARG             , MVT::Other, Expand);
164  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
165  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
166  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
167  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
168  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
169
170  setStackPointerRegisterToSaveRestore(V8::O6);
171
172  computeRegisterProperties();
173}
174
175const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
176  switch (Opcode) {
177  default: return 0;
178  case V8ISD::CMPICC:     return "V8ISD::CMPICC";
179  case V8ISD::CMPFCC:     return "V8ISD::CMPFCC";
180  case V8ISD::BRICC:      return "V8ISD::BRICC";
181  case V8ISD::BRFCC:      return "V8ISD::BRFCC";
182  case V8ISD::Hi:         return "V8ISD::Hi";
183  case V8ISD::Lo:         return "V8ISD::Lo";
184  case V8ISD::FTOI:       return "V8ISD::FTOI";
185  case V8ISD::ITOF:       return "V8ISD::ITOF";
186  case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
187  case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
188  case V8ISD::RET_FLAG:   return "V8ISD::RET_FLAG";
189  }
190}
191
192/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
193/// either one or two GPRs, including FP values.  TODO: we should pass FP values
194/// in FP registers for fastcc functions.
195std::vector<SDOperand>
196SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
197  MachineFunction &MF = DAG.getMachineFunction();
198  SSARegMap *RegMap = MF.getSSARegMap();
199  std::vector<SDOperand> ArgValues;
200
201  static const unsigned ArgRegs[] = {
202    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
203  };
204
205  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
206  unsigned ArgOffset = 68;
207
208  SDOperand Root = DAG.getRoot();
209  std::vector<SDOperand> OutChains;
210
211  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
212    MVT::ValueType ObjectVT = getValueType(I->getType());
213
214    switch (ObjectVT) {
215    default: assert(0 && "Unhandled argument type!");
216    case MVT::i1:
217    case MVT::i8:
218    case MVT::i16:
219    case MVT::i32:
220      if (I->use_empty()) {                // Argument is dead.
221        if (CurArgReg < ArgRegEnd) ++CurArgReg;
222        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
223      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
224        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
225        MF.addLiveIn(*CurArgReg++, VReg);
226        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
227        if (ObjectVT != MVT::i32) {
228          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
229                                                       : ISD::AssertZext;
230          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
231                            DAG.getValueType(ObjectVT));
232          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
233        }
234        ArgValues.push_back(Arg);
235      } else {
236        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
237        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
238        SDOperand Load;
239        if (ObjectVT == MVT::i32) {
240          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
241        } else {
242          unsigned LoadOp =
243            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
244
245          // Sparc is big endian, so add an offset based on the ObjectVT.
246          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
247          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
248                              DAG.getConstant(Offset, MVT::i32));
249          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
250                                DAG.getSrcValue(0), ObjectVT);
251          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
252        }
253        ArgValues.push_back(Load);
254      }
255
256      ArgOffset += 4;
257      break;
258    case MVT::f32:
259      if (I->use_empty()) {                // Argument is dead.
260        if (CurArgReg < ArgRegEnd) ++CurArgReg;
261        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
262      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
263        // FP value is passed in an integer register.
264        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
265        MF.addLiveIn(*CurArgReg++, VReg);
266        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
267
268        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
269        ArgValues.push_back(Arg);
270      } else {
271        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
272        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
273        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
274        ArgValues.push_back(Load);
275      }
276      ArgOffset += 4;
277      break;
278
279    case MVT::i64:
280    case MVT::f64:
281      if (I->use_empty()) {                // Argument is dead.
282        if (CurArgReg < ArgRegEnd) ++CurArgReg;
283        if (CurArgReg < ArgRegEnd) ++CurArgReg;
284        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
285      } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
286                 ((CurArgReg-ArgRegs) & 1) == 0) {
287        // If this is a double argument and the whole thing lives on the stack,
288        // and the argument is aligned, load the double straight from the stack.
289        // We can't do a load in cases like void foo([6ints], int,double),
290        // because the double wouldn't be aligned!
291        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
292        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
293        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
294                                        DAG.getSrcValue(0)));
295      } else {
296        SDOperand HiVal;
297        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
298          unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
299          MF.addLiveIn(*CurArgReg++, VRegHi);
300          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
301        } else {
302          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
303          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
304          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
305        }
306
307        SDOperand LoVal;
308        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
309          unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
310          MF.addLiveIn(*CurArgReg++, VRegLo);
311          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
312        } else {
313          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
314          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
315          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
316        }
317
318        // Compose the two halves together into an i64 unit.
319        SDOperand WholeValue =
320          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
321
322        // If we want a double, do a bit convert.
323        if (ObjectVT == MVT::f64)
324          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
325
326        ArgValues.push_back(WholeValue);
327      }
328      ArgOffset += 8;
329      break;
330    }
331  }
332
333  // Store remaining ArgRegs to the stack if this is a varargs function.
334  if (F.getFunctionType()->isVarArg()) {
335    // Remember the vararg offset for the va_start implementation.
336    VarArgsFrameOffset = ArgOffset;
337
338    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
339      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
340      MF.addLiveIn(*CurArgReg, VReg);
341      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
342
343      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
344      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
345
346      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
347                                      Arg, FIPtr, DAG.getSrcValue(0)));
348      ArgOffset += 4;
349    }
350  }
351
352  if (!OutChains.empty())
353    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
354
355  // Finally, inform the code generator which regs we return values in.
356  switch (getValueType(F.getReturnType())) {
357  default: assert(0 && "Unknown type!");
358  case MVT::isVoid: break;
359  case MVT::i1:
360  case MVT::i8:
361  case MVT::i16:
362  case MVT::i32:
363    MF.addLiveOut(V8::I0);
364    break;
365  case MVT::i64:
366    MF.addLiveOut(V8::I0);
367    MF.addLiveOut(V8::I1);
368    break;
369  case MVT::f32:
370    MF.addLiveOut(V8::F0);
371    break;
372  case MVT::f64:
373    MF.addLiveOut(V8::D0);
374    break;
375  }
376
377  return ArgValues;
378}
379
380std::pair<SDOperand, SDOperand>
381SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
382                                   bool isVarArg, unsigned CC,
383                                   bool isTailCall, SDOperand Callee,
384                                   ArgListTy &Args, SelectionDAG &DAG) {
385  MachineFunction &MF = DAG.getMachineFunction();
386  // Count the size of the outgoing arguments.
387  unsigned ArgsSize = 0;
388  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
389    switch (getValueType(Args[i].second)) {
390    default: assert(0 && "Unknown value type!");
391    case MVT::i1:
392    case MVT::i8:
393    case MVT::i16:
394    case MVT::i32:
395    case MVT::f32:
396      ArgsSize += 4;
397      break;
398    case MVT::i64:
399    case MVT::f64:
400      ArgsSize += 8;
401      break;
402    }
403  }
404  if (ArgsSize > 4*6)
405    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
406  else
407    ArgsSize = 0;
408
409  // Keep stack frames 8-byte aligned.
410  ArgsSize = (ArgsSize+7) & ~7;
411
412  Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
413                      DAG.getConstant(ArgsSize, getPointerTy()));
414
415  SDOperand StackPtr, NullSV;
416  std::vector<SDOperand> Stores;
417  std::vector<SDOperand> RegValuesToPass;
418  unsigned ArgOffset = 68;
419  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
420    SDOperand Val = Args[i].first;
421    MVT::ValueType ObjectVT = Val.getValueType();
422    SDOperand ValToStore(0, 0);
423    unsigned ObjSize;
424    switch (ObjectVT) {
425    default: assert(0 && "Unhandled argument type!");
426    case MVT::i1:
427    case MVT::i8:
428    case MVT::i16:
429      // Promote the integer to 32-bits.  If the input type is signed, use a
430      // sign extend, otherwise use a zero extend.
431      if (Args[i].second->isSigned())
432        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
433      else
434        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
435      // FALL THROUGH
436    case MVT::i32:
437      ObjSize = 4;
438
439      if (RegValuesToPass.size() >= 6) {
440        ValToStore = Val;
441      } else {
442        RegValuesToPass.push_back(Val);
443      }
444      break;
445    case MVT::f32:
446      ObjSize = 4;
447      if (RegValuesToPass.size() >= 6) {
448        ValToStore = Val;
449      } else {
450        // Convert this to a FP value in an int reg.
451        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
452        RegValuesToPass.push_back(Val);
453      }
454      break;
455    case MVT::f64:
456      ObjSize = 8;
457      // If we can store this directly into the outgoing slot, do so.  We can
458      // do this when all ArgRegs are used and if the outgoing slot is aligned.
459      // FIXME: McGill/misr fails with this.
460      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
461        ValToStore = Val;
462        break;
463      }
464
465      // Otherwise, convert this to a FP value in int regs.
466      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
467      // FALL THROUGH
468    case MVT::i64:
469      ObjSize = 8;
470      if (RegValuesToPass.size() >= 6) {
471        ValToStore = Val;    // Whole thing is passed in memory.
472        break;
473      }
474
475      // Split the value into top and bottom part.  Top part goes in a reg.
476      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
477                                 DAG.getConstant(1, MVT::i32));
478      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
479                                 DAG.getConstant(0, MVT::i32));
480      RegValuesToPass.push_back(Hi);
481
482      if (RegValuesToPass.size() >= 6) {
483        ValToStore = Lo;
484        ArgOffset += 4;
485        ObjSize = 4;
486      } else {
487        RegValuesToPass.push_back(Lo);
488      }
489      break;
490    }
491
492    if (ValToStore.Val) {
493      if (!StackPtr.Val) {
494        StackPtr = DAG.getRegister(V8::O6, MVT::i32);
495        NullSV = DAG.getSrcValue(NULL);
496      }
497      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
498      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
499      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
500                                   ValToStore, PtrOff, NullSV));
501    }
502    ArgOffset += ObjSize;
503  }
504
505  // Emit all stores, make sure the occur before any copies into physregs.
506  if (!Stores.empty())
507    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
508
509  static const unsigned ArgRegs[] = {
510    V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
511  };
512
513  // Build a sequence of copy-to-reg nodes chained together with token chain
514  // and flag operands which copy the outgoing args into O[0-5].
515  SDOperand InFlag;
516  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
517    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
518    InFlag = Chain.getValue(1);
519  }
520
521  // If the callee is a GlobalAddress node (quite common, every direct call is)
522  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
523  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
524    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
525
526  std::vector<MVT::ValueType> NodeTys;
527  NodeTys.push_back(MVT::Other);   // Returns a chain
528  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
529  if (InFlag.Val)
530    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
531  else
532    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
533  InFlag = Chain.getValue(1);
534
535  MVT::ValueType RetTyVT = getValueType(RetTy);
536  SDOperand RetVal;
537  if (RetTyVT != MVT::isVoid) {
538    switch (RetTyVT) {
539    default: assert(0 && "Unknown value type to return!");
540    case MVT::i1:
541    case MVT::i8:
542    case MVT::i16:
543      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
544      Chain = RetVal.getValue(1);
545
546      // Add a note to keep track of whether it is sign or zero extended.
547      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
548                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
549      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
550      break;
551    case MVT::i32:
552      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
553      Chain = RetVal.getValue(1);
554      break;
555    case MVT::f32:
556      RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
557      Chain = RetVal.getValue(1);
558      break;
559    case MVT::f64:
560      RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
561      Chain = RetVal.getValue(1);
562      break;
563    case MVT::i64:
564      SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
565      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
566                                        Lo.getValue(2));
567      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
568      Chain = Hi.getValue(1);
569      break;
570    }
571  }
572
573  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
574                      DAG.getConstant(ArgsSize, getPointerTy()));
575
576  return std::make_pair(RetVal, Chain);
577}
578
579std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
580LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
581                        SelectionDAG &DAG) {
582  assert(0 && "Unimp");
583  abort();
584}
585
586SDOperand SparcV8TargetLowering::
587LowerOperation(SDOperand Op, SelectionDAG &DAG) {
588  switch (Op.getOpcode()) {
589  default: assert(0 && "Should not custom lower this!");
590  case ISD::GlobalAddress: {
591    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
592    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
593    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
594    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
595    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
596  }
597  case ISD::ConstantPool: {
598    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
599    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
600    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
601    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
602    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
603  }
604  case ISD::FP_TO_SINT:
605    // Convert the fp value to integer in an FP register.
606    assert(Op.getValueType() == MVT::i32);
607    Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
608    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
609  case ISD::SINT_TO_FP: {
610    assert(Op.getOperand(0).getValueType() == MVT::i32);
611    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
612    // Convert the int value to FP in an FP register.
613    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
614  }
615  case ISD::BR_CC: {
616    SDOperand Chain = Op.getOperand(0);
617    SDOperand CC = Op.getOperand(1);
618    SDOperand LHS = Op.getOperand(2);
619    SDOperand RHS = Op.getOperand(3);
620    SDOperand Dest = Op.getOperand(4);
621
622    // Get the condition flag.
623    if (LHS.getValueType() == MVT::i32) {
624      std::vector<MVT::ValueType> VTs;
625      VTs.push_back(MVT::i32);
626      VTs.push_back(MVT::Flag);
627      std::vector<SDOperand> Ops;
628      Ops.push_back(LHS);
629      Ops.push_back(RHS);
630      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
631      return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
632    } else {
633      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
634      return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
635    }
636  }
637  case ISD::SELECT_CC: {
638    SDOperand LHS = Op.getOperand(0);
639    SDOperand RHS = Op.getOperand(1);
640    unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
641    SDOperand TrueVal = Op.getOperand(2);
642    SDOperand FalseVal = Op.getOperand(3);
643
644    SDOperand CompareFlag;
645    unsigned Opc;
646    if (LHS.getValueType() == MVT::i32) {
647      std::vector<MVT::ValueType> VTs;
648      VTs.push_back(LHS.getValueType());   // subcc returns a value
649      VTs.push_back(MVT::Flag);
650      std::vector<SDOperand> Ops;
651      Ops.push_back(LHS);
652      Ops.push_back(RHS);
653      CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
654      Opc = V8ISD::SELECT_ICC;
655    } else {
656      CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
657      Opc = V8ISD::SELECT_FCC;
658    }
659    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
660                       DAG.getConstant(CC, MVT::i32), CompareFlag);
661  }
662  case ISD::VASTART: {
663    // vastart just stores the address of the VarArgsFrameIndex slot into the
664    // memory location argument.
665    SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
666                                   DAG.getRegister(V8::I6, MVT::i32),
667                                   DAG.getConstant(VarArgsFrameOffset, MVT::i32));
668    return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
669                       Op.getOperand(1), Op.getOperand(2));
670  }
671  case ISD::RET: {
672    SDOperand Copy;
673
674    switch(Op.getNumOperands()) {
675    default:
676      assert(0 && "Do not know how to return this many arguments!");
677      abort();
678    case 1:
679      return SDOperand(); // ret void is legal
680    case 2: {
681      unsigned ArgReg;
682      switch(Op.getOperand(1).getValueType()) {
683      default: assert(0 && "Unknown type to return!");
684      case MVT::i32: ArgReg = V8::I0; break;
685      case MVT::f32: ArgReg = V8::F0; break;
686      case MVT::f64: ArgReg = V8::D0; break;
687      }
688      Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
689                              SDOperand());
690      break;
691    }
692    case 3:
693      Copy = DAG.getCopyToReg(Op.getOperand(0), V8::I0, Op.getOperand(2),
694                              SDOperand());
695      Copy = DAG.getCopyToReg(Copy, V8::I1, Op.getOperand(1), Copy.getValue(1));
696      break;
697    }
698    return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
699  }
700  }
701}
702
703MachineBasicBlock *
704SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
705                                               MachineBasicBlock *BB) {
706  unsigned BROpcode;
707  // Figure out the conditional branch opcode to use for this select_cc.
708  switch (MI->getOpcode()) {
709  default: assert(0 && "Unknown SELECT_CC!");
710  case V8::SELECT_CC_Int_ICC:
711  case V8::SELECT_CC_FP_ICC:
712  case V8::SELECT_CC_DFP_ICC:
713    // Integer compare.
714    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
715    default: assert(0 && "Unknown integer condition code!");
716    case ISD::SETEQ:  BROpcode = V8::BE; break;
717    case ISD::SETNE:  BROpcode = V8::BNE; break;
718    case ISD::SETLT:  BROpcode = V8::BL; break;
719    case ISD::SETGT:  BROpcode = V8::BG; break;
720    case ISD::SETLE:  BROpcode = V8::BLE; break;
721    case ISD::SETGE:  BROpcode = V8::BGE; break;
722    case ISD::SETULT: BROpcode = V8::BCS; break;
723    case ISD::SETULE: BROpcode = V8::BLEU; break;
724    case ISD::SETUGT: BROpcode = V8::BGU; break;
725    case ISD::SETUGE: BROpcode = V8::BCC; break;
726    }
727    break;
728  case V8::SELECT_CC_Int_FCC:
729  case V8::SELECT_CC_FP_FCC:
730  case V8::SELECT_CC_DFP_FCC:
731    // FP compare.
732    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
733    default: assert(0 && "Unknown fp condition code!");
734    case ISD::SETEQ:  BROpcode = V8::FBE; break;
735    case ISD::SETNE:  BROpcode = V8::FBNE; break;
736    case ISD::SETLT:  BROpcode = V8::FBL; break;
737    case ISD::SETGT:  BROpcode = V8::FBG; break;
738    case ISD::SETLE:  BROpcode = V8::FBLE; break;
739    case ISD::SETGE:  BROpcode = V8::FBGE; break;
740    case ISD::SETULT: BROpcode = V8::FBUL; break;
741    case ISD::SETULE: BROpcode = V8::FBULE; break;
742    case ISD::SETUGT: BROpcode = V8::FBUG; break;
743    case ISD::SETUGE: BROpcode = V8::FBUGE; break;
744    case ISD::SETUO:  BROpcode = V8::FBU; break;
745    case ISD::SETO:   BROpcode = V8::FBO; break;
746    case ISD::SETONE: BROpcode = V8::FBLG; break;
747    case ISD::SETUEQ: BROpcode = V8::FBUE; break;
748    }
749    break;
750  }
751
752  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
753  // control-flow pattern.  The incoming instruction knows the destination vreg
754  // to set, the condition code register to branch on, the true/false values to
755  // select between, and a branch opcode to use.
756  const BasicBlock *LLVM_BB = BB->getBasicBlock();
757  ilist<MachineBasicBlock>::iterator It = BB;
758  ++It;
759
760  //  thisMBB:
761  //  ...
762  //   TrueVal = ...
763  //   [f]bCC copy1MBB
764  //   fallthrough --> copy0MBB
765  MachineBasicBlock *thisMBB = BB;
766  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
767  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
768  BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
769  MachineFunction *F = BB->getParent();
770  F->getBasicBlockList().insert(It, copy0MBB);
771  F->getBasicBlockList().insert(It, sinkMBB);
772  // Update machine-CFG edges
773  BB->addSuccessor(copy0MBB);
774  BB->addSuccessor(sinkMBB);
775
776  //  copy0MBB:
777  //   %FalseValue = ...
778  //   # fallthrough to sinkMBB
779  BB = copy0MBB;
780
781  // Update machine-CFG edges
782  BB->addSuccessor(sinkMBB);
783
784  //  sinkMBB:
785  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
786  //  ...
787  BB = sinkMBB;
788  BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
789    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
790    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
791
792  delete MI;   // The pseudo instruction is gone now.
793  return BB;
794}
795
796//===----------------------------------------------------------------------===//
797// Instruction Selector Implementation
798//===----------------------------------------------------------------------===//
799
800//===--------------------------------------------------------------------===//
801/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
802/// instructions for SelectionDAG operations.
803///
804namespace {
805class SparcV8DAGToDAGISel : public SelectionDAGISel {
806  SparcV8TargetLowering V8Lowering;
807public:
808  SparcV8DAGToDAGISel(TargetMachine &TM)
809    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
810
811  SDOperand Select(SDOperand Op);
812
813  // Complex Pattern Selectors.
814  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
815  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
816
817  /// InstructionSelectBasicBlock - This callback is invoked by
818  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
819  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
820
821  virtual const char *getPassName() const {
822    return "SparcV8 DAG->DAG Pattern Instruction Selection";
823  }
824
825  // Include the pieces autogenerated from the target description.
826#include "SparcV8GenDAGISel.inc"
827};
828}  // end anonymous namespace
829
830/// InstructionSelectBasicBlock - This callback is invoked by
831/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
832void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
833  DEBUG(BB->dump());
834
835  // Select target instructions for the DAG.
836  DAG.setRoot(Select(DAG.getRoot()));
837  CodeGenMap.clear();
838  DAG.RemoveDeadNodes();
839
840  // Emit machine code to BB.
841  ScheduleAndEmitDAG(DAG);
842}
843
844bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
845                                       SDOperand &Offset) {
846  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
847    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
848    Offset = CurDAG->getTargetConstant(0, MVT::i32);
849    return true;
850  }
851
852  if (Addr.getOpcode() == ISD::ADD) {
853    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
854      if (Predicate_simm13(CN)) {
855        if (FrameIndexSDNode *FIN =
856                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
857          // Constant offset from frame ref.
858          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
859        } else {
860          Base = Select(Addr.getOperand(0));
861        }
862        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
863        return true;
864      }
865    }
866    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
867      Base = Select(Addr.getOperand(1));
868      Offset = Addr.getOperand(0).getOperand(0);
869      return true;
870    }
871    if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
872      Base = Select(Addr.getOperand(0));
873      Offset = Addr.getOperand(1).getOperand(0);
874      return true;
875    }
876  }
877  Base = Select(Addr);
878  Offset = CurDAG->getTargetConstant(0, MVT::i32);
879  return true;
880}
881
882bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
883                                       SDOperand &R2) {
884  if (Addr.getOpcode() == ISD::FrameIndex) return false;
885  if (Addr.getOpcode() == ISD::ADD) {
886    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
887        Predicate_simm13(Addr.getOperand(1).Val))
888      return false;  // Let the reg+imm pattern catch this!
889    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
890        Addr.getOperand(1).getOpcode() == V8ISD::Lo)
891      return false;  // Let the reg+imm pattern catch this!
892    R1 = Select(Addr.getOperand(0));
893    R2 = Select(Addr.getOperand(1));
894    return true;
895  }
896
897  R1 = Select(Addr);
898  R2 = CurDAG->getRegister(V8::G0, MVT::i32);
899  return true;
900}
901
902SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
903  SDNode *N = Op.Val;
904  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
905      N->getOpcode() < V8ISD::FIRST_NUMBER)
906    return Op;   // Already selected.
907                 // If this has already been converted, use it.
908  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
909  if (CGMI != CodeGenMap.end()) return CGMI->second;
910
911  switch (N->getOpcode()) {
912  default: break;
913  case ISD::FrameIndex: {
914    int FI = cast<FrameIndexSDNode>(N)->getIndex();
915    if (N->hasOneUse())
916      return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
917                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
918                                  CurDAG->getTargetConstant(0, MVT::i32));
919    return CodeGenMap[Op] =
920      CurDAG->getTargetNode(V8::ADDri, MVT::i32,
921                            CurDAG->getTargetFrameIndex(FI, MVT::i32),
922                            CurDAG->getTargetConstant(0, MVT::i32));
923  }
924  case ISD::ADD_PARTS: {
925    SDOperand LHSL = Select(N->getOperand(0));
926    SDOperand LHSH = Select(N->getOperand(1));
927    SDOperand RHSL = Select(N->getOperand(2));
928    SDOperand RHSH = Select(N->getOperand(3));
929    // FIXME, handle immediate RHS.
930    SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
931                                          LHSL, RHSL);
932    SDOperand Hi  = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
933                                          Low.getValue(1));
934    CodeGenMap[SDOperand(N, 0)] = Low;
935    CodeGenMap[SDOperand(N, 1)] = Hi;
936    return Op.ResNo ? Hi : Low;
937  }
938  case ISD::SUB_PARTS: {
939    SDOperand LHSL = Select(N->getOperand(0));
940    SDOperand LHSH = Select(N->getOperand(1));
941    SDOperand RHSL = Select(N->getOperand(2));
942    SDOperand RHSH = Select(N->getOperand(3));
943    // FIXME, handle immediate RHS.
944    SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
945                                          LHSL, RHSL);
946    SDOperand Hi  = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
947                                          Low.getValue(1));
948    CodeGenMap[SDOperand(N, 0)] = Low;
949    CodeGenMap[SDOperand(N, 1)] = Hi;
950    return Op.ResNo ? Hi : Low;
951  }
952  case ISD::SDIV:
953  case ISD::UDIV: {
954    // FIXME: should use a custom expander to expose the SRA to the dag.
955    SDOperand DivLHS = Select(N->getOperand(0));
956    SDOperand DivRHS = Select(N->getOperand(1));
957
958    // Set the Y register to the high-part.
959    SDOperand TopPart;
960    if (N->getOpcode() == ISD::SDIV) {
961      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
962                                      CurDAG->getTargetConstant(31, MVT::i32));
963    } else {
964      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
965    }
966    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
967                                    CurDAG->getRegister(V8::G0, MVT::i32));
968
969    // FIXME: Handle div by immediate.
970    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
971    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
972  }
973  case ISD::MULHU:
974  case ISD::MULHS: {
975    // FIXME: Handle mul by immediate.
976    SDOperand MulLHS = Select(N->getOperand(0));
977    SDOperand MulRHS = Select(N->getOperand(1));
978    unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
979    SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
980                                          MulLHS, MulRHS);
981    // The high part is in the Y register.
982    return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
983  }
984  case ISD::CALL:
985    // FIXME: This is a workaround for a bug in tblgen.
986  { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
987    // Emits: (CALL:void (tglobaladdr:i32):$dst)
988    // Pattern complexity = 2  cost = 1
989    SDOperand N1 = N->getOperand(1);
990    if (N1.getOpcode() != ISD::TargetGlobalAddress &&
991        N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
992    SDOperand InFlag = SDOperand(0, 0);
993    SDOperand Chain = N->getOperand(0);
994    SDOperand Tmp0 = N1;
995    Chain = Select(Chain);
996    SDOperand Result;
997    if (N->getNumOperands() == 3) {
998      InFlag = Select(N->getOperand(2));
999      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1000                                     Chain, InFlag);
1001    } else {
1002      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1003                                     Chain);
1004    }
1005    Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
1006     CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
1007    return Result.getValue(Op.ResNo);
1008  }
1009    P47Fail:;
1010
1011  }
1012
1013  return SelectCode(Op);
1014}
1015
1016
1017/// createSparcV8ISelDag - This pass converts a legalized DAG into a
1018/// SPARC-specific DAG, ready for instruction scheduling.
1019///
1020FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1021  return new SparcV8DAGToDAGISel(TM);
1022}
1023