SparcISelLowering.cpp revision 41d59c61307002823c246c14589048266a6bf423
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcMachineFunctionInfo.h" 17#include "SparcTargetMachine.h" 18#include "llvm/CodeGen/CallingConvLower.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 25#include "llvm/IR/DerivedTypes.h" 26#include "llvm/IR/Function.h" 27#include "llvm/IR/Module.h" 28#include "llvm/Support/ErrorHandling.h" 29using namespace llvm; 30 31 32//===----------------------------------------------------------------------===// 33// Calling Convention Implementation 34//===----------------------------------------------------------------------===// 35 36static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 37 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 38 ISD::ArgFlagsTy &ArgFlags, CCState &State) 39{ 40 assert (ArgFlags.isSRet()); 41 42 //Assign SRet argument 43 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 44 0, 45 LocVT, LocInfo)); 46 return true; 47} 48 49static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 50 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 51 ISD::ArgFlagsTy &ArgFlags, CCState &State) 52{ 53 static const uint16_t RegList[] = { 54 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 55 }; 56 //Try to get first reg 57 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 58 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 59 } else { 60 //Assign whole thing in stack 61 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 62 State.AllocateStack(8,4), 63 LocVT, LocInfo)); 64 return true; 65 } 66 67 //Try to get second reg 68 if (unsigned Reg = State.AllocateReg(RegList, 6)) 69 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 70 else 71 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 72 State.AllocateStack(4,4), 73 LocVT, LocInfo)); 74 return true; 75} 76 77// Allocate a full-sized argument for the 64-bit ABI. 78static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, 79 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 80 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 81 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) && 82 "Can't handle non-64 bits locations"); 83 84 // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. 85 unsigned Offset = State.AllocateStack(8, 8); 86 unsigned Reg = 0; 87 88 if (LocVT == MVT::i64 && Offset < 6*8) 89 // Promote integers to %i0-%i5. 90 Reg = SP::I0 + Offset/8; 91 else if (LocVT == MVT::f64 && Offset < 16*8) 92 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). 93 Reg = SP::D0 + Offset/8; 94 else if (LocVT == MVT::f32 && Offset < 16*8) 95 // Promote floats to %f1, %f3, ... 96 Reg = SP::F1 + Offset/4; 97 98 // Promote to register when possible, otherwise use the stack slot. 99 if (Reg) { 100 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 101 return true; 102 } 103 104 // This argument goes on the stack in an 8-byte slot. 105 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to 106 // the right-aligned float. The first 4 bytes of the stack slot are undefined. 107 if (LocVT == MVT::f32) 108 Offset += 4; 109 110 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 111 return true; 112} 113 114// Allocate a half-sized argument for the 64-bit ABI. 115// 116// This is used when passing { float, int } structs by value in registers. 117static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, 118 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 119 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 120 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); 121 unsigned Offset = State.AllocateStack(4, 4); 122 123 if (LocVT == MVT::f32 && Offset < 16*8) { 124 // Promote floats to %f0-%f31. 125 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, 126 LocVT, LocInfo)); 127 return true; 128 } 129 130 if (LocVT == MVT::i32 && Offset < 6*8) { 131 // Promote integers to %i0-%i5, using half the register. 132 unsigned Reg = SP::I0 + Offset/8; 133 LocVT = MVT::i64; 134 LocInfo = CCValAssign::AExt; 135 136 // Set the Custom bit if this i32 goes in the high bits of a register. 137 if (Offset % 8 == 0) 138 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, 139 LocVT, LocInfo)); 140 else 141 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 142 return true; 143 } 144 145 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 146 return true; 147} 148 149#include "SparcGenCallingConv.inc" 150 151// The calling conventions in SparcCallingConv.td are described in terms of the 152// callee's register window. This function translates registers to the 153// corresponding caller window %o register. 154static unsigned toCallerWindow(unsigned Reg) { 155 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); 156 if (Reg >= SP::I0 && Reg <= SP::I7) 157 return Reg - SP::I0 + SP::O0; 158 return Reg; 159} 160 161SDValue 162SparcTargetLowering::LowerReturn(SDValue Chain, 163 CallingConv::ID CallConv, bool IsVarArg, 164 const SmallVectorImpl<ISD::OutputArg> &Outs, 165 const SmallVectorImpl<SDValue> &OutVals, 166 DebugLoc DL, SelectionDAG &DAG) const { 167 if (Subtarget->is64Bit()) 168 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 169 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 170} 171 172SDValue 173SparcTargetLowering::LowerReturn_32(SDValue Chain, 174 CallingConv::ID CallConv, bool IsVarArg, 175 const SmallVectorImpl<ISD::OutputArg> &Outs, 176 const SmallVectorImpl<SDValue> &OutVals, 177 DebugLoc DL, SelectionDAG &DAG) const { 178 MachineFunction &MF = DAG.getMachineFunction(); 179 180 // CCValAssign - represent the assignment of the return value to locations. 181 SmallVector<CCValAssign, 16> RVLocs; 182 183 // CCState - Info about the registers and stack slot. 184 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 185 DAG.getTarget(), RVLocs, *DAG.getContext()); 186 187 // Analyze return values. 188 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 189 190 SDValue Flag; 191 SmallVector<SDValue, 4> RetOps(1, Chain); 192 // Make room for the return address offset. 193 RetOps.push_back(SDValue()); 194 195 // Copy the result values into the output registers. 196 for (unsigned i = 0; i != RVLocs.size(); ++i) { 197 CCValAssign &VA = RVLocs[i]; 198 assert(VA.isRegLoc() && "Can only return in registers!"); 199 200 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), 201 OutVals[i], Flag); 202 203 // Guarantee that all emitted copies are stuck together with flags. 204 Flag = Chain.getValue(1); 205 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 206 } 207 208 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot 209 // If the function returns a struct, copy the SRetReturnReg to I0 210 if (MF.getFunction()->hasStructRetAttr()) { 211 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 212 unsigned Reg = SFI->getSRetReturnReg(); 213 if (!Reg) 214 llvm_unreachable("sret virtual register not created in the entry block"); 215 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 216 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); 217 Flag = Chain.getValue(1); 218 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); 219 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 220 } 221 222 RetOps[0] = Chain; // Update chain. 223 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 224 225 // Add the flag if we have it. 226 if (Flag.getNode()) 227 RetOps.push_back(Flag); 228 229 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 230 &RetOps[0], RetOps.size()); 231} 232 233// Lower return values for the 64-bit ABI. 234// Return values are passed the exactly the same way as function arguments. 235SDValue 236SparcTargetLowering::LowerReturn_64(SDValue Chain, 237 CallingConv::ID CallConv, bool IsVarArg, 238 const SmallVectorImpl<ISD::OutputArg> &Outs, 239 const SmallVectorImpl<SDValue> &OutVals, 240 DebugLoc DL, SelectionDAG &DAG) const { 241 // CCValAssign - represent the assignment of the return value to locations. 242 SmallVector<CCValAssign, 16> RVLocs; 243 244 // CCState - Info about the registers and stack slot. 245 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 246 DAG.getTarget(), RVLocs, *DAG.getContext()); 247 248 // Analyze return values. 249 CCInfo.AnalyzeReturn(Outs, CC_Sparc64); 250 251 SDValue Flag; 252 SmallVector<SDValue, 4> RetOps(1, Chain); 253 254 // The second operand on the return instruction is the return address offset. 255 // The return address is always %i7+8 with the 64-bit ABI. 256 RetOps.push_back(DAG.getConstant(8, MVT::i32)); 257 258 // Copy the result values into the output registers. 259 for (unsigned i = 0; i != RVLocs.size(); ++i) { 260 CCValAssign &VA = RVLocs[i]; 261 assert(VA.isRegLoc() && "Can only return in registers!"); 262 SDValue OutVal = OutVals[i]; 263 264 // Integer return values must be sign or zero extended by the callee. 265 switch (VA.getLocInfo()) { 266 case CCValAssign::SExt: 267 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 268 break; 269 case CCValAssign::ZExt: 270 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); 271 break; 272 case CCValAssign::AExt: 273 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); 274 default: 275 break; 276 } 277 278 // The custom bit on an i32 return value indicates that it should be passed 279 // in the high bits of the register. 280 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 281 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 282 DAG.getConstant(32, MVT::i32)); 283 284 // The next value may go in the low bits of the same register. 285 // Handle both at once. 286 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { 287 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); 288 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); 289 // Skip the next value, it's already done. 290 ++i; 291 } 292 } 293 294 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); 295 296 // Guarantee that all emitted copies are stuck together with flags. 297 Flag = Chain.getValue(1); 298 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 299 } 300 301 RetOps[0] = Chain; // Update chain. 302 303 // Add the flag if we have it. 304 if (Flag.getNode()) 305 RetOps.push_back(Flag); 306 307 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 308 &RetOps[0], RetOps.size()); 309} 310 311SDValue SparcTargetLowering:: 312LowerFormalArguments(SDValue Chain, 313 CallingConv::ID CallConv, 314 bool IsVarArg, 315 const SmallVectorImpl<ISD::InputArg> &Ins, 316 DebugLoc DL, 317 SelectionDAG &DAG, 318 SmallVectorImpl<SDValue> &InVals) const { 319 if (Subtarget->is64Bit()) 320 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins, 321 DL, DAG, InVals); 322 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins, 323 DL, DAG, InVals); 324} 325 326/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are 327/// passed in either one or two GPRs, including FP values. TODO: we should 328/// pass FP values in FP registers for fastcc functions. 329SDValue SparcTargetLowering:: 330LowerFormalArguments_32(SDValue Chain, 331 CallingConv::ID CallConv, 332 bool isVarArg, 333 const SmallVectorImpl<ISD::InputArg> &Ins, 334 DebugLoc dl, 335 SelectionDAG &DAG, 336 SmallVectorImpl<SDValue> &InVals) const { 337 MachineFunction &MF = DAG.getMachineFunction(); 338 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 339 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 340 341 // Assign locations to all of the incoming arguments. 342 SmallVector<CCValAssign, 16> ArgLocs; 343 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 344 getTargetMachine(), ArgLocs, *DAG.getContext()); 345 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 346 347 const unsigned StackOffset = 92; 348 349 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 350 CCValAssign &VA = ArgLocs[i]; 351 352 if (i == 0 && Ins[i].Flags.isSRet()) { 353 //Get SRet from [%fp+64] 354 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 355 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 356 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 357 MachinePointerInfo(), 358 false, false, false, 0); 359 InVals.push_back(Arg); 360 continue; 361 } 362 363 if (VA.isRegLoc()) { 364 if (VA.needsCustom()) { 365 assert(VA.getLocVT() == MVT::f64); 366 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 367 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 368 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 369 370 assert(i+1 < e); 371 CCValAssign &NextVA = ArgLocs[++i]; 372 373 SDValue LoVal; 374 if (NextVA.isMemLoc()) { 375 int FrameIdx = MF.getFrameInfo()-> 376 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 377 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 378 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 379 MachinePointerInfo(), 380 false, false, false, 0); 381 } else { 382 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 383 &SP::IntRegsRegClass); 384 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 385 } 386 SDValue WholeValue = 387 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 388 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 389 InVals.push_back(WholeValue); 390 continue; 391 } 392 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 393 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 394 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 395 if (VA.getLocVT() == MVT::f32) 396 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 397 else if (VA.getLocVT() != MVT::i32) { 398 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 399 DAG.getValueType(VA.getLocVT())); 400 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 401 } 402 InVals.push_back(Arg); 403 continue; 404 } 405 406 assert(VA.isMemLoc()); 407 408 unsigned Offset = VA.getLocMemOffset()+StackOffset; 409 410 if (VA.needsCustom()) { 411 assert(VA.getValVT() == MVT::f64); 412 //If it is double-word aligned, just load. 413 if (Offset % 8 == 0) { 414 int FI = MF.getFrameInfo()->CreateFixedObject(8, 415 Offset, 416 true); 417 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 418 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 419 MachinePointerInfo(), 420 false,false, false, 0); 421 InVals.push_back(Load); 422 continue; 423 } 424 425 int FI = MF.getFrameInfo()->CreateFixedObject(4, 426 Offset, 427 true); 428 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 429 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 430 MachinePointerInfo(), 431 false, false, false, 0); 432 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 433 Offset+4, 434 true); 435 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 436 437 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 438 MachinePointerInfo(), 439 false, false, false, 0); 440 441 SDValue WholeValue = 442 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 443 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 444 InVals.push_back(WholeValue); 445 continue; 446 } 447 448 int FI = MF.getFrameInfo()->CreateFixedObject(4, 449 Offset, 450 true); 451 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 452 SDValue Load ; 453 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 454 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 455 MachinePointerInfo(), 456 false, false, false, 0); 457 } else { 458 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 459 // Sparc is big endian, so add an offset based on the ObjectVT. 460 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 461 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 462 DAG.getConstant(Offset, MVT::i32)); 463 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 464 MachinePointerInfo(), 465 VA.getValVT(), false, false,0); 466 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 467 } 468 InVals.push_back(Load); 469 } 470 471 if (MF.getFunction()->hasStructRetAttr()) { 472 //Copy the SRet Argument to SRetReturnReg 473 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 474 unsigned Reg = SFI->getSRetReturnReg(); 475 if (!Reg) { 476 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 477 SFI->setSRetReturnReg(Reg); 478 } 479 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 480 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 481 } 482 483 // Store remaining ArgRegs to the stack if this is a varargs function. 484 if (isVarArg) { 485 static const uint16_t ArgRegs[] = { 486 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 487 }; 488 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 489 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 490 unsigned ArgOffset = CCInfo.getNextStackOffset(); 491 if (NumAllocated == 6) 492 ArgOffset += StackOffset; 493 else { 494 assert(!ArgOffset); 495 ArgOffset = 68+4*NumAllocated; 496 } 497 498 // Remember the vararg offset for the va_start implementation. 499 FuncInfo->setVarArgsFrameOffset(ArgOffset); 500 501 std::vector<SDValue> OutChains; 502 503 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 504 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 505 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 506 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 507 508 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 509 true); 510 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 511 512 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 513 MachinePointerInfo(), 514 false, false, 0)); 515 ArgOffset += 4; 516 } 517 518 if (!OutChains.empty()) { 519 OutChains.push_back(Chain); 520 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 521 &OutChains[0], OutChains.size()); 522 } 523 } 524 525 return Chain; 526} 527 528// Lower formal arguments for the 64 bit ABI. 529SDValue SparcTargetLowering:: 530LowerFormalArguments_64(SDValue Chain, 531 CallingConv::ID CallConv, 532 bool IsVarArg, 533 const SmallVectorImpl<ISD::InputArg> &Ins, 534 DebugLoc DL, 535 SelectionDAG &DAG, 536 SmallVectorImpl<SDValue> &InVals) const { 537 MachineFunction &MF = DAG.getMachineFunction(); 538 539 // Analyze arguments according to CC_Sparc64. 540 SmallVector<CCValAssign, 16> ArgLocs; 541 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 542 getTargetMachine(), ArgLocs, *DAG.getContext()); 543 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); 544 545 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 546 CCValAssign &VA = ArgLocs[i]; 547 if (VA.isRegLoc()) { 548 // This argument is passed in a register. 549 // All integer register arguments are promoted by the caller to i64. 550 551 // Create a virtual register for the promoted live-in value. 552 unsigned VReg = MF.addLiveIn(VA.getLocReg(), 553 getRegClassFor(VA.getLocVT())); 554 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); 555 556 // Get the high bits for i32 struct elements. 557 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 558 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, 559 DAG.getConstant(32, MVT::i32)); 560 561 // The caller promoted the argument, so insert an Assert?ext SDNode so we 562 // won't promote the value again in this function. 563 switch (VA.getLocInfo()) { 564 case CCValAssign::SExt: 565 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, 566 DAG.getValueType(VA.getValVT())); 567 break; 568 case CCValAssign::ZExt: 569 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, 570 DAG.getValueType(VA.getValVT())); 571 break; 572 default: 573 break; 574 } 575 576 // Truncate the register down to the argument type. 577 if (VA.isExtInLoc()) 578 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); 579 580 InVals.push_back(Arg); 581 continue; 582 } 583 584 // The registers are exhausted. This argument was passed on the stack. 585 assert(VA.isMemLoc()); 586 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the 587 // beginning of the arguments area at %fp+BIAS+128. 588 unsigned Offset = VA.getLocMemOffset() + 128; 589 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; 590 // Adjust offset for extended arguments, SPARC is big-endian. 591 // The caller will have written the full slot with extended bytes, but we 592 // prefer our own extending loads. 593 if (VA.isExtInLoc()) 594 Offset += 8 - ValSize; 595 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true); 596 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, 597 DAG.getFrameIndex(FI, getPointerTy()), 598 MachinePointerInfo::getFixedStack(FI), 599 false, false, false, 0)); 600 } 601 return Chain; 602} 603 604SDValue 605SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 606 SmallVectorImpl<SDValue> &InVals) const { 607 if (Subtarget->is64Bit()) 608 return LowerCall_64(CLI, InVals); 609 return LowerCall_32(CLI, InVals); 610} 611 612// Lower a call for the 32-bit ABI. 613SDValue 614SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 615 SmallVectorImpl<SDValue> &InVals) const { 616 SelectionDAG &DAG = CLI.DAG; 617 DebugLoc &dl = CLI.DL; 618 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 619 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 620 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 621 SDValue Chain = CLI.Chain; 622 SDValue Callee = CLI.Callee; 623 bool &isTailCall = CLI.IsTailCall; 624 CallingConv::ID CallConv = CLI.CallConv; 625 bool isVarArg = CLI.IsVarArg; 626 627 // Sparc target does not yet support tail call optimization. 628 isTailCall = false; 629 630 // Analyze operands of the call, assigning locations to each operand. 631 SmallVector<CCValAssign, 16> ArgLocs; 632 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 633 DAG.getTarget(), ArgLocs, *DAG.getContext()); 634 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 635 636 // Get the size of the outgoing arguments stack space requirement. 637 unsigned ArgsSize = CCInfo.getNextStackOffset(); 638 639 // Keep stack frames 8-byte aligned. 640 ArgsSize = (ArgsSize+7) & ~7; 641 642 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 643 644 //Create local copies for byval args. 645 SmallVector<SDValue, 8> ByValArgs; 646 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 647 ISD::ArgFlagsTy Flags = Outs[i].Flags; 648 if (!Flags.isByVal()) 649 continue; 650 651 SDValue Arg = OutVals[i]; 652 unsigned Size = Flags.getByValSize(); 653 unsigned Align = Flags.getByValAlign(); 654 655 int FI = MFI->CreateStackObject(Size, Align, false); 656 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 657 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 658 659 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 660 false, //isVolatile, 661 (Size <= 32), //AlwaysInline if size <= 32 662 MachinePointerInfo(), MachinePointerInfo()); 663 ByValArgs.push_back(FIPtr); 664 } 665 666 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 667 668 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 669 SmallVector<SDValue, 8> MemOpChains; 670 671 const unsigned StackOffset = 92; 672 bool hasStructRetAttr = false; 673 // Walk the register/memloc assignments, inserting copies/loads. 674 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 675 i != e; 676 ++i, ++realArgIdx) { 677 CCValAssign &VA = ArgLocs[i]; 678 SDValue Arg = OutVals[realArgIdx]; 679 680 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 681 682 //Use local copy if it is a byval arg. 683 if (Flags.isByVal()) 684 Arg = ByValArgs[byvalArgIdx++]; 685 686 // Promote the value if needed. 687 switch (VA.getLocInfo()) { 688 default: llvm_unreachable("Unknown loc info!"); 689 case CCValAssign::Full: break; 690 case CCValAssign::SExt: 691 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 692 break; 693 case CCValAssign::ZExt: 694 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 695 break; 696 case CCValAssign::AExt: 697 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 698 break; 699 case CCValAssign::BCvt: 700 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 701 break; 702 } 703 704 if (Flags.isSRet()) { 705 assert(VA.needsCustom()); 706 // store SRet argument in %sp+64 707 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 708 SDValue PtrOff = DAG.getIntPtrConstant(64); 709 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 710 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 711 MachinePointerInfo(), 712 false, false, 0)); 713 hasStructRetAttr = true; 714 continue; 715 } 716 717 if (VA.needsCustom()) { 718 assert(VA.getLocVT() == MVT::f64); 719 720 if (VA.isMemLoc()) { 721 unsigned Offset = VA.getLocMemOffset() + StackOffset; 722 //if it is double-word aligned, just store. 723 if (Offset % 8 == 0) { 724 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 725 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 726 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 727 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 728 MachinePointerInfo(), 729 false, false, 0)); 730 continue; 731 } 732 } 733 734 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 735 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 736 Arg, StackPtr, MachinePointerInfo(), 737 false, false, 0); 738 // Sparc is big-endian, so the high part comes first. 739 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 740 MachinePointerInfo(), false, false, false, 0); 741 // Increment the pointer to the other half. 742 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 743 DAG.getIntPtrConstant(4)); 744 // Load the low part. 745 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 746 MachinePointerInfo(), false, false, false, 0); 747 748 if (VA.isRegLoc()) { 749 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 750 assert(i+1 != e); 751 CCValAssign &NextVA = ArgLocs[++i]; 752 if (NextVA.isRegLoc()) { 753 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 754 } else { 755 //Store the low part in stack. 756 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 757 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 758 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 759 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 760 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 761 MachinePointerInfo(), 762 false, false, 0)); 763 } 764 } else { 765 unsigned Offset = VA.getLocMemOffset() + StackOffset; 766 // Store the high part. 767 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 768 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 769 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 770 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 771 MachinePointerInfo(), 772 false, false, 0)); 773 // Store the low part. 774 PtrOff = DAG.getIntPtrConstant(Offset+4); 775 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 776 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 777 MachinePointerInfo(), 778 false, false, 0)); 779 } 780 continue; 781 } 782 783 // Arguments that can be passed on register must be kept at 784 // RegsToPass vector 785 if (VA.isRegLoc()) { 786 if (VA.getLocVT() != MVT::f32) { 787 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 788 continue; 789 } 790 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 791 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 792 continue; 793 } 794 795 assert(VA.isMemLoc()); 796 797 // Create a store off the stack pointer for this argument. 798 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 799 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 800 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 801 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 802 MachinePointerInfo(), 803 false, false, 0)); 804 } 805 806 807 // Emit all stores, make sure the occur before any copies into physregs. 808 if (!MemOpChains.empty()) 809 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 810 &MemOpChains[0], MemOpChains.size()); 811 812 // Build a sequence of copy-to-reg nodes chained together with token 813 // chain and flag operands which copy the outgoing args into registers. 814 // The InFlag in necessary since all emitted instructions must be 815 // stuck together. 816 SDValue InFlag; 817 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 818 unsigned Reg = toCallerWindow(RegsToPass[i].first); 819 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 820 InFlag = Chain.getValue(1); 821 } 822 823 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 824 825 // If the callee is a GlobalAddress node (quite common, every direct call is) 826 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 827 // Likewise ExternalSymbol -> TargetExternalSymbol. 828 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 829 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 830 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 831 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 832 833 // Returns a chain & a flag for retval copy to use 834 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 835 SmallVector<SDValue, 8> Ops; 836 Ops.push_back(Chain); 837 Ops.push_back(Callee); 838 if (hasStructRetAttr) 839 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 840 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 841 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), 842 RegsToPass[i].second.getValueType())); 843 if (InFlag.getNode()) 844 Ops.push_back(InFlag); 845 846 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 847 InFlag = Chain.getValue(1); 848 849 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 850 DAG.getIntPtrConstant(0, true), InFlag); 851 InFlag = Chain.getValue(1); 852 853 // Assign locations to each value returned by this call. 854 SmallVector<CCValAssign, 16> RVLocs; 855 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 856 DAG.getTarget(), RVLocs, *DAG.getContext()); 857 858 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 859 860 // Copy all of the result registers out of their specified physreg. 861 for (unsigned i = 0; i != RVLocs.size(); ++i) { 862 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), 863 RVLocs[i].getValVT(), InFlag).getValue(1); 864 InFlag = Chain.getValue(2); 865 InVals.push_back(Chain.getValue(0)); 866 } 867 868 return Chain; 869} 870 871unsigned 872SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 873{ 874 const Function *CalleeFn = 0; 875 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 876 CalleeFn = dyn_cast<Function>(G->getGlobal()); 877 } else if (ExternalSymbolSDNode *E = 878 dyn_cast<ExternalSymbolSDNode>(Callee)) { 879 const Function *Fn = DAG.getMachineFunction().getFunction(); 880 const Module *M = Fn->getParent(); 881 CalleeFn = M->getFunction(E->getSymbol()); 882 } 883 884 if (!CalleeFn) 885 return 0; 886 887 assert(CalleeFn->hasStructRetAttr() && 888 "Callee does not have the StructRet attribute."); 889 890 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 891 Type *ElementTy = Ty->getElementType(); 892 return getDataLayout()->getTypeAllocSize(ElementTy); 893} 894 895// Lower a call for the 64-bit ABI. 896SDValue 897SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 898 SmallVectorImpl<SDValue> &InVals) const { 899 SelectionDAG &DAG = CLI.DAG; 900 DebugLoc DL = CLI.DL; 901 SDValue Chain = CLI.Chain; 902 903 // Analyze operands of the call, assigning locations to each operand. 904 SmallVector<CCValAssign, 16> ArgLocs; 905 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 906 DAG.getTarget(), ArgLocs, *DAG.getContext()); 907 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); 908 909 // Get the size of the outgoing arguments stack space requirement. 910 // The stack offset computed by CC_Sparc64 includes all arguments. 911 // Called functions expect 6 argument words to exist in the stack frame, used 912 // or not. 913 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); 914 915 // Keep stack frames 16-byte aligned. 916 ArgsSize = RoundUpToAlignment(ArgsSize, 16); 917 918 // Adjust the stack pointer to make room for the arguments. 919 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls 920 // with more than 6 arguments. 921 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 922 923 // Collect the set of registers to pass to the function and their values. 924 // This will be emitted as a sequence of CopyToReg nodes glued to the call 925 // instruction. 926 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 927 928 // Collect chains from all the memory opeations that copy arguments to the 929 // stack. They must follow the stack pointer adjustment above and precede the 930 // call instruction itself. 931 SmallVector<SDValue, 8> MemOpChains; 932 933 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 934 const CCValAssign &VA = ArgLocs[i]; 935 SDValue Arg = CLI.OutVals[i]; 936 937 // Promote the value if needed. 938 switch (VA.getLocInfo()) { 939 default: 940 llvm_unreachable("Unknown location info!"); 941 case CCValAssign::Full: 942 break; 943 case CCValAssign::SExt: 944 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 945 break; 946 case CCValAssign::ZExt: 947 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 948 break; 949 case CCValAssign::AExt: 950 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 951 break; 952 case CCValAssign::BCvt: 953 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 954 break; 955 } 956 957 if (VA.isRegLoc()) { 958 // The custom bit on an i32 return value indicates that it should be 959 // passed in the high bits of the register. 960 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 961 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, 962 DAG.getConstant(32, MVT::i32)); 963 964 // The next value may go in the low bits of the same register. 965 // Handle both at once. 966 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && 967 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { 968 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, 969 CLI.OutVals[i+1]); 970 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); 971 // Skip the next value, it's already done. 972 ++i; 973 } 974 } 975 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); 976 continue; 977 } 978 979 assert(VA.isMemLoc()); 980 981 // Create a store off the stack pointer for this argument. 982 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 983 // The argument area starts at %fp+BIAS+128 in the callee frame, 984 // %sp+BIAS+128 in ours. 985 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + 986 Subtarget->getStackPointerBias() + 987 128); 988 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 989 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, 990 MachinePointerInfo(), 991 false, false, 0)); 992 } 993 994 // Emit all stores, make sure they occur before the call. 995 if (!MemOpChains.empty()) 996 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 997 &MemOpChains[0], MemOpChains.size()); 998 999 // Build a sequence of CopyToReg nodes glued together with token chain and 1000 // glue operands which copy the outgoing args into registers. The InGlue is 1001 // necessary since all emitted instructions must be stuck together in order 1002 // to pass the live physical registers. 1003 SDValue InGlue; 1004 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1005 Chain = DAG.getCopyToReg(Chain, DL, 1006 RegsToPass[i].first, RegsToPass[i].second, InGlue); 1007 InGlue = Chain.getValue(1); 1008 } 1009 1010 // If the callee is a GlobalAddress node (quite common, every direct call is) 1011 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1012 // Likewise ExternalSymbol -> TargetExternalSymbol. 1013 SDValue Callee = CLI.Callee; 1014 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1015 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy()); 1016 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1017 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 1018 1019 // Build the operands for the call instruction itself. 1020 SmallVector<SDValue, 8> Ops; 1021 Ops.push_back(Chain); 1022 Ops.push_back(Callee); 1023 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1024 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1025 RegsToPass[i].second.getValueType())); 1026 1027 // Make sure the CopyToReg nodes are glued to the call instruction which 1028 // consumes the registers. 1029 if (InGlue.getNode()) 1030 Ops.push_back(InGlue); 1031 1032 // Now the call itself. 1033 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1034 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size()); 1035 InGlue = Chain.getValue(1); 1036 1037 // Revert the stack pointer immediately after the call. 1038 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1039 DAG.getIntPtrConstant(0, true), InGlue); 1040 InGlue = Chain.getValue(1); 1041 1042 // Now extract the return values. This is more or less the same as 1043 // LowerFormalArguments_64. 1044 1045 // Assign locations to each value returned by this call. 1046 SmallVector<CCValAssign, 16> RVLocs; 1047 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1048 DAG.getTarget(), RVLocs, *DAG.getContext()); 1049 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64); 1050 1051 // Copy all of the result registers out of their specified physreg. 1052 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1053 CCValAssign &VA = RVLocs[i]; 1054 unsigned Reg = toCallerWindow(VA.getLocReg()); 1055 1056 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can 1057 // reside in the same register in the high and low bits. Reuse the 1058 // CopyFromReg previous node to avoid duplicate copies. 1059 SDValue RV; 1060 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1))) 1061 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) 1062 RV = Chain.getValue(0); 1063 1064 // But usually we'll create a new CopyFromReg for a different register. 1065 if (!RV.getNode()) { 1066 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue); 1067 Chain = RV.getValue(1); 1068 InGlue = Chain.getValue(2); 1069 } 1070 1071 // Get the high bits for i32 struct elements. 1072 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 1073 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, 1074 DAG.getConstant(32, MVT::i32)); 1075 1076 // The callee promoted the return value, so insert an Assert?ext SDNode so 1077 // we won't promote the value again in this function. 1078 switch (VA.getLocInfo()) { 1079 case CCValAssign::SExt: 1080 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, 1081 DAG.getValueType(VA.getValVT())); 1082 break; 1083 case CCValAssign::ZExt: 1084 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, 1085 DAG.getValueType(VA.getValVT())); 1086 break; 1087 default: 1088 break; 1089 } 1090 1091 // Truncate the register down to the return value type. 1092 if (VA.isExtInLoc()) 1093 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); 1094 1095 InVals.push_back(RV); 1096 } 1097 1098 return Chain; 1099} 1100 1101//===----------------------------------------------------------------------===// 1102// TargetLowering Implementation 1103//===----------------------------------------------------------------------===// 1104 1105/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 1106/// condition. 1107static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 1108 switch (CC) { 1109 default: llvm_unreachable("Unknown integer condition code!"); 1110 case ISD::SETEQ: return SPCC::ICC_E; 1111 case ISD::SETNE: return SPCC::ICC_NE; 1112 case ISD::SETLT: return SPCC::ICC_L; 1113 case ISD::SETGT: return SPCC::ICC_G; 1114 case ISD::SETLE: return SPCC::ICC_LE; 1115 case ISD::SETGE: return SPCC::ICC_GE; 1116 case ISD::SETULT: return SPCC::ICC_CS; 1117 case ISD::SETULE: return SPCC::ICC_LEU; 1118 case ISD::SETUGT: return SPCC::ICC_GU; 1119 case ISD::SETUGE: return SPCC::ICC_CC; 1120 } 1121} 1122 1123/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 1124/// FCC condition. 1125static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 1126 switch (CC) { 1127 default: llvm_unreachable("Unknown fp condition code!"); 1128 case ISD::SETEQ: 1129 case ISD::SETOEQ: return SPCC::FCC_E; 1130 case ISD::SETNE: 1131 case ISD::SETUNE: return SPCC::FCC_NE; 1132 case ISD::SETLT: 1133 case ISD::SETOLT: return SPCC::FCC_L; 1134 case ISD::SETGT: 1135 case ISD::SETOGT: return SPCC::FCC_G; 1136 case ISD::SETLE: 1137 case ISD::SETOLE: return SPCC::FCC_LE; 1138 case ISD::SETGE: 1139 case ISD::SETOGE: return SPCC::FCC_GE; 1140 case ISD::SETULT: return SPCC::FCC_UL; 1141 case ISD::SETULE: return SPCC::FCC_ULE; 1142 case ISD::SETUGT: return SPCC::FCC_UG; 1143 case ISD::SETUGE: return SPCC::FCC_UGE; 1144 case ISD::SETUO: return SPCC::FCC_U; 1145 case ISD::SETO: return SPCC::FCC_O; 1146 case ISD::SETONE: return SPCC::FCC_LG; 1147 case ISD::SETUEQ: return SPCC::FCC_UE; 1148 } 1149} 1150 1151SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 1152 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 1153 Subtarget = &TM.getSubtarget<SparcSubtarget>(); 1154 1155 // Set up the register classes. 1156 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); 1157 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); 1158 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); 1159 if (Subtarget->is64Bit()) 1160 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); 1161 1162 // Turn FP extload into load/fextend 1163 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1164 // Sparc doesn't have i1 sign extending load 1165 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1166 // Turn FP truncstore into trunc + store. 1167 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1168 1169 // Custom legalize GlobalAddress nodes into LO/HI parts. 1170 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); 1171 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); 1172 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); 1173 1174 // Sparc doesn't have sext_inreg, replace them with shl/sra 1175 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 1176 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 1177 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1178 1179 // Sparc has no REM or DIVREM operations. 1180 setOperationAction(ISD::UREM, MVT::i32, Expand); 1181 setOperationAction(ISD::SREM, MVT::i32, Expand); 1182 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1183 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1184 1185 // Custom expand fp<->sint 1186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 1187 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1188 1189 // Expand fp<->uint 1190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1191 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1192 1193 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 1194 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 1195 1196 // Sparc has no select or setcc: expand to SELECT_CC. 1197 setOperationAction(ISD::SELECT, MVT::i32, Expand); 1198 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1199 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1200 setOperationAction(ISD::SETCC, MVT::i32, Expand); 1201 setOperationAction(ISD::SETCC, MVT::f32, Expand); 1202 setOperationAction(ISD::SETCC, MVT::f64, Expand); 1203 1204 // Sparc doesn't have BRCOND either, it has BR_CC. 1205 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1206 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1207 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1208 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1209 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1210 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 1211 1212 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1213 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1214 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1215 1216 if (Subtarget->is64Bit()) { 1217 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 1218 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1219 } 1220 1221 // FIXME: There are instructions available for ATOMIC_FENCE 1222 // on SparcV8 and later. 1223 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 1224 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 1225 1226 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1227 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1228 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1229 setOperationAction(ISD::FREM , MVT::f64, Expand); 1230 setOperationAction(ISD::FMA , MVT::f64, Expand); 1231 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1232 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1233 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1234 setOperationAction(ISD::FREM , MVT::f32, Expand); 1235 setOperationAction(ISD::FMA , MVT::f32, Expand); 1236 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 1237 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1238 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1239 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1240 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1241 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1242 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1243 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1244 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1245 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1246 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1247 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1248 1249 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1250 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1251 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1252 1253 // FIXME: Sparc provides these multiplies, but we don't have them yet. 1254 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1255 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1256 1257 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 1258 1259 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1260 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1261 // VAARG needs to be lowered to not do unaligned accesses for doubles. 1262 setOperationAction(ISD::VAARG , MVT::Other, Custom); 1263 1264 // Use the default implementation. 1265 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1266 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1267 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1268 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1269 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1270 1271 // No debug info support yet. 1272 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 1273 1274 setStackPointerRegisterToSaveRestore(SP::O6); 1275 1276 if (TM.getSubtarget<SparcSubtarget>().isV9()) 1277 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 1278 1279 setMinFunctionAlignment(2); 1280 1281 computeRegisterProperties(); 1282} 1283 1284const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 1285 switch (Opcode) { 1286 default: return 0; 1287 case SPISD::CMPICC: return "SPISD::CMPICC"; 1288 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 1289 case SPISD::BRICC: return "SPISD::BRICC"; 1290 case SPISD::BRXCC: return "SPISD::BRXCC"; 1291 case SPISD::BRFCC: return "SPISD::BRFCC"; 1292 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 1293 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; 1294 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 1295 case SPISD::Hi: return "SPISD::Hi"; 1296 case SPISD::Lo: return "SPISD::Lo"; 1297 case SPISD::FTOI: return "SPISD::FTOI"; 1298 case SPISD::ITOF: return "SPISD::ITOF"; 1299 case SPISD::CALL: return "SPISD::CALL"; 1300 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 1301 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 1302 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 1303 } 1304} 1305 1306/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 1307/// be zero. Op is expected to be a target specific node. Used by DAG 1308/// combiner. 1309void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1310 APInt &KnownZero, 1311 APInt &KnownOne, 1312 const SelectionDAG &DAG, 1313 unsigned Depth) const { 1314 APInt KnownZero2, KnownOne2; 1315 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1316 1317 switch (Op.getOpcode()) { 1318 default: break; 1319 case SPISD::SELECT_ICC: 1320 case SPISD::SELECT_XCC: 1321 case SPISD::SELECT_FCC: 1322 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); 1323 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); 1324 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1325 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1326 1327 // Only known if known in both the LHS and RHS. 1328 KnownOne &= KnownOne2; 1329 KnownZero &= KnownZero2; 1330 break; 1331 } 1332} 1333 1334// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 1335// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 1336static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 1337 ISD::CondCode CC, unsigned &SPCC) { 1338 if (isa<ConstantSDNode>(RHS) && 1339 cast<ConstantSDNode>(RHS)->isNullValue() && 1340 CC == ISD::SETNE && 1341 (((LHS.getOpcode() == SPISD::SELECT_ICC || 1342 LHS.getOpcode() == SPISD::SELECT_XCC) && 1343 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 1344 (LHS.getOpcode() == SPISD::SELECT_FCC && 1345 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 1346 isa<ConstantSDNode>(LHS.getOperand(0)) && 1347 isa<ConstantSDNode>(LHS.getOperand(1)) && 1348 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 1349 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 1350 SDValue CMPCC = LHS.getOperand(3); 1351 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 1352 LHS = CMPCC.getOperand(0); 1353 RHS = CMPCC.getOperand(1); 1354 } 1355} 1356 1357SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 1358 SelectionDAG &DAG) const { 1359 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1360 // FIXME there isn't really any debug info here 1361 DebugLoc dl = Op.getDebugLoc(); 1362 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 1363 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); 1364 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); 1365 1366 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1367 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 1368 1369 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 1370 getPointerTy()); 1371 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 1372 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 1373 GlobalBase, RelAddr); 1374 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 1375 AbsAddr, MachinePointerInfo(), false, false, false, 0); 1376} 1377 1378SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 1379 SelectionDAG &DAG) const { 1380 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1381 // FIXME there isn't really any debug info here 1382 DebugLoc dl = Op.getDebugLoc(); 1383 const Constant *C = N->getConstVal(); 1384 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 1385 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); 1386 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); 1387 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1388 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 1389 1390 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 1391 getPointerTy()); 1392 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 1393 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 1394 GlobalBase, RelAddr); 1395 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 1396 AbsAddr, MachinePointerInfo(), false, false, false, 0); 1397} 1398 1399static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 1400 DebugLoc dl = Op.getDebugLoc(); 1401 // Convert the fp value to integer in an FP register. 1402 assert(Op.getValueType() == MVT::i32); 1403 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 1404 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 1405} 1406 1407static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1408 DebugLoc dl = Op.getDebugLoc(); 1409 assert(Op.getOperand(0).getValueType() == MVT::i32); 1410 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 1411 // Convert the int value to FP in an FP register. 1412 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 1413} 1414 1415static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 1416 SDValue Chain = Op.getOperand(0); 1417 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1418 SDValue LHS = Op.getOperand(2); 1419 SDValue RHS = Op.getOperand(3); 1420 SDValue Dest = Op.getOperand(4); 1421 DebugLoc dl = Op.getDebugLoc(); 1422 unsigned Opc, SPCC = ~0U; 1423 1424 // If this is a br_cc of a "setcc", and if the setcc got lowered into 1425 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 1426 LookThroughSetCC(LHS, RHS, CC, SPCC); 1427 1428 // Get the condition flag. 1429 SDValue CompareFlag; 1430 if (LHS.getValueType().isInteger()) { 1431 EVT VTs[] = { LHS.getValueType(), MVT::Glue }; 1432 SDValue Ops[2] = { LHS, RHS }; 1433 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 1434 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 1435 // 32-bit compares use the icc flags, 64-bit uses the xcc flags. 1436 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; 1437 } else { 1438 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 1439 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 1440 Opc = SPISD::BRFCC; 1441 } 1442 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 1443 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 1444} 1445 1446static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 1447 SDValue LHS = Op.getOperand(0); 1448 SDValue RHS = Op.getOperand(1); 1449 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1450 SDValue TrueVal = Op.getOperand(2); 1451 SDValue FalseVal = Op.getOperand(3); 1452 DebugLoc dl = Op.getDebugLoc(); 1453 unsigned Opc, SPCC = ~0U; 1454 1455 // If this is a select_cc of a "setcc", and if the setcc got lowered into 1456 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 1457 LookThroughSetCC(LHS, RHS, CC, SPCC); 1458 1459 SDValue CompareFlag; 1460 if (LHS.getValueType().isInteger()) { 1461 // subcc returns a value 1462 EVT VTs[] = { LHS.getValueType(), MVT::Glue }; 1463 SDValue Ops[2] = { LHS, RHS }; 1464 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 1465 Opc = LHS.getValueType() == MVT::i32 ? 1466 SPISD::SELECT_ICC : SPISD::SELECT_XCC; 1467 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 1468 } else { 1469 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 1470 Opc = SPISD::SELECT_FCC; 1471 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 1472 } 1473 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 1474 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 1475} 1476 1477static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1478 const SparcTargetLowering &TLI) { 1479 MachineFunction &MF = DAG.getMachineFunction(); 1480 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 1481 1482 // vastart just stores the address of the VarArgsFrameIndex slot into the 1483 // memory location argument. 1484 DebugLoc dl = Op.getDebugLoc(); 1485 SDValue Offset = 1486 DAG.getNode(ISD::ADD, dl, MVT::i32, 1487 DAG.getRegister(SP::I6, MVT::i32), 1488 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(), 1489 MVT::i32)); 1490 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1491 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), 1492 MachinePointerInfo(SV), false, false, 0); 1493} 1494 1495static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 1496 SDNode *Node = Op.getNode(); 1497 EVT VT = Node->getValueType(0); 1498 SDValue InChain = Node->getOperand(0); 1499 SDValue VAListPtr = Node->getOperand(1); 1500 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1501 DebugLoc dl = Node->getDebugLoc(); 1502 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, 1503 MachinePointerInfo(SV), false, false, false, 0); 1504 // Increment the pointer, VAList, to the next vaarg 1505 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 1506 DAG.getConstant(VT.getSizeInBits()/8, 1507 MVT::i32)); 1508 // Store the incremented VAList to the legalized pointer 1509 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 1510 VAListPtr, MachinePointerInfo(SV), false, false, 0); 1511 // Load the actual argument out of the pointer VAList, unless this is an 1512 // f64 load. 1513 if (VT != MVT::f64) 1514 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 1515 false, false, false, 0); 1516 1517 // Otherwise, load it as i64, then do a bitconvert. 1518 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(), 1519 false, false, false, 0); 1520 1521 // Bit-Convert the value to f64. 1522 SDValue Ops[2] = { 1523 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V), 1524 V.getValue(1) 1525 }; 1526 return DAG.getMergeValues(Ops, 2, dl); 1527} 1528 1529static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1530 SDValue Chain = Op.getOperand(0); // Legalize the chain. 1531 SDValue Size = Op.getOperand(1); // Legalize the size. 1532 DebugLoc dl = Op.getDebugLoc(); 1533 1534 unsigned SPReg = SP::O6; 1535 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 1536 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 1537 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 1538 1539 // The resultant pointer is actually 16 words from the bottom of the stack, 1540 // to provide a register spill area. 1541 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 1542 DAG.getConstant(96, MVT::i32)); 1543 SDValue Ops[2] = { NewVal, Chain }; 1544 return DAG.getMergeValues(Ops, 2, dl); 1545} 1546 1547 1548static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 1549 DebugLoc dl = Op.getDebugLoc(); 1550 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 1551 dl, MVT::Other, DAG.getEntryNode()); 1552 return Chain; 1553} 1554 1555static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1556 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1557 MFI->setFrameAddressIsTaken(true); 1558 1559 EVT VT = Op.getValueType(); 1560 DebugLoc dl = Op.getDebugLoc(); 1561 unsigned FrameReg = SP::I6; 1562 1563 uint64_t depth = Op.getConstantOperandVal(0); 1564 1565 SDValue FrameAddr; 1566 if (depth == 0) 1567 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1568 else { 1569 // flush first to make sure the windowed registers' values are in stack 1570 SDValue Chain = getFLUSHW(Op, DAG); 1571 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 1572 1573 for (uint64_t i = 0; i != depth; ++i) { 1574 SDValue Ptr = DAG.getNode(ISD::ADD, 1575 dl, MVT::i32, 1576 FrameAddr, DAG.getIntPtrConstant(56)); 1577 FrameAddr = DAG.getLoad(MVT::i32, dl, 1578 Chain, 1579 Ptr, 1580 MachinePointerInfo(), false, false, false, 0); 1581 } 1582 } 1583 return FrameAddr; 1584} 1585 1586static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 1587 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1588 MFI->setReturnAddressIsTaken(true); 1589 1590 EVT VT = Op.getValueType(); 1591 DebugLoc dl = Op.getDebugLoc(); 1592 unsigned RetReg = SP::I7; 1593 1594 uint64_t depth = Op.getConstantOperandVal(0); 1595 1596 SDValue RetAddr; 1597 if (depth == 0) 1598 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 1599 else { 1600 // flush first to make sure the windowed registers' values are in stack 1601 SDValue Chain = getFLUSHW(Op, DAG); 1602 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 1603 1604 for (uint64_t i = 0; i != depth; ++i) { 1605 SDValue Ptr = DAG.getNode(ISD::ADD, 1606 dl, MVT::i32, 1607 RetAddr, 1608 DAG.getIntPtrConstant((i == depth-1)?60:56)); 1609 RetAddr = DAG.getLoad(MVT::i32, dl, 1610 Chain, 1611 Ptr, 1612 MachinePointerInfo(), false, false, false, 0); 1613 } 1614 } 1615 return RetAddr; 1616} 1617 1618SDValue SparcTargetLowering:: 1619LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1620 switch (Op.getOpcode()) { 1621 default: llvm_unreachable("Should not custom lower this!"); 1622 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1623 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1624 case ISD::GlobalTLSAddress: 1625 llvm_unreachable("TLS not implemented for Sparc."); 1626 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1627 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1628 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1629 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1630 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1631 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1632 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 1633 case ISD::VAARG: return LowerVAARG(Op, DAG); 1634 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1635 } 1636} 1637 1638MachineBasicBlock * 1639SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1640 MachineBasicBlock *BB) const { 1641 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1642 unsigned BROpcode; 1643 unsigned CC; 1644 DebugLoc dl = MI->getDebugLoc(); 1645 // Figure out the conditional branch opcode to use for this select_cc. 1646 switch (MI->getOpcode()) { 1647 default: llvm_unreachable("Unknown SELECT_CC!"); 1648 case SP::SELECT_CC_Int_ICC: 1649 case SP::SELECT_CC_FP_ICC: 1650 case SP::SELECT_CC_DFP_ICC: 1651 BROpcode = SP::BCOND; 1652 break; 1653 case SP::SELECT_CC_Int_FCC: 1654 case SP::SELECT_CC_FP_FCC: 1655 case SP::SELECT_CC_DFP_FCC: 1656 BROpcode = SP::FBCOND; 1657 break; 1658 } 1659 1660 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 1661 1662 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1663 // control-flow pattern. The incoming instruction knows the destination vreg 1664 // to set, the condition code register to branch on, the true/false values to 1665 // select between, and a branch opcode to use. 1666 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1667 MachineFunction::iterator It = BB; 1668 ++It; 1669 1670 // thisMBB: 1671 // ... 1672 // TrueVal = ... 1673 // [f]bCC copy1MBB 1674 // fallthrough --> copy0MBB 1675 MachineBasicBlock *thisMBB = BB; 1676 MachineFunction *F = BB->getParent(); 1677 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1678 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1679 F->insert(It, copy0MBB); 1680 F->insert(It, sinkMBB); 1681 1682 // Transfer the remainder of BB and its successor edges to sinkMBB. 1683 sinkMBB->splice(sinkMBB->begin(), BB, 1684 llvm::next(MachineBasicBlock::iterator(MI)), 1685 BB->end()); 1686 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1687 1688 // Add the true and fallthrough blocks as its successors. 1689 BB->addSuccessor(copy0MBB); 1690 BB->addSuccessor(sinkMBB); 1691 1692 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1693 1694 // copy0MBB: 1695 // %FalseValue = ... 1696 // # fallthrough to sinkMBB 1697 BB = copy0MBB; 1698 1699 // Update machine-CFG edges 1700 BB->addSuccessor(sinkMBB); 1701 1702 // sinkMBB: 1703 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1704 // ... 1705 BB = sinkMBB; 1706 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1707 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1708 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1709 1710 MI->eraseFromParent(); // The pseudo instruction is gone now. 1711 return BB; 1712} 1713 1714//===----------------------------------------------------------------------===// 1715// Sparc Inline Assembly Support 1716//===----------------------------------------------------------------------===// 1717 1718/// getConstraintType - Given a constraint letter, return the type of 1719/// constraint it is for this target. 1720SparcTargetLowering::ConstraintType 1721SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1722 if (Constraint.size() == 1) { 1723 switch (Constraint[0]) { 1724 default: break; 1725 case 'r': return C_RegisterClass; 1726 } 1727 } 1728 1729 return TargetLowering::getConstraintType(Constraint); 1730} 1731 1732std::pair<unsigned, const TargetRegisterClass*> 1733SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1734 EVT VT) const { 1735 if (Constraint.size() == 1) { 1736 switch (Constraint[0]) { 1737 case 'r': 1738 return std::make_pair(0U, &SP::IntRegsRegClass); 1739 } 1740 } 1741 1742 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1743} 1744 1745bool 1746SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1747 // The Sparc target isn't yet aware of offsets. 1748 return false; 1749} 1750