SparcISelLowering.cpp revision 5a65b928302494ad2b3051980ce956e8f9e95023
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcTargetMachine.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/CallingConvLower.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24using namespace llvm; 25 26 27//===----------------------------------------------------------------------===// 28// Calling Convention Implementation 29//===----------------------------------------------------------------------===// 30 31#include "SparcGenCallingConv.inc" 32 33static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 34 // CCValAssign - represent the assignment of the return value to locations. 35 SmallVector<CCValAssign, 16> RVLocs; 36 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 37 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 38 39 // CCState - Info about the registers and stack slot. 40 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs); 41 42 // Analize return values of ISD::RET 43 CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32); 44 45 // If this is the first return lowered for this function, add the regs to the 46 // liveout set for the function. 47 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 48 for (unsigned i = 0; i != RVLocs.size(); ++i) 49 if (RVLocs[i].isRegLoc()) 50 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 51 } 52 53 SDOperand Chain = Op.getOperand(0); 54 SDOperand Flag; 55 56 // Copy the result values into the output registers. 57 for (unsigned i = 0; i != RVLocs.size(); ++i) { 58 CCValAssign &VA = RVLocs[i]; 59 assert(VA.isRegLoc() && "Can only return in registers!"); 60 61 // ISD::RET => ret chain, (regnum1,val1), ... 62 // So i*2+1 index only the regnums. 63 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 64 65 // Guarantee that all emitted copies are stuck together with flags. 66 Flag = Chain.getValue(1); 67 } 68 69 if (Flag.Val) 70 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag); 71 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain); 72} 73 74/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 75/// either one or two GPRs, including FP values. TODO: we should pass FP values 76/// in FP registers for fastcc functions. 77std::vector<SDOperand> 78SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 79 MachineFunction &MF = DAG.getMachineFunction(); 80 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 81 std::vector<SDOperand> ArgValues; 82 83 static const unsigned ArgRegs[] = { 84 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 85 }; 86 87 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 88 unsigned ArgOffset = 68; 89 90 SDOperand Root = DAG.getRoot(); 91 std::vector<SDOperand> OutChains; 92 93 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 94 MVT::ValueType ObjectVT = getValueType(I->getType()); 95 96 switch (ObjectVT) { 97 default: assert(0 && "Unhandled argument type!"); 98 case MVT::i1: 99 case MVT::i8: 100 case MVT::i16: 101 case MVT::i32: 102 if (I->use_empty()) { // Argument is dead. 103 if (CurArgReg < ArgRegEnd) ++CurArgReg; 104 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 105 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 106 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 107 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 108 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 109 if (ObjectVT != MVT::i32) { 110 unsigned AssertOp = ISD::AssertSext; 111 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 112 DAG.getValueType(ObjectVT)); 113 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 114 } 115 ArgValues.push_back(Arg); 116 } else { 117 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 118 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 119 SDOperand Load; 120 if (ObjectVT == MVT::i32) { 121 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 122 } else { 123 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 124 125 // Sparc is big endian, so add an offset based on the ObjectVT. 126 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 127 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 128 DAG.getConstant(Offset, MVT::i32)); 129 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 130 NULL, 0, ObjectVT); 131 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 132 } 133 ArgValues.push_back(Load); 134 } 135 136 ArgOffset += 4; 137 break; 138 case MVT::f32: 139 if (I->use_empty()) { // Argument is dead. 140 if (CurArgReg < ArgRegEnd) ++CurArgReg; 141 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 142 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 143 // FP value is passed in an integer register. 144 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 145 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 146 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 147 148 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 149 ArgValues.push_back(Arg); 150 } else { 151 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 152 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 153 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 154 ArgValues.push_back(Load); 155 } 156 ArgOffset += 4; 157 break; 158 159 case MVT::i64: 160 case MVT::f64: 161 if (I->use_empty()) { // Argument is dead. 162 if (CurArgReg < ArgRegEnd) ++CurArgReg; 163 if (CurArgReg < ArgRegEnd) ++CurArgReg; 164 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 165 } else if (/* FIXME: Apparently this isn't safe?? */ 166 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 167 ((CurArgReg-ArgRegs) & 1) == 0) { 168 // If this is a double argument and the whole thing lives on the stack, 169 // and the argument is aligned, load the double straight from the stack. 170 // We can't do a load in cases like void foo([6ints], int,double), 171 // because the double wouldn't be aligned! 172 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 173 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 174 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 175 } else { 176 SDOperand HiVal; 177 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 178 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 179 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 180 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 181 } else { 182 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 183 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 184 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 185 } 186 187 SDOperand LoVal; 188 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 189 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 190 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 191 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 192 } else { 193 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 194 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 195 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 196 } 197 198 // Compose the two halves together into an i64 unit. 199 SDOperand WholeValue = 200 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 201 202 // If we want a double, do a bit convert. 203 if (ObjectVT == MVT::f64) 204 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 205 206 ArgValues.push_back(WholeValue); 207 } 208 ArgOffset += 8; 209 break; 210 } 211 } 212 213 // Store remaining ArgRegs to the stack if this is a varargs function. 214 if (F.isVarArg()) { 215 // Remember the vararg offset for the va_start implementation. 216 VarArgsFrameOffset = ArgOffset; 217 218 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 219 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 220 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 221 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 222 223 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 224 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 225 226 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 227 ArgOffset += 4; 228 } 229 } 230 231 if (!OutChains.empty()) 232 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 233 &OutChains[0], OutChains.size())); 234 235 return ArgValues; 236} 237 238std::pair<SDOperand, SDOperand> 239SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 240 bool RetSExt, bool RetZExt, bool isVarArg, 241 unsigned CC, bool isTailCall, SDOperand Callee, 242 ArgListTy &Args, SelectionDAG &DAG) { 243 // Count the size of the outgoing arguments. 244 unsigned ArgsSize = 0; 245 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 246 switch (getValueType(Args[i].Ty)) { 247 default: assert(0 && "Unknown value type!"); 248 case MVT::i1: 249 case MVT::i8: 250 case MVT::i16: 251 case MVT::i32: 252 case MVT::f32: 253 ArgsSize += 4; 254 break; 255 case MVT::i64: 256 case MVT::f64: 257 ArgsSize += 8; 258 break; 259 } 260 } 261 if (ArgsSize > 4*6) 262 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 263 else 264 ArgsSize = 0; 265 266 // Keep stack frames 8-byte aligned. 267 ArgsSize = (ArgsSize+7) & ~7; 268 269 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 270 271 SDOperand StackPtr; 272 std::vector<SDOperand> Stores; 273 std::vector<SDOperand> RegValuesToPass; 274 unsigned ArgOffset = 68; 275 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 276 SDOperand Val = Args[i].Node; 277 MVT::ValueType ObjectVT = Val.getValueType(); 278 SDOperand ValToStore(0, 0); 279 unsigned ObjSize; 280 switch (ObjectVT) { 281 default: assert(0 && "Unhandled argument type!"); 282 case MVT::i1: 283 case MVT::i8: 284 case MVT::i16: { 285 // Promote the integer to 32-bits. If the input type is signed, use a 286 // sign extend, otherwise use a zero extend. 287 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 288 if (Args[i].isSExt) 289 ExtendKind = ISD::SIGN_EXTEND; 290 else if (Args[i].isZExt) 291 ExtendKind = ISD::ZERO_EXTEND; 292 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 293 // FALL THROUGH 294 } 295 case MVT::i32: 296 ObjSize = 4; 297 298 if (RegValuesToPass.size() >= 6) { 299 ValToStore = Val; 300 } else { 301 RegValuesToPass.push_back(Val); 302 } 303 break; 304 case MVT::f32: 305 ObjSize = 4; 306 if (RegValuesToPass.size() >= 6) { 307 ValToStore = Val; 308 } else { 309 // Convert this to a FP value in an int reg. 310 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 311 RegValuesToPass.push_back(Val); 312 } 313 break; 314 case MVT::f64: 315 ObjSize = 8; 316 // If we can store this directly into the outgoing slot, do so. We can 317 // do this when all ArgRegs are used and if the outgoing slot is aligned. 318 // FIXME: McGill/misr fails with this. 319 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 320 ValToStore = Val; 321 break; 322 } 323 324 // Otherwise, convert this to a FP value in int regs. 325 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 326 // FALL THROUGH 327 case MVT::i64: 328 ObjSize = 8; 329 if (RegValuesToPass.size() >= 6) { 330 ValToStore = Val; // Whole thing is passed in memory. 331 break; 332 } 333 334 // Split the value into top and bottom part. Top part goes in a reg. 335 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 336 DAG.getConstant(1, MVT::i32)); 337 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 338 DAG.getConstant(0, MVT::i32)); 339 RegValuesToPass.push_back(Hi); 340 341 if (RegValuesToPass.size() >= 6) { 342 ValToStore = Lo; 343 ArgOffset += 4; 344 ObjSize = 4; 345 } else { 346 RegValuesToPass.push_back(Lo); 347 } 348 break; 349 } 350 351 if (ValToStore.Val) { 352 if (!StackPtr.Val) { 353 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 354 } 355 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 356 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 357 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 358 } 359 ArgOffset += ObjSize; 360 } 361 362 // Emit all stores, make sure the occur before any copies into physregs. 363 if (!Stores.empty()) 364 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 365 366 static const unsigned ArgRegs[] = { 367 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 368 }; 369 370 // Build a sequence of copy-to-reg nodes chained together with token chain 371 // and flag operands which copy the outgoing args into O[0-5]. 372 SDOperand InFlag; 373 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 374 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 375 InFlag = Chain.getValue(1); 376 } 377 378 // If the callee is a GlobalAddress node (quite common, every direct call is) 379 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 380 // Likewise ExternalSymbol -> TargetExternalSymbol. 381 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 382 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 383 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 384 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 385 386 std::vector<MVT::ValueType> NodeTys; 387 NodeTys.push_back(MVT::Other); // Returns a chain 388 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 389 SDOperand Ops[] = { Chain, Callee, InFlag }; 390 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 391 InFlag = Chain.getValue(1); 392 393 MVT::ValueType RetTyVT = getValueType(RetTy); 394 395 SDOperand RetVal; 396 if (RetTyVT != MVT::isVoid) { 397 switch (RetTyVT) { 398 default: assert(0 && "Unknown value type to return!"); 399 case MVT::i1: 400 case MVT::i8: 401 case MVT::i16: { 402 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 403 Chain = RetVal.getValue(1); 404 405 // Add a note to keep track of whether it is sign or zero extended. 406 ISD::NodeType AssertKind = ISD::DELETED_NODE; 407 if (RetSExt) 408 AssertKind = ISD::AssertSext; 409 else if (RetZExt) 410 AssertKind = ISD::AssertZext; 411 412 if (AssertKind != ISD::DELETED_NODE) 413 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 414 DAG.getValueType(RetTyVT)); 415 416 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 417 break; 418 } 419 case MVT::i32: 420 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 421 Chain = RetVal.getValue(1); 422 break; 423 case MVT::f32: 424 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 425 Chain = RetVal.getValue(1); 426 break; 427 case MVT::f64: 428 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 429 Chain = RetVal.getValue(1); 430 break; 431 case MVT::i64: 432 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 433 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 434 Lo.getValue(2)); 435 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 436 Chain = Hi.getValue(1); 437 break; 438 } 439 } 440 441 Chain = DAG.getCALLSEQ_END(Chain, 442 DAG.getConstant(ArgsSize, getPointerTy()), 443 DAG.getConstant(0, getPointerTy()), 444 SDOperand()); 445 return std::make_pair(RetVal, Chain); 446} 447 448 449 450//===----------------------------------------------------------------------===// 451// TargetLowering Implementation 452//===----------------------------------------------------------------------===// 453 454/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 455/// condition. 456static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 457 switch (CC) { 458 default: assert(0 && "Unknown integer condition code!"); 459 case ISD::SETEQ: return SPCC::ICC_E; 460 case ISD::SETNE: return SPCC::ICC_NE; 461 case ISD::SETLT: return SPCC::ICC_L; 462 case ISD::SETGT: return SPCC::ICC_G; 463 case ISD::SETLE: return SPCC::ICC_LE; 464 case ISD::SETGE: return SPCC::ICC_GE; 465 case ISD::SETULT: return SPCC::ICC_CS; 466 case ISD::SETULE: return SPCC::ICC_LEU; 467 case ISD::SETUGT: return SPCC::ICC_GU; 468 case ISD::SETUGE: return SPCC::ICC_CC; 469 } 470} 471 472/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 473/// FCC condition. 474static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 475 switch (CC) { 476 default: assert(0 && "Unknown fp condition code!"); 477 case ISD::SETEQ: 478 case ISD::SETOEQ: return SPCC::FCC_E; 479 case ISD::SETNE: 480 case ISD::SETUNE: return SPCC::FCC_NE; 481 case ISD::SETLT: 482 case ISD::SETOLT: return SPCC::FCC_L; 483 case ISD::SETGT: 484 case ISD::SETOGT: return SPCC::FCC_G; 485 case ISD::SETLE: 486 case ISD::SETOLE: return SPCC::FCC_LE; 487 case ISD::SETGE: 488 case ISD::SETOGE: return SPCC::FCC_GE; 489 case ISD::SETULT: return SPCC::FCC_UL; 490 case ISD::SETULE: return SPCC::FCC_ULE; 491 case ISD::SETUGT: return SPCC::FCC_UG; 492 case ISD::SETUGE: return SPCC::FCC_UGE; 493 case ISD::SETUO: return SPCC::FCC_U; 494 case ISD::SETO: return SPCC::FCC_O; 495 case ISD::SETONE: return SPCC::FCC_LG; 496 case ISD::SETUEQ: return SPCC::FCC_UE; 497 } 498} 499 500 501SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 502 : TargetLowering(TM) { 503 504 // Set up the register classes. 505 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 506 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 507 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 508 509 // Turn FP extload into load/fextend 510 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 511 // Sparc doesn't have i1 sign extending load 512 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 513 // Turn FP truncstore into trunc + store. 514 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 515 516 // Custom legalize GlobalAddress nodes into LO/HI parts. 517 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 518 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 519 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 520 521 // Sparc doesn't have sext_inreg, replace them with shl/sra 522 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 523 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 524 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 525 526 // Sparc has no REM or DIVREM operations. 527 setOperationAction(ISD::UREM, MVT::i32, Expand); 528 setOperationAction(ISD::SREM, MVT::i32, Expand); 529 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 530 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 531 532 // Custom expand fp<->sint 533 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 534 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 535 536 // Expand fp<->uint 537 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 538 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 539 540 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 541 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 542 543 // Sparc has no select or setcc: expand to SELECT_CC. 544 setOperationAction(ISD::SELECT, MVT::i32, Expand); 545 setOperationAction(ISD::SELECT, MVT::f32, Expand); 546 setOperationAction(ISD::SELECT, MVT::f64, Expand); 547 setOperationAction(ISD::SETCC, MVT::i32, Expand); 548 setOperationAction(ISD::SETCC, MVT::f32, Expand); 549 setOperationAction(ISD::SETCC, MVT::f64, Expand); 550 551 // Sparc doesn't have BRCOND either, it has BR_CC. 552 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 553 setOperationAction(ISD::BRIND, MVT::Other, Expand); 554 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 555 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 556 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 557 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 558 559 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 560 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 561 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 562 563 // SPARC has no intrinsics for these particular operations. 564 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 565 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 566 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 567 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 568 569 setOperationAction(ISD::FSIN , MVT::f64, Expand); 570 setOperationAction(ISD::FCOS , MVT::f64, Expand); 571 setOperationAction(ISD::FREM , MVT::f64, Expand); 572 setOperationAction(ISD::FSIN , MVT::f32, Expand); 573 setOperationAction(ISD::FCOS , MVT::f32, Expand); 574 setOperationAction(ISD::FREM , MVT::f32, Expand); 575 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 576 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 577 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 578 setOperationAction(ISD::ROTL , MVT::i32, Expand); 579 setOperationAction(ISD::ROTR , MVT::i32, Expand); 580 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 581 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 582 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 583 setOperationAction(ISD::FPOW , MVT::f64, Expand); 584 setOperationAction(ISD::FPOW , MVT::f32, Expand); 585 586 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 587 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 588 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 589 590 // FIXME: Sparc provides these multiplies, but we don't have them yet. 591 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 592 593 // We don't have line number support yet. 594 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 595 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 596 setOperationAction(ISD::LABEL, MVT::Other, Expand); 597 598 // RET must be custom lowered, to meet ABI requirements 599 setOperationAction(ISD::RET , MVT::Other, Custom); 600 601 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 602 setOperationAction(ISD::VASTART , MVT::Other, Custom); 603 // VAARG needs to be lowered to not do unaligned accesses for doubles. 604 setOperationAction(ISD::VAARG , MVT::Other, Custom); 605 606 // Use the default implementation. 607 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 608 setOperationAction(ISD::VAEND , MVT::Other, Expand); 609 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 610 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 611 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 612 613 // No debug info support yet. 614 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 615 setOperationAction(ISD::LABEL, MVT::Other, Expand); 616 setOperationAction(ISD::DECLARE, MVT::Other, Expand); 617 618 setStackPointerRegisterToSaveRestore(SP::O6); 619 620 if (TM.getSubtarget<SparcSubtarget>().isV9()) 621 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 622 623 computeRegisterProperties(); 624} 625 626const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 627 switch (Opcode) { 628 default: return 0; 629 case SPISD::CMPICC: return "SPISD::CMPICC"; 630 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 631 case SPISD::BRICC: return "SPISD::BRICC"; 632 case SPISD::BRFCC: return "SPISD::BRFCC"; 633 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 634 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 635 case SPISD::Hi: return "SPISD::Hi"; 636 case SPISD::Lo: return "SPISD::Lo"; 637 case SPISD::FTOI: return "SPISD::FTOI"; 638 case SPISD::ITOF: return "SPISD::ITOF"; 639 case SPISD::CALL: return "SPISD::CALL"; 640 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 641 } 642} 643 644/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 645/// be zero. Op is expected to be a target specific node. Used by DAG 646/// combiner. 647void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 648 const APInt &Mask, 649 APInt &KnownZero, 650 APInt &KnownOne, 651 const SelectionDAG &DAG, 652 unsigned Depth) const { 653 APInt KnownZero2, KnownOne2; 654 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 655 656 switch (Op.getOpcode()) { 657 default: break; 658 case SPISD::SELECT_ICC: 659 case SPISD::SELECT_FCC: 660 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 661 Depth+1); 662 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 663 Depth+1); 664 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 665 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 666 667 // Only known if known in both the LHS and RHS. 668 KnownOne &= KnownOne2; 669 KnownZero &= KnownZero2; 670 break; 671 } 672} 673 674// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 675// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 676static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 677 ISD::CondCode CC, unsigned &SPCC) { 678 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 679 CC == ISD::SETNE && 680 ((LHS.getOpcode() == SPISD::SELECT_ICC && 681 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 682 (LHS.getOpcode() == SPISD::SELECT_FCC && 683 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 684 isa<ConstantSDNode>(LHS.getOperand(0)) && 685 isa<ConstantSDNode>(LHS.getOperand(1)) && 686 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 687 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 688 SDOperand CMPCC = LHS.getOperand(3); 689 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 690 LHS = CMPCC.getOperand(0); 691 RHS = CMPCC.getOperand(1); 692 } 693} 694 695static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) { 696 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 697 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 698 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 699 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 700 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 701} 702 703static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) { 704 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 705 Constant *C = N->getConstVal(); 706 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 707 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 708 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 709 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 710} 711 712static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 713 // Convert the fp value to integer in an FP register. 714 assert(Op.getValueType() == MVT::i32); 715 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 716 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 717} 718 719static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 720 assert(Op.getOperand(0).getValueType() == MVT::i32); 721 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 722 // Convert the int value to FP in an FP register. 723 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 724} 725 726static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { 727 SDOperand Chain = Op.getOperand(0); 728 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 729 SDOperand LHS = Op.getOperand(2); 730 SDOperand RHS = Op.getOperand(3); 731 SDOperand Dest = Op.getOperand(4); 732 unsigned Opc, SPCC = ~0U; 733 734 // If this is a br_cc of a "setcc", and if the setcc got lowered into 735 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 736 LookThroughSetCC(LHS, RHS, CC, SPCC); 737 738 // Get the condition flag. 739 SDOperand CompareFlag; 740 if (LHS.getValueType() == MVT::i32) { 741 std::vector<MVT::ValueType> VTs; 742 VTs.push_back(MVT::i32); 743 VTs.push_back(MVT::Flag); 744 SDOperand Ops[2] = { LHS, RHS }; 745 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 746 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 747 Opc = SPISD::BRICC; 748 } else { 749 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 750 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 751 Opc = SPISD::BRFCC; 752 } 753 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 754 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 755} 756 757static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 758 SDOperand LHS = Op.getOperand(0); 759 SDOperand RHS = Op.getOperand(1); 760 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 761 SDOperand TrueVal = Op.getOperand(2); 762 SDOperand FalseVal = Op.getOperand(3); 763 unsigned Opc, SPCC = ~0U; 764 765 // If this is a select_cc of a "setcc", and if the setcc got lowered into 766 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 767 LookThroughSetCC(LHS, RHS, CC, SPCC); 768 769 SDOperand CompareFlag; 770 if (LHS.getValueType() == MVT::i32) { 771 std::vector<MVT::ValueType> VTs; 772 VTs.push_back(LHS.getValueType()); // subcc returns a value 773 VTs.push_back(MVT::Flag); 774 SDOperand Ops[2] = { LHS, RHS }; 775 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 776 Opc = SPISD::SELECT_ICC; 777 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 778 } else { 779 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 780 Opc = SPISD::SELECT_FCC; 781 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 782 } 783 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 784 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 785} 786 787static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 788 SparcTargetLowering &TLI) { 789 // vastart just stores the address of the VarArgsFrameIndex slot into the 790 // memory location argument. 791 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 792 DAG.getRegister(SP::I6, MVT::i32), 793 DAG.getConstant(TLI.getVarArgsFrameOffset(), 794 MVT::i32)); 795 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 796 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); 797} 798 799static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) { 800 SDNode *Node = Op.Val; 801 MVT::ValueType VT = Node->getValueType(0); 802 SDOperand InChain = Node->getOperand(0); 803 SDOperand VAListPtr = Node->getOperand(1); 804 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 805 SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); 806 // Increment the pointer, VAList, to the next vaarg 807 SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, 808 DAG.getConstant(MVT::getSizeInBits(VT)/8, 809 MVT::i32)); 810 // Store the incremented VAList to the legalized pointer 811 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 812 VAListPtr, SV, 0); 813 // Load the actual argument out of the pointer VAList, unless this is an 814 // f64 load. 815 if (VT != MVT::f64) 816 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 817 818 // Otherwise, load it as i64, then do a bitconvert. 819 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 820 821 // Bit-Convert the value to f64. 822 SDOperand Ops[2] = { 823 DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 824 V.getValue(1) 825 }; 826 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::f64, MVT::Other), 827 Ops, 2); 828} 829 830static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) { 831 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 832 SDOperand Size = Op.getOperand(1); // Legalize the size. 833 834 unsigned SPReg = SP::O6; 835 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 836 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 837 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 838 839 // The resultant pointer is actually 16 words from the bottom of the stack, 840 // to provide a register spill area. 841 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 842 DAG.getConstant(96, MVT::i32)); 843 std::vector<MVT::ValueType> Tys; 844 Tys.push_back(MVT::i32); 845 Tys.push_back(MVT::Other); 846 SDOperand Ops[2] = { NewVal, Chain }; 847 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 848} 849 850 851SDOperand SparcTargetLowering:: 852LowerOperation(SDOperand Op, SelectionDAG &DAG) { 853 switch (Op.getOpcode()) { 854 default: assert(0 && "Should not custom lower this!"); 855 // Frame & Return address. Currently unimplemented 856 case ISD::RETURNADDR: return SDOperand(); 857 case ISD::FRAMEADDR: return SDOperand(); 858 case ISD::GlobalTLSAddress: 859 assert(0 && "TLS not implemented for Sparc."); 860 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 861 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG); 862 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 863 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 864 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 865 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 866 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 867 case ISD::VAARG: return LowerVAARG(Op, DAG); 868 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 869 case ISD::RET: return LowerRET(Op, DAG); 870 } 871} 872 873MachineBasicBlock * 874SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 875 MachineBasicBlock *BB) { 876 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 877 unsigned BROpcode; 878 unsigned CC; 879 // Figure out the conditional branch opcode to use for this select_cc. 880 switch (MI->getOpcode()) { 881 default: assert(0 && "Unknown SELECT_CC!"); 882 case SP::SELECT_CC_Int_ICC: 883 case SP::SELECT_CC_FP_ICC: 884 case SP::SELECT_CC_DFP_ICC: 885 BROpcode = SP::BCOND; 886 break; 887 case SP::SELECT_CC_Int_FCC: 888 case SP::SELECT_CC_FP_FCC: 889 case SP::SELECT_CC_DFP_FCC: 890 BROpcode = SP::FBCOND; 891 break; 892 } 893 894 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 895 896 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 897 // control-flow pattern. The incoming instruction knows the destination vreg 898 // to set, the condition code register to branch on, the true/false values to 899 // select between, and a branch opcode to use. 900 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 901 ilist<MachineBasicBlock>::iterator It = BB; 902 ++It; 903 904 // thisMBB: 905 // ... 906 // TrueVal = ... 907 // [f]bCC copy1MBB 908 // fallthrough --> copy0MBB 909 MachineBasicBlock *thisMBB = BB; 910 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 911 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 912 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 913 MachineFunction *F = BB->getParent(); 914 F->getBasicBlockList().insert(It, copy0MBB); 915 F->getBasicBlockList().insert(It, sinkMBB); 916 // Update machine-CFG edges by first adding all successors of the current 917 // block to the new block which will contain the Phi node for the select. 918 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 919 e = BB->succ_end(); i != e; ++i) 920 sinkMBB->addSuccessor(*i); 921 // Next, remove all successors of the current block, and add the true 922 // and fallthrough blocks as its successors. 923 while(!BB->succ_empty()) 924 BB->removeSuccessor(BB->succ_begin()); 925 BB->addSuccessor(copy0MBB); 926 BB->addSuccessor(sinkMBB); 927 928 // copy0MBB: 929 // %FalseValue = ... 930 // # fallthrough to sinkMBB 931 BB = copy0MBB; 932 933 // Update machine-CFG edges 934 BB->addSuccessor(sinkMBB); 935 936 // sinkMBB: 937 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 938 // ... 939 BB = sinkMBB; 940 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 941 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 942 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 943 944 delete MI; // The pseudo instruction is gone now. 945 return BB; 946} 947 948