SparcISelLowering.cpp revision 5e45051e0ee8917a88e84d799c5c90840d0c465b
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcRegisterInfo.h"
18#include "SparcTargetMachine.h"
19#include "MCTargetDesc/SparcBaseInfo.h"
20#include "llvm/CodeGen/CallingConvLower.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/SelectionDAG.h"
26#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27#include "llvm/IR/DerivedTypes.h"
28#include "llvm/IR/Function.h"
29#include "llvm/IR/Module.h"
30#include "llvm/Support/ErrorHandling.h"
31using namespace llvm;
32
33
34//===----------------------------------------------------------------------===//
35// Calling Convention Implementation
36//===----------------------------------------------------------------------===//
37
38static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
39                                 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
40                                 ISD::ArgFlagsTy &ArgFlags, CCState &State)
41{
42  assert (ArgFlags.isSRet());
43
44  // Assign SRet argument.
45  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
46                                         0,
47                                         LocVT, LocInfo));
48  return true;
49}
50
51static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
52                                MVT &LocVT, CCValAssign::LocInfo &LocInfo,
53                                ISD::ArgFlagsTy &ArgFlags, CCState &State)
54{
55  static const uint16_t RegList[] = {
56    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
57  };
58  // Try to get first reg.
59  if (unsigned Reg = State.AllocateReg(RegList, 6)) {
60    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
61  } else {
62    // Assign whole thing in stack.
63    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
64                                           State.AllocateStack(8,4),
65                                           LocVT, LocInfo));
66    return true;
67  }
68
69  // Try to get second reg.
70  if (unsigned Reg = State.AllocateReg(RegList, 6))
71    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
72  else
73    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
74                                           State.AllocateStack(4,4),
75                                           LocVT, LocInfo));
76  return true;
77}
78
79// Allocate a full-sized argument for the 64-bit ABI.
80static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
81                            MVT &LocVT, CCValAssign::LocInfo &LocInfo,
82                            ISD::ArgFlagsTy &ArgFlags, CCState &State) {
83  assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
84         "Can't handle non-64 bits locations");
85
86  // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
87  unsigned Offset = State.AllocateStack(8, 8);
88  unsigned Reg = 0;
89
90  if (LocVT == MVT::i64 && Offset < 6*8)
91    // Promote integers to %i0-%i5.
92    Reg = SP::I0 + Offset/8;
93  else if (LocVT == MVT::f64 && Offset < 16*8)
94    // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
95    Reg = SP::D0 + Offset/8;
96  else if (LocVT == MVT::f32 && Offset < 16*8)
97    // Promote floats to %f1, %f3, ...
98    Reg = SP::F1 + Offset/4;
99
100  // Promote to register when possible, otherwise use the stack slot.
101  if (Reg) {
102    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
103    return true;
104  }
105
106  // This argument goes on the stack in an 8-byte slot.
107  // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
108  // the right-aligned float. The first 4 bytes of the stack slot are undefined.
109  if (LocVT == MVT::f32)
110    Offset += 4;
111
112  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
113  return true;
114}
115
116// Allocate a half-sized argument for the 64-bit ABI.
117//
118// This is used when passing { float, int } structs by value in registers.
119static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
120                            MVT &LocVT, CCValAssign::LocInfo &LocInfo,
121                            ISD::ArgFlagsTy &ArgFlags, CCState &State) {
122  assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
123  unsigned Offset = State.AllocateStack(4, 4);
124
125  if (LocVT == MVT::f32 && Offset < 16*8) {
126    // Promote floats to %f0-%f31.
127    State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
128                                     LocVT, LocInfo));
129    return true;
130  }
131
132  if (LocVT == MVT::i32 && Offset < 6*8) {
133    // Promote integers to %i0-%i5, using half the register.
134    unsigned Reg = SP::I0 + Offset/8;
135    LocVT = MVT::i64;
136    LocInfo = CCValAssign::AExt;
137
138    // Set the Custom bit if this i32 goes in the high bits of a register.
139    if (Offset % 8 == 0)
140      State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
141                                             LocVT, LocInfo));
142    else
143      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
144    return true;
145  }
146
147  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
148  return true;
149}
150
151#include "SparcGenCallingConv.inc"
152
153// The calling conventions in SparcCallingConv.td are described in terms of the
154// callee's register window. This function translates registers to the
155// corresponding caller window %o register.
156static unsigned toCallerWindow(unsigned Reg) {
157  assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
158  if (Reg >= SP::I0 && Reg <= SP::I7)
159    return Reg - SP::I0 + SP::O0;
160  return Reg;
161}
162
163SDValue
164SparcTargetLowering::LowerReturn(SDValue Chain,
165                                 CallingConv::ID CallConv, bool IsVarArg,
166                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
167                                 const SmallVectorImpl<SDValue> &OutVals,
168                                 SDLoc DL, SelectionDAG &DAG) const {
169  if (Subtarget->is64Bit())
170    return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
171  return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
172}
173
174SDValue
175SparcTargetLowering::LowerReturn_32(SDValue Chain,
176                                    CallingConv::ID CallConv, bool IsVarArg,
177                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
178                                    const SmallVectorImpl<SDValue> &OutVals,
179                                    SDLoc DL, SelectionDAG &DAG) const {
180  MachineFunction &MF = DAG.getMachineFunction();
181
182  // CCValAssign - represent the assignment of the return value to locations.
183  SmallVector<CCValAssign, 16> RVLocs;
184
185  // CCState - Info about the registers and stack slot.
186  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
187                 DAG.getTarget(), RVLocs, *DAG.getContext());
188
189  // Analyze return values.
190  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
191
192  SDValue Flag;
193  SmallVector<SDValue, 4> RetOps(1, Chain);
194  // Make room for the return address offset.
195  RetOps.push_back(SDValue());
196
197  // Copy the result values into the output registers.
198  for (unsigned i = 0; i != RVLocs.size(); ++i) {
199    CCValAssign &VA = RVLocs[i];
200    assert(VA.isRegLoc() && "Can only return in registers!");
201
202    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
203                             OutVals[i], Flag);
204
205    // Guarantee that all emitted copies are stuck together with flags.
206    Flag = Chain.getValue(1);
207    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
208  }
209
210  unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
211  // If the function returns a struct, copy the SRetReturnReg to I0
212  if (MF.getFunction()->hasStructRetAttr()) {
213    SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
214    unsigned Reg = SFI->getSRetReturnReg();
215    if (!Reg)
216      llvm_unreachable("sret virtual register not created in the entry block");
217    SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
218    Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
219    Flag = Chain.getValue(1);
220    RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
221    RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
222  }
223
224  RetOps[0] = Chain;  // Update chain.
225  RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
226
227  // Add the flag if we have it.
228  if (Flag.getNode())
229    RetOps.push_back(Flag);
230
231  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
232                     &RetOps[0], RetOps.size());
233}
234
235// Lower return values for the 64-bit ABI.
236// Return values are passed the exactly the same way as function arguments.
237SDValue
238SparcTargetLowering::LowerReturn_64(SDValue Chain,
239                                    CallingConv::ID CallConv, bool IsVarArg,
240                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
241                                    const SmallVectorImpl<SDValue> &OutVals,
242                                    SDLoc DL, SelectionDAG &DAG) const {
243  // CCValAssign - represent the assignment of the return value to locations.
244  SmallVector<CCValAssign, 16> RVLocs;
245
246  // CCState - Info about the registers and stack slot.
247  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
248                 DAG.getTarget(), RVLocs, *DAG.getContext());
249
250  // Analyze return values.
251  CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
252
253  SDValue Flag;
254  SmallVector<SDValue, 4> RetOps(1, Chain);
255
256  // The second operand on the return instruction is the return address offset.
257  // The return address is always %i7+8 with the 64-bit ABI.
258  RetOps.push_back(DAG.getConstant(8, MVT::i32));
259
260  // Copy the result values into the output registers.
261  for (unsigned i = 0; i != RVLocs.size(); ++i) {
262    CCValAssign &VA = RVLocs[i];
263    assert(VA.isRegLoc() && "Can only return in registers!");
264    SDValue OutVal = OutVals[i];
265
266    // Integer return values must be sign or zero extended by the callee.
267    switch (VA.getLocInfo()) {
268    case CCValAssign::SExt:
269      OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
270      break;
271    case CCValAssign::ZExt:
272      OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
273      break;
274    case CCValAssign::AExt:
275      OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
276    default:
277      break;
278    }
279
280    // The custom bit on an i32 return value indicates that it should be passed
281    // in the high bits of the register.
282    if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
283      OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
284                           DAG.getConstant(32, MVT::i32));
285
286      // The next value may go in the low bits of the same register.
287      // Handle both at once.
288      if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
289        SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
290        OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
291        // Skip the next value, it's already done.
292        ++i;
293      }
294    }
295
296    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
297
298    // Guarantee that all emitted copies are stuck together with flags.
299    Flag = Chain.getValue(1);
300    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
301  }
302
303  RetOps[0] = Chain;  // Update chain.
304
305  // Add the flag if we have it.
306  if (Flag.getNode())
307    RetOps.push_back(Flag);
308
309  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
310                     &RetOps[0], RetOps.size());
311}
312
313SDValue SparcTargetLowering::
314LowerFormalArguments(SDValue Chain,
315                     CallingConv::ID CallConv,
316                     bool IsVarArg,
317                     const SmallVectorImpl<ISD::InputArg> &Ins,
318                     SDLoc DL,
319                     SelectionDAG &DAG,
320                     SmallVectorImpl<SDValue> &InVals) const {
321  if (Subtarget->is64Bit())
322    return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
323                                   DL, DAG, InVals);
324  return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
325                                 DL, DAG, InVals);
326}
327
328/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
329/// passed in either one or two GPRs, including FP values.  TODO: we should
330/// pass FP values in FP registers for fastcc functions.
331SDValue SparcTargetLowering::
332LowerFormalArguments_32(SDValue Chain,
333                        CallingConv::ID CallConv,
334                        bool isVarArg,
335                        const SmallVectorImpl<ISD::InputArg> &Ins,
336                        SDLoc dl,
337                        SelectionDAG &DAG,
338                        SmallVectorImpl<SDValue> &InVals) const {
339  MachineFunction &MF = DAG.getMachineFunction();
340  MachineRegisterInfo &RegInfo = MF.getRegInfo();
341  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
342
343  // Assign locations to all of the incoming arguments.
344  SmallVector<CCValAssign, 16> ArgLocs;
345  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
346                 getTargetMachine(), ArgLocs, *DAG.getContext());
347  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
348
349  const unsigned StackOffset = 92;
350
351  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
352    CCValAssign &VA = ArgLocs[i];
353
354    if (i == 0  && Ins[i].Flags.isSRet()) {
355      // Get SRet from [%fp+64].
356      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
357      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
358      SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
359                                MachinePointerInfo(),
360                                false, false, false, 0);
361      InVals.push_back(Arg);
362      continue;
363    }
364
365    if (VA.isRegLoc()) {
366      if (VA.needsCustom()) {
367        assert(VA.getLocVT() == MVT::f64);
368        unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
369        MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
370        SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
371
372        assert(i+1 < e);
373        CCValAssign &NextVA = ArgLocs[++i];
374
375        SDValue LoVal;
376        if (NextVA.isMemLoc()) {
377          int FrameIdx = MF.getFrameInfo()->
378            CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
379          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
380          LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
381                              MachinePointerInfo(),
382                              false, false, false, 0);
383        } else {
384          unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
385                                        &SP::IntRegsRegClass);
386          LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
387        }
388        SDValue WholeValue =
389          DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
390        WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
391        InVals.push_back(WholeValue);
392        continue;
393      }
394      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
395      MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
396      SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
397      if (VA.getLocVT() == MVT::f32)
398        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
399      else if (VA.getLocVT() != MVT::i32) {
400        Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
401                          DAG.getValueType(VA.getLocVT()));
402        Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
403      }
404      InVals.push_back(Arg);
405      continue;
406    }
407
408    assert(VA.isMemLoc());
409
410    unsigned Offset = VA.getLocMemOffset()+StackOffset;
411
412    if (VA.needsCustom()) {
413      assert(VA.getValVT() == MVT::f64);
414      // If it is double-word aligned, just load.
415      if (Offset % 8 == 0) {
416        int FI = MF.getFrameInfo()->CreateFixedObject(8,
417                                                      Offset,
418                                                      true);
419        SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
420        SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
421                                   MachinePointerInfo(),
422                                   false,false, false, 0);
423        InVals.push_back(Load);
424        continue;
425      }
426
427      int FI = MF.getFrameInfo()->CreateFixedObject(4,
428                                                    Offset,
429                                                    true);
430      SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
431      SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
432                                  MachinePointerInfo(),
433                                  false, false, false, 0);
434      int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
435                                                     Offset+4,
436                                                     true);
437      SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
438
439      SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
440                                  MachinePointerInfo(),
441                                  false, false, false, 0);
442
443      SDValue WholeValue =
444        DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
445      WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
446      InVals.push_back(WholeValue);
447      continue;
448    }
449
450    int FI = MF.getFrameInfo()->CreateFixedObject(4,
451                                                  Offset,
452                                                  true);
453    SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
454    SDValue Load ;
455    if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
456      Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
457                         MachinePointerInfo(),
458                         false, false, false, 0);
459    } else {
460      ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
461      // Sparc is big endian, so add an offset based on the ObjectVT.
462      unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
463      FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
464                          DAG.getConstant(Offset, MVT::i32));
465      Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
466                            MachinePointerInfo(),
467                            VA.getValVT(), false, false,0);
468      Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
469    }
470    InVals.push_back(Load);
471  }
472
473  if (MF.getFunction()->hasStructRetAttr()) {
474    // Copy the SRet Argument to SRetReturnReg.
475    SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
476    unsigned Reg = SFI->getSRetReturnReg();
477    if (!Reg) {
478      Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
479      SFI->setSRetReturnReg(Reg);
480    }
481    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
482    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
483  }
484
485  // Store remaining ArgRegs to the stack if this is a varargs function.
486  if (isVarArg) {
487    static const uint16_t ArgRegs[] = {
488      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
489    };
490    unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
491    const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
492    unsigned ArgOffset = CCInfo.getNextStackOffset();
493    if (NumAllocated == 6)
494      ArgOffset += StackOffset;
495    else {
496      assert(!ArgOffset);
497      ArgOffset = 68+4*NumAllocated;
498    }
499
500    // Remember the vararg offset for the va_start implementation.
501    FuncInfo->setVarArgsFrameOffset(ArgOffset);
502
503    std::vector<SDValue> OutChains;
504
505    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
506      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
507      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
508      SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
509
510      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
511                                                          true);
512      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
513
514      OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
515                                       MachinePointerInfo(),
516                                       false, false, 0));
517      ArgOffset += 4;
518    }
519
520    if (!OutChains.empty()) {
521      OutChains.push_back(Chain);
522      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
523                          &OutChains[0], OutChains.size());
524    }
525  }
526
527  return Chain;
528}
529
530// Lower formal arguments for the 64 bit ABI.
531SDValue SparcTargetLowering::
532LowerFormalArguments_64(SDValue Chain,
533                        CallingConv::ID CallConv,
534                        bool IsVarArg,
535                        const SmallVectorImpl<ISD::InputArg> &Ins,
536                        SDLoc DL,
537                        SelectionDAG &DAG,
538                        SmallVectorImpl<SDValue> &InVals) const {
539  MachineFunction &MF = DAG.getMachineFunction();
540
541  // Analyze arguments according to CC_Sparc64.
542  SmallVector<CCValAssign, 16> ArgLocs;
543  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
544                 getTargetMachine(), ArgLocs, *DAG.getContext());
545  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
546
547  // The argument array begins at %fp+BIAS+128, after the register save area.
548  const unsigned ArgArea = 128;
549
550  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
551    CCValAssign &VA = ArgLocs[i];
552    if (VA.isRegLoc()) {
553      // This argument is passed in a register.
554      // All integer register arguments are promoted by the caller to i64.
555
556      // Create a virtual register for the promoted live-in value.
557      unsigned VReg = MF.addLiveIn(VA.getLocReg(),
558                                   getRegClassFor(VA.getLocVT()));
559      SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
560
561      // Get the high bits for i32 struct elements.
562      if (VA.getValVT() == MVT::i32 && VA.needsCustom())
563        Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
564                          DAG.getConstant(32, MVT::i32));
565
566      // The caller promoted the argument, so insert an Assert?ext SDNode so we
567      // won't promote the value again in this function.
568      switch (VA.getLocInfo()) {
569      case CCValAssign::SExt:
570        Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
571                          DAG.getValueType(VA.getValVT()));
572        break;
573      case CCValAssign::ZExt:
574        Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
575                          DAG.getValueType(VA.getValVT()));
576        break;
577      default:
578        break;
579      }
580
581      // Truncate the register down to the argument type.
582      if (VA.isExtInLoc())
583        Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
584
585      InVals.push_back(Arg);
586      continue;
587    }
588
589    // The registers are exhausted. This argument was passed on the stack.
590    assert(VA.isMemLoc());
591    // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
592    // beginning of the arguments area at %fp+BIAS+128.
593    unsigned Offset = VA.getLocMemOffset() + ArgArea;
594    unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
595    // Adjust offset for extended arguments, SPARC is big-endian.
596    // The caller will have written the full slot with extended bytes, but we
597    // prefer our own extending loads.
598    if (VA.isExtInLoc())
599      Offset += 8 - ValSize;
600    int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
601    InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
602                                 DAG.getFrameIndex(FI, getPointerTy()),
603                                 MachinePointerInfo::getFixedStack(FI),
604                                 false, false, false, 0));
605  }
606
607  if (!IsVarArg)
608    return Chain;
609
610  // This function takes variable arguments, some of which may have been passed
611  // in registers %i0-%i5. Variable floating point arguments are never passed
612  // in floating point registers. They go on %i0-%i5 or on the stack like
613  // integer arguments.
614  //
615  // The va_start intrinsic needs to know the offset to the first variable
616  // argument.
617  unsigned ArgOffset = CCInfo.getNextStackOffset();
618  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
619  // Skip the 128 bytes of register save area.
620  FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
621                                  Subtarget->getStackPointerBias());
622
623  // Save the variable arguments that were passed in registers.
624  // The caller is required to reserve stack space for 6 arguments regardless
625  // of how many arguments were actually passed.
626  SmallVector<SDValue, 8> OutChains;
627  for (; ArgOffset < 6*8; ArgOffset += 8) {
628    unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
629    SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
630    int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
631    OutChains.push_back(DAG.getStore(Chain, DL, VArg,
632                                     DAG.getFrameIndex(FI, getPointerTy()),
633                                     MachinePointerInfo::getFixedStack(FI),
634                                     false, false, 0));
635  }
636
637  if (!OutChains.empty())
638    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
639                        &OutChains[0], OutChains.size());
640
641  return Chain;
642}
643
644SDValue
645SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
646                               SmallVectorImpl<SDValue> &InVals) const {
647  if (Subtarget->is64Bit())
648    return LowerCall_64(CLI, InVals);
649  return LowerCall_32(CLI, InVals);
650}
651
652static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
653                                     ImmutableCallSite *CS) {
654  if (CS)
655    return CS->hasFnAttr(Attribute::ReturnsTwice);
656
657  const Function *CalleeFn = 0;
658  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
659    CalleeFn = dyn_cast<Function>(G->getGlobal());
660  } else if (ExternalSymbolSDNode *E =
661             dyn_cast<ExternalSymbolSDNode>(Callee)) {
662    const Function *Fn = DAG.getMachineFunction().getFunction();
663    const Module *M = Fn->getParent();
664    const char *CalleeName = E->getSymbol();
665    CalleeFn = M->getFunction(CalleeName);
666  }
667
668  if (!CalleeFn)
669    return false;
670  return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
671}
672
673// Lower a call for the 32-bit ABI.
674SDValue
675SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
676                                  SmallVectorImpl<SDValue> &InVals) const {
677  SelectionDAG &DAG                     = CLI.DAG;
678  SDLoc &dl                             = CLI.DL;
679  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
680  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
681  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
682  SDValue Chain                         = CLI.Chain;
683  SDValue Callee                        = CLI.Callee;
684  bool &isTailCall                      = CLI.IsTailCall;
685  CallingConv::ID CallConv              = CLI.CallConv;
686  bool isVarArg                         = CLI.IsVarArg;
687
688  // Sparc target does not yet support tail call optimization.
689  isTailCall = false;
690
691  // Analyze operands of the call, assigning locations to each operand.
692  SmallVector<CCValAssign, 16> ArgLocs;
693  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
694                 DAG.getTarget(), ArgLocs, *DAG.getContext());
695  CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
696
697  // Get the size of the outgoing arguments stack space requirement.
698  unsigned ArgsSize = CCInfo.getNextStackOffset();
699
700  // Keep stack frames 8-byte aligned.
701  ArgsSize = (ArgsSize+7) & ~7;
702
703  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
704
705  // Create local copies for byval args.
706  SmallVector<SDValue, 8> ByValArgs;
707  for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {
708    ISD::ArgFlagsTy Flags = Outs[i].Flags;
709    if (!Flags.isByVal())
710      continue;
711
712    SDValue Arg = OutVals[i];
713    unsigned Size = Flags.getByValSize();
714    unsigned Align = Flags.getByValAlign();
715
716    int FI = MFI->CreateStackObject(Size, Align, false);
717    SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
718    SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
719
720    Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
721                          false,        // isVolatile,
722                          (Size <= 32), // AlwaysInline if size <= 32
723                          MachinePointerInfo(), MachinePointerInfo());
724    ByValArgs.push_back(FIPtr);
725  }
726
727  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
728                               dl);
729
730  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
731  SmallVector<SDValue, 8> MemOpChains;
732
733  const unsigned StackOffset = 92;
734  bool hasStructRetAttr = false;
735  // Walk the register/memloc assignments, inserting copies/loads.
736  for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
737       i != e;
738       ++i, ++realArgIdx) {
739    CCValAssign &VA = ArgLocs[i];
740    SDValue Arg = OutVals[realArgIdx];
741
742    ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
743
744    // Use local copy if it is a byval arg.
745    if (Flags.isByVal())
746      Arg = ByValArgs[byvalArgIdx++];
747
748    // Promote the value if needed.
749    switch (VA.getLocInfo()) {
750    default: llvm_unreachable("Unknown loc info!");
751    case CCValAssign::Full: break;
752    case CCValAssign::SExt:
753      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
754      break;
755    case CCValAssign::ZExt:
756      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
757      break;
758    case CCValAssign::AExt:
759      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
760      break;
761    case CCValAssign::BCvt:
762      Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
763      break;
764    }
765
766    if (Flags.isSRet()) {
767      assert(VA.needsCustom());
768      // store SRet argument in %sp+64
769      SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
770      SDValue PtrOff = DAG.getIntPtrConstant(64);
771      PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
772      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
773                                         MachinePointerInfo(),
774                                         false, false, 0));
775      hasStructRetAttr = true;
776      continue;
777    }
778
779    if (VA.needsCustom()) {
780      assert(VA.getLocVT() == MVT::f64);
781
782      if (VA.isMemLoc()) {
783        unsigned Offset = VA.getLocMemOffset() + StackOffset;
784        // if it is double-word aligned, just store.
785        if (Offset % 8 == 0) {
786          SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
787          SDValue PtrOff = DAG.getIntPtrConstant(Offset);
788          PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
789          MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
790                                             MachinePointerInfo(),
791                                             false, false, 0));
792          continue;
793        }
794      }
795
796      SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
797      SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
798                                   Arg, StackPtr, MachinePointerInfo(),
799                                   false, false, 0);
800      // Sparc is big-endian, so the high part comes first.
801      SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
802                               MachinePointerInfo(), false, false, false, 0);
803      // Increment the pointer to the other half.
804      StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
805                             DAG.getIntPtrConstant(4));
806      // Load the low part.
807      SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
808                               MachinePointerInfo(), false, false, false, 0);
809
810      if (VA.isRegLoc()) {
811        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
812        assert(i+1 != e);
813        CCValAssign &NextVA = ArgLocs[++i];
814        if (NextVA.isRegLoc()) {
815          RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
816        } else {
817          // Store the low part in stack.
818          unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
819          SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
820          SDValue PtrOff = DAG.getIntPtrConstant(Offset);
821          PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
822          MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
823                                             MachinePointerInfo(),
824                                             false, false, 0));
825        }
826      } else {
827        unsigned Offset = VA.getLocMemOffset() + StackOffset;
828        // Store the high part.
829        SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
830        SDValue PtrOff = DAG.getIntPtrConstant(Offset);
831        PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
832        MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
833                                           MachinePointerInfo(),
834                                           false, false, 0));
835        // Store the low part.
836        PtrOff = DAG.getIntPtrConstant(Offset+4);
837        PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
838        MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
839                                           MachinePointerInfo(),
840                                           false, false, 0));
841      }
842      continue;
843    }
844
845    // Arguments that can be passed on register must be kept at
846    // RegsToPass vector
847    if (VA.isRegLoc()) {
848      if (VA.getLocVT() != MVT::f32) {
849        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
850        continue;
851      }
852      Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
853      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
854      continue;
855    }
856
857    assert(VA.isMemLoc());
858
859    // Create a store off the stack pointer for this argument.
860    SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
861    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
862    PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
863    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
864                                       MachinePointerInfo(),
865                                       false, false, 0));
866  }
867
868
869  // Emit all stores, make sure the occur before any copies into physregs.
870  if (!MemOpChains.empty())
871    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
872                        &MemOpChains[0], MemOpChains.size());
873
874  // Build a sequence of copy-to-reg nodes chained together with token
875  // chain and flag operands which copy the outgoing args into registers.
876  // The InFlag in necessary since all emitted instructions must be
877  // stuck together.
878  SDValue InFlag;
879  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
880    unsigned Reg = toCallerWindow(RegsToPass[i].first);
881    Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
882    InFlag = Chain.getValue(1);
883  }
884
885  unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
886  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
887
888  // If the callee is a GlobalAddress node (quite common, every direct call is)
889  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
890  // Likewise ExternalSymbol -> TargetExternalSymbol.
891  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
892    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
893  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
894    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
895
896  // Returns a chain & a flag for retval copy to use
897  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
898  SmallVector<SDValue, 8> Ops;
899  Ops.push_back(Chain);
900  Ops.push_back(Callee);
901  if (hasStructRetAttr)
902    Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
903  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
904    Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
905                                  RegsToPass[i].second.getValueType()));
906
907  // Add a register mask operand representing the call-preserved registers.
908  const SparcRegisterInfo *TRI =
909    ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
910  const uint32_t *Mask = ((hasReturnsTwice)
911                          ? TRI->getRTCallPreservedMask(CallConv)
912                          : TRI->getCallPreservedMask(CallConv));
913  assert(Mask && "Missing call preserved mask for calling convention");
914  Ops.push_back(DAG.getRegisterMask(Mask));
915
916  if (InFlag.getNode())
917    Ops.push_back(InFlag);
918
919  Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
920  InFlag = Chain.getValue(1);
921
922  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
923                             DAG.getIntPtrConstant(0, true), InFlag, dl);
924  InFlag = Chain.getValue(1);
925
926  // Assign locations to each value returned by this call.
927  SmallVector<CCValAssign, 16> RVLocs;
928  CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
929                 DAG.getTarget(), RVLocs, *DAG.getContext());
930
931  RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
932
933  // Copy all of the result registers out of their specified physreg.
934  for (unsigned i = 0; i != RVLocs.size(); ++i) {
935    Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
936                               RVLocs[i].getValVT(), InFlag).getValue(1);
937    InFlag = Chain.getValue(2);
938    InVals.push_back(Chain.getValue(0));
939  }
940
941  return Chain;
942}
943
944// This functions returns true if CalleeName is a ABI function that returns
945// a long double (fp128).
946static bool isFP128ABICall(const char *CalleeName)
947{
948  static const char *const ABICalls[] =
949    {  "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
950       "_Q_sqrt", "_Q_neg",
951       "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
952       0
953    };
954  for (const char * const *I = ABICalls; I != 0; ++I)
955    if (strcmp(CalleeName, *I) == 0)
956      return true;
957  return false;
958}
959
960unsigned
961SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
962{
963  const Function *CalleeFn = 0;
964  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
965    CalleeFn = dyn_cast<Function>(G->getGlobal());
966  } else if (ExternalSymbolSDNode *E =
967             dyn_cast<ExternalSymbolSDNode>(Callee)) {
968    const Function *Fn = DAG.getMachineFunction().getFunction();
969    const Module *M = Fn->getParent();
970    const char *CalleeName = E->getSymbol();
971    CalleeFn = M->getFunction(CalleeName);
972    if (!CalleeFn && isFP128ABICall(CalleeName))
973      return 16; // Return sizeof(fp128)
974  }
975
976  if (!CalleeFn)
977    return 0;
978
979  assert(CalleeFn->hasStructRetAttr() &&
980         "Callee does not have the StructRet attribute.");
981
982  PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
983  Type *ElementTy = Ty->getElementType();
984  return getDataLayout()->getTypeAllocSize(ElementTy);
985}
986
987
988// Fixup floating point arguments in the ... part of a varargs call.
989//
990// The SPARC v9 ABI requires that floating point arguments are treated the same
991// as integers when calling a varargs function. This does not apply to the
992// fixed arguments that are part of the function's prototype.
993//
994// This function post-processes a CCValAssign array created by
995// AnalyzeCallOperands().
996static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
997                                   ArrayRef<ISD::OutputArg> Outs) {
998  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
999    const CCValAssign &VA = ArgLocs[i];
1000    // FIXME: What about f32 arguments? C promotes them to f64 when calling
1001    // varargs functions.
1002    if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64)
1003      continue;
1004    // The fixed arguments to a varargs function still go in FP registers.
1005    if (Outs[VA.getValNo()].IsFixed)
1006      continue;
1007
1008    // This floating point argument should be reassigned.
1009    CCValAssign NewVA;
1010
1011    // Determine the offset into the argument array.
1012    unsigned Offset = 8 * (VA.getLocReg() - SP::D0);
1013    assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1014
1015    if (Offset < 6*8) {
1016      // This argument should go in %i0-%i5.
1017      unsigned IReg = SP::I0 + Offset/8;
1018      // Full register, just bitconvert into i64.
1019      NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1020                                  IReg, MVT::i64, CCValAssign::BCvt);
1021    } else {
1022      // This needs to go to memory, we're out of integer registers.
1023      NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1024                                  Offset, VA.getLocVT(), VA.getLocInfo());
1025    }
1026    ArgLocs[i] = NewVA;
1027  }
1028}
1029
1030// Lower a call for the 64-bit ABI.
1031SDValue
1032SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1033                                  SmallVectorImpl<SDValue> &InVals) const {
1034  SelectionDAG &DAG = CLI.DAG;
1035  SDLoc DL = CLI.DL;
1036  SDValue Chain = CLI.Chain;
1037
1038  // Sparc target does not yet support tail call optimization.
1039  CLI.IsTailCall = false;
1040
1041  // Analyze operands of the call, assigning locations to each operand.
1042  SmallVector<CCValAssign, 16> ArgLocs;
1043  CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1044                 DAG.getTarget(), ArgLocs, *DAG.getContext());
1045  CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1046
1047  // Get the size of the outgoing arguments stack space requirement.
1048  // The stack offset computed by CC_Sparc64 includes all arguments.
1049  // Called functions expect 6 argument words to exist in the stack frame, used
1050  // or not.
1051  unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1052
1053  // Keep stack frames 16-byte aligned.
1054  ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1055
1056  // Varargs calls require special treatment.
1057  if (CLI.IsVarArg)
1058    fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1059
1060  // Adjust the stack pointer to make room for the arguments.
1061  // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1062  // with more than 6 arguments.
1063  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1064                               DL);
1065
1066  // Collect the set of registers to pass to the function and their values.
1067  // This will be emitted as a sequence of CopyToReg nodes glued to the call
1068  // instruction.
1069  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1070
1071  // Collect chains from all the memory opeations that copy arguments to the
1072  // stack. They must follow the stack pointer adjustment above and precede the
1073  // call instruction itself.
1074  SmallVector<SDValue, 8> MemOpChains;
1075
1076  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1077    const CCValAssign &VA = ArgLocs[i];
1078    SDValue Arg = CLI.OutVals[i];
1079
1080    // Promote the value if needed.
1081    switch (VA.getLocInfo()) {
1082    default:
1083      llvm_unreachable("Unknown location info!");
1084    case CCValAssign::Full:
1085      break;
1086    case CCValAssign::SExt:
1087      Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1088      break;
1089    case CCValAssign::ZExt:
1090      Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1091      break;
1092    case CCValAssign::AExt:
1093      Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1094      break;
1095    case CCValAssign::BCvt:
1096      Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1097      break;
1098    }
1099
1100    if (VA.isRegLoc()) {
1101      // The custom bit on an i32 return value indicates that it should be
1102      // passed in the high bits of the register.
1103      if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1104        Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1105                          DAG.getConstant(32, MVT::i32));
1106
1107        // The next value may go in the low bits of the same register.
1108        // Handle both at once.
1109        if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1110            ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1111          SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1112                                   CLI.OutVals[i+1]);
1113          Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1114          // Skip the next value, it's already done.
1115          ++i;
1116        }
1117      }
1118      RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1119      continue;
1120    }
1121
1122    assert(VA.isMemLoc());
1123
1124    // Create a store off the stack pointer for this argument.
1125    SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1126    // The argument area starts at %fp+BIAS+128 in the callee frame,
1127    // %sp+BIAS+128 in ours.
1128    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1129                                           Subtarget->getStackPointerBias() +
1130                                           128);
1131    PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1132    MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1133                                       MachinePointerInfo(),
1134                                       false, false, 0));
1135  }
1136
1137  // Emit all stores, make sure they occur before the call.
1138  if (!MemOpChains.empty())
1139    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1140                        &MemOpChains[0], MemOpChains.size());
1141
1142  // Build a sequence of CopyToReg nodes glued together with token chain and
1143  // glue operands which copy the outgoing args into registers. The InGlue is
1144  // necessary since all emitted instructions must be stuck together in order
1145  // to pass the live physical registers.
1146  SDValue InGlue;
1147  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1148    Chain = DAG.getCopyToReg(Chain, DL,
1149                             RegsToPass[i].first, RegsToPass[i].second, InGlue);
1150    InGlue = Chain.getValue(1);
1151  }
1152
1153  // If the callee is a GlobalAddress node (quite common, every direct call is)
1154  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1155  // Likewise ExternalSymbol -> TargetExternalSymbol.
1156  SDValue Callee = CLI.Callee;
1157  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1158  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1159    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy());
1160  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1161    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
1162
1163  // Build the operands for the call instruction itself.
1164  SmallVector<SDValue, 8> Ops;
1165  Ops.push_back(Chain);
1166  Ops.push_back(Callee);
1167  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1168    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1169                                  RegsToPass[i].second.getValueType()));
1170
1171  // Add a register mask operand representing the call-preserved registers.
1172  const SparcRegisterInfo *TRI =
1173    ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
1174  const uint32_t *Mask = ((hasReturnsTwice)
1175                          ? TRI->getRTCallPreservedMask(CLI.CallConv)
1176                          : TRI->getCallPreservedMask(CLI.CallConv));
1177  assert(Mask && "Missing call preserved mask for calling convention");
1178  Ops.push_back(DAG.getRegisterMask(Mask));
1179
1180  // Make sure the CopyToReg nodes are glued to the call instruction which
1181  // consumes the registers.
1182  if (InGlue.getNode())
1183    Ops.push_back(InGlue);
1184
1185  // Now the call itself.
1186  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1187  Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
1188  InGlue = Chain.getValue(1);
1189
1190  // Revert the stack pointer immediately after the call.
1191  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1192                             DAG.getIntPtrConstant(0, true), InGlue, DL);
1193  InGlue = Chain.getValue(1);
1194
1195  // Now extract the return values. This is more or less the same as
1196  // LowerFormalArguments_64.
1197
1198  // Assign locations to each value returned by this call.
1199  SmallVector<CCValAssign, 16> RVLocs;
1200  CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1201                 DAG.getTarget(), RVLocs, *DAG.getContext());
1202  RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
1203
1204  // Copy all of the result registers out of their specified physreg.
1205  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1206    CCValAssign &VA = RVLocs[i];
1207    unsigned Reg = toCallerWindow(VA.getLocReg());
1208
1209    // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1210    // reside in the same register in the high and low bits. Reuse the
1211    // CopyFromReg previous node to avoid duplicate copies.
1212    SDValue RV;
1213    if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1214      if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1215        RV = Chain.getValue(0);
1216
1217    // But usually we'll create a new CopyFromReg for a different register.
1218    if (!RV.getNode()) {
1219      RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1220      Chain = RV.getValue(1);
1221      InGlue = Chain.getValue(2);
1222    }
1223
1224    // Get the high bits for i32 struct elements.
1225    if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1226      RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1227                       DAG.getConstant(32, MVT::i32));
1228
1229    // The callee promoted the return value, so insert an Assert?ext SDNode so
1230    // we won't promote the value again in this function.
1231    switch (VA.getLocInfo()) {
1232    case CCValAssign::SExt:
1233      RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1234                       DAG.getValueType(VA.getValVT()));
1235      break;
1236    case CCValAssign::ZExt:
1237      RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1238                       DAG.getValueType(VA.getValVT()));
1239      break;
1240    default:
1241      break;
1242    }
1243
1244    // Truncate the register down to the return value type.
1245    if (VA.isExtInLoc())
1246      RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1247
1248    InVals.push_back(RV);
1249  }
1250
1251  return Chain;
1252}
1253
1254//===----------------------------------------------------------------------===//
1255// TargetLowering Implementation
1256//===----------------------------------------------------------------------===//
1257
1258/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1259/// condition.
1260static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1261  switch (CC) {
1262  default: llvm_unreachable("Unknown integer condition code!");
1263  case ISD::SETEQ:  return SPCC::ICC_E;
1264  case ISD::SETNE:  return SPCC::ICC_NE;
1265  case ISD::SETLT:  return SPCC::ICC_L;
1266  case ISD::SETGT:  return SPCC::ICC_G;
1267  case ISD::SETLE:  return SPCC::ICC_LE;
1268  case ISD::SETGE:  return SPCC::ICC_GE;
1269  case ISD::SETULT: return SPCC::ICC_CS;
1270  case ISD::SETULE: return SPCC::ICC_LEU;
1271  case ISD::SETUGT: return SPCC::ICC_GU;
1272  case ISD::SETUGE: return SPCC::ICC_CC;
1273  }
1274}
1275
1276/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1277/// FCC condition.
1278static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1279  switch (CC) {
1280  default: llvm_unreachable("Unknown fp condition code!");
1281  case ISD::SETEQ:
1282  case ISD::SETOEQ: return SPCC::FCC_E;
1283  case ISD::SETNE:
1284  case ISD::SETUNE: return SPCC::FCC_NE;
1285  case ISD::SETLT:
1286  case ISD::SETOLT: return SPCC::FCC_L;
1287  case ISD::SETGT:
1288  case ISD::SETOGT: return SPCC::FCC_G;
1289  case ISD::SETLE:
1290  case ISD::SETOLE: return SPCC::FCC_LE;
1291  case ISD::SETGE:
1292  case ISD::SETOGE: return SPCC::FCC_GE;
1293  case ISD::SETULT: return SPCC::FCC_UL;
1294  case ISD::SETULE: return SPCC::FCC_ULE;
1295  case ISD::SETUGT: return SPCC::FCC_UG;
1296  case ISD::SETUGE: return SPCC::FCC_UGE;
1297  case ISD::SETUO:  return SPCC::FCC_U;
1298  case ISD::SETO:   return SPCC::FCC_O;
1299  case ISD::SETONE: return SPCC::FCC_LG;
1300  case ISD::SETUEQ: return SPCC::FCC_UE;
1301  }
1302}
1303
1304SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
1305  : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
1306  Subtarget = &TM.getSubtarget<SparcSubtarget>();
1307
1308  // Set up the register classes.
1309  addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1310  addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1311  addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1312  addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1313  if (Subtarget->is64Bit())
1314    addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1315
1316  // Turn FP extload into load/fextend
1317  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1318  setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
1319
1320  // Sparc doesn't have i1 sign extending load
1321  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1322
1323  // Turn FP truncstore into trunc + store.
1324  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1325  setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1326  setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1327
1328  // Custom legalize GlobalAddress nodes into LO/HI parts.
1329  setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1330  setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1331  setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1332  setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1333
1334  // Sparc doesn't have sext_inreg, replace them with shl/sra
1335  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1336  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1337  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1338
1339  // Sparc has no REM or DIVREM operations.
1340  setOperationAction(ISD::UREM, MVT::i32, Expand);
1341  setOperationAction(ISD::SREM, MVT::i32, Expand);
1342  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1343  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1344
1345  // ... nor does SparcV9.
1346  if (Subtarget->is64Bit()) {
1347    setOperationAction(ISD::UREM, MVT::i64, Expand);
1348    setOperationAction(ISD::SREM, MVT::i64, Expand);
1349    setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1350    setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1351  }
1352
1353  // Custom expand fp<->sint
1354  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1355  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1356
1357  // Custom Expand fp<->uint
1358  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1359  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1360
1361  setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1362  setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1363
1364  // Sparc has no select or setcc: expand to SELECT_CC.
1365  setOperationAction(ISD::SELECT, MVT::i32, Expand);
1366  setOperationAction(ISD::SELECT, MVT::f32, Expand);
1367  setOperationAction(ISD::SELECT, MVT::f64, Expand);
1368  setOperationAction(ISD::SELECT, MVT::f128, Expand);
1369
1370  setOperationAction(ISD::SETCC, MVT::i32, Expand);
1371  setOperationAction(ISD::SETCC, MVT::f32, Expand);
1372  setOperationAction(ISD::SETCC, MVT::f64, Expand);
1373  setOperationAction(ISD::SETCC, MVT::f128, Expand);
1374
1375  // Sparc doesn't have BRCOND either, it has BR_CC.
1376  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1377  setOperationAction(ISD::BRIND, MVT::Other, Expand);
1378  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1379  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1380  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1381  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1382  setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1383
1384  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1385  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1386  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1387  setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1388
1389  if (Subtarget->is64Bit()) {
1390    setOperationAction(ISD::ADDC, MVT::i64, Custom);
1391    setOperationAction(ISD::ADDE, MVT::i64, Custom);
1392    setOperationAction(ISD::SUBC, MVT::i64, Custom);
1393    setOperationAction(ISD::SUBE, MVT::i64, Custom);
1394    setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1395    setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1396    setOperationAction(ISD::SELECT, MVT::i64, Expand);
1397    setOperationAction(ISD::SETCC, MVT::i64, Expand);
1398    setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1399    setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1400
1401    setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1402    setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1403    setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1404    setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1405    setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1406    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1407  }
1408
1409  // FIXME: There are instructions available for ATOMIC_FENCE
1410  // on SparcV8 and later.
1411  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
1412
1413  if (!Subtarget->isV9()) {
1414    // SparcV8 does not have FNEGD and FABSD.
1415    setOperationAction(ISD::FNEG, MVT::f64, Custom);
1416    setOperationAction(ISD::FABS, MVT::f64, Custom);
1417  }
1418
1419  setOperationAction(ISD::FSIN , MVT::f128, Expand);
1420  setOperationAction(ISD::FCOS , MVT::f128, Expand);
1421  setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1422  setOperationAction(ISD::FREM , MVT::f128, Expand);
1423  setOperationAction(ISD::FMA  , MVT::f128, Expand);
1424  setOperationAction(ISD::FSIN , MVT::f64, Expand);
1425  setOperationAction(ISD::FCOS , MVT::f64, Expand);
1426  setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1427  setOperationAction(ISD::FREM , MVT::f64, Expand);
1428  setOperationAction(ISD::FMA  , MVT::f64, Expand);
1429  setOperationAction(ISD::FSIN , MVT::f32, Expand);
1430  setOperationAction(ISD::FCOS , MVT::f32, Expand);
1431  setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1432  setOperationAction(ISD::FREM , MVT::f32, Expand);
1433  setOperationAction(ISD::FMA  , MVT::f32, Expand);
1434  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1435  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1436  setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1437  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1438  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1439  setOperationAction(ISD::ROTL , MVT::i32, Expand);
1440  setOperationAction(ISD::ROTR , MVT::i32, Expand);
1441  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1442  setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1443  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1444  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1445  setOperationAction(ISD::FPOW , MVT::f128, Expand);
1446  setOperationAction(ISD::FPOW , MVT::f64, Expand);
1447  setOperationAction(ISD::FPOW , MVT::f32, Expand);
1448
1449  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1450  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1451  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1452
1453  // FIXME: Sparc provides these multiplies, but we don't have them yet.
1454  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1455  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1456
1457  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1458  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
1459  // VAARG needs to be lowered to not do unaligned accesses for doubles.
1460  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
1461
1462  // Use the default implementation.
1463  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
1464  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
1465  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
1466  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
1467  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
1468
1469  setExceptionPointerRegister(SP::I0);
1470  setExceptionSelectorRegister(SP::I1);
1471
1472  setStackPointerRegisterToSaveRestore(SP::O6);
1473
1474  if (Subtarget->isV9())
1475    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1476
1477  if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1478    setOperationAction(ISD::LOAD, MVT::f128, Legal);
1479    setOperationAction(ISD::STORE, MVT::f128, Legal);
1480  } else {
1481    setOperationAction(ISD::LOAD, MVT::f128, Custom);
1482    setOperationAction(ISD::STORE, MVT::f128, Custom);
1483  }
1484
1485  if (Subtarget->hasHardQuad()) {
1486    setOperationAction(ISD::FADD,  MVT::f128, Legal);
1487    setOperationAction(ISD::FSUB,  MVT::f128, Legal);
1488    setOperationAction(ISD::FMUL,  MVT::f128, Legal);
1489    setOperationAction(ISD::FDIV,  MVT::f128, Legal);
1490    setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1491    setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1492    setOperationAction(ISD::FP_ROUND,  MVT::f64, Legal);
1493    if (Subtarget->isV9()) {
1494      setOperationAction(ISD::FNEG, MVT::f128, Legal);
1495      setOperationAction(ISD::FABS, MVT::f128, Legal);
1496    } else {
1497      setOperationAction(ISD::FNEG, MVT::f128, Custom);
1498      setOperationAction(ISD::FABS, MVT::f128, Custom);
1499    }
1500  } else {
1501    // Custom legalize f128 operations.
1502
1503    setOperationAction(ISD::FADD,  MVT::f128, Custom);
1504    setOperationAction(ISD::FSUB,  MVT::f128, Custom);
1505    setOperationAction(ISD::FMUL,  MVT::f128, Custom);
1506    setOperationAction(ISD::FDIV,  MVT::f128, Custom);
1507    setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1508    setOperationAction(ISD::FNEG,  MVT::f128, Custom);
1509    setOperationAction(ISD::FABS,  MVT::f128, Custom);
1510
1511    setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1512    setOperationAction(ISD::FP_ROUND,  MVT::f64, Custom);
1513    setOperationAction(ISD::FP_ROUND,  MVT::f32, Custom);
1514
1515    // Setup Runtime library names.
1516    if (Subtarget->is64Bit()) {
1517      setLibcallName(RTLIB::ADD_F128,  "_Qp_add");
1518      setLibcallName(RTLIB::SUB_F128,  "_Qp_sub");
1519      setLibcallName(RTLIB::MUL_F128,  "_Qp_mul");
1520      setLibcallName(RTLIB::DIV_F128,  "_Qp_div");
1521      setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1522      setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1523      setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1524      setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1525      setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1526      setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1527      setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1528      setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1529      setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1530    } else {
1531      setLibcallName(RTLIB::ADD_F128,  "_Q_add");
1532      setLibcallName(RTLIB::SUB_F128,  "_Q_sub");
1533      setLibcallName(RTLIB::MUL_F128,  "_Q_mul");
1534      setLibcallName(RTLIB::DIV_F128,  "_Q_div");
1535      setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1536      setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1537      setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1538      setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1539      setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1540      setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1541      setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1542      setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1543      setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1544    }
1545  }
1546
1547  setMinFunctionAlignment(2);
1548
1549  computeRegisterProperties();
1550}
1551
1552const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1553  switch (Opcode) {
1554  default: return 0;
1555  case SPISD::CMPICC:     return "SPISD::CMPICC";
1556  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
1557  case SPISD::BRICC:      return "SPISD::BRICC";
1558  case SPISD::BRXCC:      return "SPISD::BRXCC";
1559  case SPISD::BRFCC:      return "SPISD::BRFCC";
1560  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1561  case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1562  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1563  case SPISD::Hi:         return "SPISD::Hi";
1564  case SPISD::Lo:         return "SPISD::Lo";
1565  case SPISD::FTOI:       return "SPISD::FTOI";
1566  case SPISD::ITOF:       return "SPISD::ITOF";
1567  case SPISD::CALL:       return "SPISD::CALL";
1568  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
1569  case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1570  case SPISD::FLUSHW:     return "SPISD::FLUSHW";
1571  case SPISD::TLS_ADD:    return "SPISD::TLS_ADD";
1572  case SPISD::TLS_LD:     return "SPISD::TLS_LD";
1573  case SPISD::TLS_CALL:   return "SPISD::TLS_CALL";
1574  }
1575}
1576
1577/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1578/// be zero. Op is expected to be a target specific node. Used by DAG
1579/// combiner.
1580void SparcTargetLowering::computeMaskedBitsForTargetNode
1581                                (const SDValue Op,
1582                                 APInt &KnownZero,
1583                                 APInt &KnownOne,
1584                                 const SelectionDAG &DAG,
1585                                 unsigned Depth) const {
1586  APInt KnownZero2, KnownOne2;
1587  KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1588
1589  switch (Op.getOpcode()) {
1590  default: break;
1591  case SPISD::SELECT_ICC:
1592  case SPISD::SELECT_XCC:
1593  case SPISD::SELECT_FCC:
1594    DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1595    DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1596    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1597    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1598
1599    // Only known if known in both the LHS and RHS.
1600    KnownOne &= KnownOne2;
1601    KnownZero &= KnownZero2;
1602    break;
1603  }
1604}
1605
1606// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
1607// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1608static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1609                             ISD::CondCode CC, unsigned &SPCC) {
1610  if (isa<ConstantSDNode>(RHS) &&
1611      cast<ConstantSDNode>(RHS)->isNullValue() &&
1612      CC == ISD::SETNE &&
1613      (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1614         LHS.getOpcode() == SPISD::SELECT_XCC) &&
1615        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1616       (LHS.getOpcode() == SPISD::SELECT_FCC &&
1617        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1618      isa<ConstantSDNode>(LHS.getOperand(0)) &&
1619      isa<ConstantSDNode>(LHS.getOperand(1)) &&
1620      cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1621      cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1622    SDValue CMPCC = LHS.getOperand(3);
1623    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1624    LHS = CMPCC.getOperand(0);
1625    RHS = CMPCC.getOperand(1);
1626  }
1627}
1628
1629// Convert to a target node and set target flags.
1630SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1631                                             SelectionDAG &DAG) const {
1632  if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1633    return DAG.getTargetGlobalAddress(GA->getGlobal(),
1634                                      SDLoc(GA),
1635                                      GA->getValueType(0),
1636                                      GA->getOffset(), TF);
1637
1638  if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1639    return DAG.getTargetConstantPool(CP->getConstVal(),
1640                                     CP->getValueType(0),
1641                                     CP->getAlignment(),
1642                                     CP->getOffset(), TF);
1643
1644  if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1645    return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1646                                     Op.getValueType(),
1647                                     0,
1648                                     TF);
1649
1650  if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1651    return DAG.getTargetExternalSymbol(ES->getSymbol(),
1652                                       ES->getValueType(0), TF);
1653
1654  llvm_unreachable("Unhandled address SDNode");
1655}
1656
1657// Split Op into high and low parts according to HiTF and LoTF.
1658// Return an ADD node combining the parts.
1659SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1660                                          unsigned HiTF, unsigned LoTF,
1661                                          SelectionDAG &DAG) const {
1662  SDLoc DL(Op);
1663  EVT VT = Op.getValueType();
1664  SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1665  SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1666  return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1667}
1668
1669// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1670// or ExternalSymbol SDNode.
1671SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1672  SDLoc DL(Op);
1673  EVT VT = getPointerTy();
1674
1675  // Handle PIC mode first.
1676  if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1677    // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1678    SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1679    SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1680    SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1681    // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1682    // function has calls.
1683    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1684    MFI->setHasCalls(true);
1685    return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1686                       MachinePointerInfo::getGOT(), false, false, false, 0);
1687  }
1688
1689  // This is one of the absolute code models.
1690  switch(getTargetMachine().getCodeModel()) {
1691  default:
1692    llvm_unreachable("Unsupported absolute code model");
1693  case CodeModel::JITDefault:
1694  case CodeModel::Small:
1695    // abs32.
1696    return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1697  case CodeModel::Medium: {
1698    // abs44.
1699    SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
1700    H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1701    SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
1702    L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1703    return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1704  }
1705  case CodeModel::Large: {
1706    // abs64.
1707    SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG);
1708    Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1709    SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1710    return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1711  }
1712  }
1713}
1714
1715SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1716                                                SelectionDAG &DAG) const {
1717  return makeAddress(Op, DAG);
1718}
1719
1720SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1721                                               SelectionDAG &DAG) const {
1722  return makeAddress(Op, DAG);
1723}
1724
1725SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1726                                               SelectionDAG &DAG) const {
1727  return makeAddress(Op, DAG);
1728}
1729
1730SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1731                                                   SelectionDAG &DAG) const {
1732
1733  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1734  SDLoc DL(GA);
1735  const GlobalValue *GV = GA->getGlobal();
1736  EVT PtrVT = getPointerTy();
1737
1738  TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1739
1740  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1741    unsigned HiTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_HI22
1742                     : SPII::MO_TLS_LDM_HI22);
1743    unsigned LoTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_LO10
1744                     : SPII::MO_TLS_LDM_LO10);
1745    unsigned addTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_ADD
1746                      : SPII::MO_TLS_LDM_ADD);
1747    unsigned callTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_CALL
1748                       : SPII::MO_TLS_LDM_CALL);
1749
1750    SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1751    SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1752    SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1753                               withTargetFlags(Op, addTF, DAG));
1754
1755    SDValue Chain = DAG.getEntryNode();
1756    SDValue InFlag;
1757
1758    Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
1759    Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1760    InFlag = Chain.getValue(1);
1761    SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1762    SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1763
1764    SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1765    SmallVector<SDValue, 4> Ops;
1766    Ops.push_back(Chain);
1767    Ops.push_back(Callee);
1768    Ops.push_back(Symbol);
1769    Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1770    const uint32_t *Mask = getTargetMachine()
1771      .getRegisterInfo()->getCallPreservedMask(CallingConv::C);
1772    assert(Mask && "Missing call preserved mask for calling convention");
1773    Ops.push_back(DAG.getRegisterMask(Mask));
1774    Ops.push_back(InFlag);
1775    Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, &Ops[0], Ops.size());
1776    InFlag = Chain.getValue(1);
1777    Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
1778                               DAG.getIntPtrConstant(0, true), InFlag, DL);
1779    InFlag = Chain.getValue(1);
1780    SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1781
1782    if (model != TLSModel::LocalDynamic)
1783      return Ret;
1784
1785    SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1786                             withTargetFlags(Op, SPII::MO_TLS_LDO_HIX22, DAG));
1787    SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1788                             withTargetFlags(Op, SPII::MO_TLS_LDO_LOX10, DAG));
1789    HiLo =  DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1790    return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1791                       withTargetFlags(Op, SPII::MO_TLS_LDO_ADD, DAG));
1792  }
1793
1794  if (model == TLSModel::InitialExec) {
1795    unsigned ldTF     = ((PtrVT == MVT::i64)? SPII::MO_TLS_IE_LDX
1796                         : SPII::MO_TLS_IE_LD);
1797
1798    SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1799
1800    // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1801    // function has calls.
1802    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1803    MFI->setHasCalls(true);
1804
1805    SDValue TGA = makeHiLoPair(Op,
1806                               SPII::MO_TLS_IE_HI22, SPII::MO_TLS_IE_LO10, DAG);
1807    SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1808    SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1809                                 DL, PtrVT, Ptr,
1810                                 withTargetFlags(Op, ldTF, DAG));
1811    return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1812                       DAG.getRegister(SP::G7, PtrVT), Offset,
1813                       withTargetFlags(Op, SPII::MO_TLS_IE_ADD, DAG));
1814  }
1815
1816  assert(model == TLSModel::LocalExec);
1817  SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1818                           withTargetFlags(Op, SPII::MO_TLS_LE_HIX22, DAG));
1819  SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1820                           withTargetFlags(Op, SPII::MO_TLS_LE_LOX10, DAG));
1821  SDValue Offset =  DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1822
1823  return DAG.getNode(ISD::ADD, DL, PtrVT,
1824                     DAG.getRegister(SP::G7, PtrVT), Offset);
1825}
1826
1827SDValue
1828SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1829                                          SDValue Arg, SDLoc DL,
1830                                          SelectionDAG &DAG) const {
1831  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1832  EVT ArgVT = Arg.getValueType();
1833  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1834
1835  ArgListEntry Entry;
1836  Entry.Node = Arg;
1837  Entry.Ty   = ArgTy;
1838
1839  if (ArgTy->isFP128Ty()) {
1840    // Create a stack object and pass the pointer to the library function.
1841    int FI = MFI->CreateStackObject(16, 8, false);
1842    SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
1843    Chain = DAG.getStore(Chain,
1844                         DL,
1845                         Entry.Node,
1846                         FIPtr,
1847                         MachinePointerInfo(),
1848                         false,
1849                         false,
1850                         8);
1851
1852    Entry.Node = FIPtr;
1853    Entry.Ty   = PointerType::getUnqual(ArgTy);
1854  }
1855  Args.push_back(Entry);
1856  return Chain;
1857}
1858
1859SDValue
1860SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
1861                                 const char *LibFuncName,
1862                                 unsigned numArgs) const {
1863
1864  ArgListTy Args;
1865
1866  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1867
1868  SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
1869  Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
1870  Type *RetTyABI = RetTy;
1871  SDValue Chain = DAG.getEntryNode();
1872  SDValue RetPtr;
1873
1874  if (RetTy->isFP128Ty()) {
1875    // Create a Stack Object to receive the return value of type f128.
1876    ArgListEntry Entry;
1877    int RetFI = MFI->CreateStackObject(16, 8, false);
1878    RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
1879    Entry.Node = RetPtr;
1880    Entry.Ty   = PointerType::getUnqual(RetTy);
1881    if (!Subtarget->is64Bit())
1882      Entry.isSRet = true;
1883    Entry.isReturned = false;
1884    Args.push_back(Entry);
1885    RetTyABI = Type::getVoidTy(*DAG.getContext());
1886  }
1887
1888  assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
1889  for (unsigned i = 0, e = numArgs; i != e; ++i) {
1890    Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
1891  }
1892  TargetLowering::
1893    CallLoweringInfo CLI(Chain,
1894                         RetTyABI,
1895                         false, false, false, false,
1896                         0, CallingConv::C,
1897                         false, false, true,
1898                         Callee, Args, DAG, SDLoc(Op));
1899  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1900
1901  // chain is in second result.
1902  if (RetTyABI == RetTy)
1903    return CallInfo.first;
1904
1905  assert (RetTy->isFP128Ty() && "Unexpected return type!");
1906
1907  Chain = CallInfo.second;
1908
1909  // Load RetPtr to get the return value.
1910  return DAG.getLoad(Op.getValueType(),
1911                     SDLoc(Op),
1912                     Chain,
1913                     RetPtr,
1914                     MachinePointerInfo(),
1915                     false, false, false, 8);
1916}
1917
1918SDValue
1919SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
1920                                      unsigned &SPCC,
1921                                      SDLoc DL,
1922                                      SelectionDAG &DAG) const {
1923
1924  const char *LibCall = 0;
1925  bool is64Bit = Subtarget->is64Bit();
1926  switch(SPCC) {
1927  default: llvm_unreachable("Unhandled conditional code!");
1928  case SPCC::FCC_E  : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
1929  case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
1930  case SPCC::FCC_L  : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
1931  case SPCC::FCC_G  : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
1932  case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
1933  case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
1934  case SPCC::FCC_UL :
1935  case SPCC::FCC_ULE:
1936  case SPCC::FCC_UG :
1937  case SPCC::FCC_UGE:
1938  case SPCC::FCC_U  :
1939  case SPCC::FCC_O  :
1940  case SPCC::FCC_LG :
1941  case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
1942  }
1943
1944  SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
1945  Type *RetTy = Type::getInt32Ty(*DAG.getContext());
1946  ArgListTy Args;
1947  SDValue Chain = DAG.getEntryNode();
1948  Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
1949  Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
1950
1951  TargetLowering::
1952    CallLoweringInfo CLI(Chain,
1953                         RetTy,
1954                         false, false, false, false,
1955                         0, CallingConv::C,
1956                         false, false, true,
1957                         Callee, Args, DAG, DL);
1958
1959  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1960
1961  // result is in first, and chain is in second result.
1962  SDValue Result =  CallInfo.first;
1963
1964  switch(SPCC) {
1965  default: {
1966    SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
1967    SPCC = SPCC::ICC_NE;
1968    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1969  }
1970  case SPCC::FCC_UL : {
1971    SDValue Mask   = DAG.getTargetConstant(1, Result.getValueType());
1972    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
1973    SDValue RHS    = DAG.getTargetConstant(0, Result.getValueType());
1974    SPCC = SPCC::ICC_NE;
1975    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1976  }
1977  case SPCC::FCC_ULE: {
1978    SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
1979    SPCC = SPCC::ICC_NE;
1980    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1981  }
1982  case SPCC::FCC_UG :  {
1983    SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
1984    SPCC = SPCC::ICC_G;
1985    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1986  }
1987  case SPCC::FCC_UGE: {
1988    SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
1989    SPCC = SPCC::ICC_NE;
1990    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1991  }
1992
1993  case SPCC::FCC_U  :  {
1994    SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
1995    SPCC = SPCC::ICC_E;
1996    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1997  }
1998  case SPCC::FCC_O  :  {
1999    SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2000    SPCC = SPCC::ICC_NE;
2001    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2002  }
2003  case SPCC::FCC_LG :  {
2004    SDValue Mask   = DAG.getTargetConstant(3, Result.getValueType());
2005    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2006    SDValue RHS    = DAG.getTargetConstant(0, Result.getValueType());
2007    SPCC = SPCC::ICC_NE;
2008    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2009  }
2010  case SPCC::FCC_UE : {
2011    SDValue Mask   = DAG.getTargetConstant(3, Result.getValueType());
2012    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2013    SDValue RHS    = DAG.getTargetConstant(0, Result.getValueType());
2014    SPCC = SPCC::ICC_E;
2015    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2016  }
2017  }
2018}
2019
2020static SDValue
2021LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2022                   const SparcTargetLowering &TLI) {
2023
2024  if (Op.getOperand(0).getValueType() == MVT::f64)
2025    return TLI.LowerF128Op(Op, DAG,
2026                           TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2027
2028  if (Op.getOperand(0).getValueType() == MVT::f32)
2029    return TLI.LowerF128Op(Op, DAG,
2030                           TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2031
2032  llvm_unreachable("fpextend with non-float operand!");
2033  return SDValue(0, 0);
2034}
2035
2036static SDValue
2037LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2038                  const SparcTargetLowering &TLI) {
2039  // FP_ROUND on f64 and f32 are legal.
2040  if (Op.getOperand(0).getValueType() != MVT::f128)
2041    return Op;
2042
2043  if (Op.getValueType() == MVT::f64)
2044    return TLI.LowerF128Op(Op, DAG,
2045                           TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2046  if (Op.getValueType() == MVT::f32)
2047    return TLI.LowerF128Op(Op, DAG,
2048                           TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2049
2050  llvm_unreachable("fpround to non-float!");
2051  return SDValue(0, 0);
2052}
2053
2054static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2055                               const SparcTargetLowering &TLI,
2056                               bool hasHardQuad) {
2057  SDLoc dl(Op);
2058  // Convert the fp value to integer in an FP register.
2059  assert(Op.getValueType() == MVT::i32);
2060
2061  if (Op.getOperand(0).getValueType() == MVT::f128 && !hasHardQuad)
2062    return TLI.LowerF128Op(Op, DAG,
2063                       TLI.getLibcallName(RTLIB::FPTOSINT_F128_I32), 1);
2064
2065  Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2066  return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2067}
2068
2069static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2070                               const SparcTargetLowering &TLI,
2071                               bool hasHardQuad) {
2072  SDLoc dl(Op);
2073  assert(Op.getOperand(0).getValueType() == MVT::i32);
2074  SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2075  // Convert the int value to FP in an FP register.
2076  if (Op.getValueType() == MVT::f128 && !hasHardQuad)
2077    return TLI.LowerF128Op(Op, DAG,
2078                           TLI.getLibcallName(RTLIB::SINTTOFP_I32_F128), 1);
2079  return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
2080}
2081
2082static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2083                               const SparcTargetLowering &TLI,
2084                               bool hasHardQuad) {
2085  // Expand if it does not involve f128 or the target has support for
2086  // quad floating point instructions.
2087  if (Op.getOperand(0).getValueType() != MVT::f128 || hasHardQuad)
2088    return SDValue(0, 0);
2089
2090  SDLoc dl(Op);
2091  assert(Op.getValueType() == MVT::i32);
2092
2093  return TLI.LowerF128Op(Op, DAG,
2094                         TLI.getLibcallName(RTLIB::FPTOUINT_F128_I32), 1);
2095}
2096
2097
2098static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2099                               const SparcTargetLowering &TLI,
2100                               bool hasHardQuad) {
2101  // Expand if it does not involve f128 or the target has support for
2102  // quad floating point instructions.
2103  if (Op.getValueType() != MVT::f128 || hasHardQuad)
2104    return SDValue(0, 0);
2105
2106  SDLoc dl(Op);
2107  assert(Op.getOperand(0).getValueType() == MVT::i32);
2108
2109  return TLI.LowerF128Op(Op, DAG,
2110                         TLI.getLibcallName(RTLIB::UINTTOFP_I32_F128), 1);
2111}
2112
2113static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2114                          const SparcTargetLowering &TLI,
2115                          bool hasHardQuad) {
2116  SDValue Chain = Op.getOperand(0);
2117  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2118  SDValue LHS = Op.getOperand(2);
2119  SDValue RHS = Op.getOperand(3);
2120  SDValue Dest = Op.getOperand(4);
2121  SDLoc dl(Op);
2122  unsigned Opc, SPCC = ~0U;
2123
2124  // If this is a br_cc of a "setcc", and if the setcc got lowered into
2125  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2126  LookThroughSetCC(LHS, RHS, CC, SPCC);
2127
2128  // Get the condition flag.
2129  SDValue CompareFlag;
2130  if (LHS.getValueType().isInteger()) {
2131    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2132    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2133    // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2134    Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2135  } else {
2136    if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2137      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2138      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2139      Opc = SPISD::BRICC;
2140    } else {
2141      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2142      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2143      Opc = SPISD::BRFCC;
2144    }
2145  }
2146  return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2147                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2148}
2149
2150static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2151                              const SparcTargetLowering &TLI,
2152                              bool hasHardQuad) {
2153  SDValue LHS = Op.getOperand(0);
2154  SDValue RHS = Op.getOperand(1);
2155  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2156  SDValue TrueVal = Op.getOperand(2);
2157  SDValue FalseVal = Op.getOperand(3);
2158  SDLoc dl(Op);
2159  unsigned Opc, SPCC = ~0U;
2160
2161  // If this is a select_cc of a "setcc", and if the setcc got lowered into
2162  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2163  LookThroughSetCC(LHS, RHS, CC, SPCC);
2164
2165  SDValue CompareFlag;
2166  if (LHS.getValueType().isInteger()) {
2167    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2168    Opc = LHS.getValueType() == MVT::i32 ?
2169          SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2170    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2171  } else {
2172    if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2173      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2174      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2175      Opc = SPISD::SELECT_ICC;
2176    } else {
2177      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2178      Opc = SPISD::SELECT_FCC;
2179      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2180    }
2181  }
2182  return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2183                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2184}
2185
2186static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2187                            const SparcTargetLowering &TLI) {
2188  MachineFunction &MF = DAG.getMachineFunction();
2189  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2190
2191  // Need frame address to find the address of VarArgsFrameIndex.
2192  MF.getFrameInfo()->setFrameAddressIsTaken(true);
2193
2194  // vastart just stores the address of the VarArgsFrameIndex slot into the
2195  // memory location argument.
2196  SDLoc DL(Op);
2197  SDValue Offset =
2198    DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
2199                DAG.getRegister(SP::I6, TLI.getPointerTy()),
2200                DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
2201  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2202  return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2203                      MachinePointerInfo(SV), false, false, 0);
2204}
2205
2206static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2207  SDNode *Node = Op.getNode();
2208  EVT VT = Node->getValueType(0);
2209  SDValue InChain = Node->getOperand(0);
2210  SDValue VAListPtr = Node->getOperand(1);
2211  EVT PtrVT = VAListPtr.getValueType();
2212  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2213  SDLoc DL(Node);
2214  SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2215                               MachinePointerInfo(SV), false, false, false, 0);
2216  // Increment the pointer, VAList, to the next vaarg.
2217  SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2218                                DAG.getIntPtrConstant(VT.getSizeInBits()/8));
2219  // Store the incremented VAList to the legalized pointer.
2220  InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2221                         VAListPtr, MachinePointerInfo(SV), false, false, 0);
2222  // Load the actual argument out of the pointer VAList.
2223  // We can't count on greater alignment than the word size.
2224  return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2225                     false, false, false,
2226                     std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2227}
2228
2229static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
2230  SDValue Chain = Op.getOperand(0);  // Legalize the chain.
2231  SDValue Size  = Op.getOperand(1);  // Legalize the size.
2232  SDLoc dl(Op);
2233
2234  unsigned SPReg = SP::O6;
2235  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
2236  SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
2237  Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP);    // Output chain
2238
2239  // The resultant pointer is actually 16 words from the bottom of the stack,
2240  // to provide a register spill area.
2241  SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
2242                                 DAG.getConstant(96, MVT::i32));
2243  SDValue Ops[2] = { NewVal, Chain };
2244  return DAG.getMergeValues(Ops, 2, dl);
2245}
2246
2247
2248static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2249  SDLoc dl(Op);
2250  SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2251                              dl, MVT::Other, DAG.getEntryNode());
2252  return Chain;
2253}
2254
2255static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
2256  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2257  MFI->setFrameAddressIsTaken(true);
2258
2259  EVT VT = Op.getValueType();
2260  SDLoc dl(Op);
2261  unsigned FrameReg = SP::I6;
2262
2263  uint64_t depth = Op.getConstantOperandVal(0);
2264
2265  SDValue FrameAddr;
2266  if (depth == 0)
2267    FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2268  else {
2269    // flush first to make sure the windowed registers' values are in stack
2270    SDValue Chain = getFLUSHW(Op, DAG);
2271    FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2272
2273    for (uint64_t i = 0; i != depth; ++i) {
2274      SDValue Ptr = DAG.getNode(ISD::ADD,
2275                                dl, MVT::i32,
2276                                FrameAddr, DAG.getIntPtrConstant(56));
2277      FrameAddr = DAG.getLoad(MVT::i32, dl,
2278                              Chain,
2279                              Ptr,
2280                              MachinePointerInfo(), false, false, false, 0);
2281    }
2282  }
2283  return FrameAddr;
2284}
2285
2286static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2287                               const SparcTargetLowering &TLI) {
2288  MachineFunction &MF = DAG.getMachineFunction();
2289  MachineFrameInfo *MFI = MF.getFrameInfo();
2290  MFI->setReturnAddressIsTaken(true);
2291
2292  EVT VT = Op.getValueType();
2293  SDLoc dl(Op);
2294  uint64_t depth = Op.getConstantOperandVal(0);
2295
2296  SDValue RetAddr;
2297  if (depth == 0) {
2298    unsigned RetReg = MF.addLiveIn(SP::I7,
2299                                   TLI.getRegClassFor(TLI.getPointerTy()));
2300    RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2301  } else {
2302    // Need frame address to find return address of the caller.
2303    MFI->setFrameAddressIsTaken(true);
2304
2305    // flush first to make sure the windowed registers' values are in stack
2306    SDValue Chain = getFLUSHW(Op, DAG);
2307    RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
2308
2309    for (uint64_t i = 0; i != depth; ++i) {
2310      SDValue Ptr = DAG.getNode(ISD::ADD,
2311                                dl, MVT::i32,
2312                                RetAddr,
2313                                DAG.getIntPtrConstant((i == depth-1)?60:56));
2314      RetAddr = DAG.getLoad(MVT::i32, dl,
2315                            Chain,
2316                            Ptr,
2317                            MachinePointerInfo(), false, false, false, 0);
2318    }
2319  }
2320  return RetAddr;
2321}
2322
2323static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2324{
2325  SDLoc dl(Op);
2326
2327  assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2328  assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2329
2330  // Lower fneg/fabs on f64 to fneg/fabs on f32.
2331  // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2332  // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2333
2334  SDValue SrcReg64 = Op.getOperand(0);
2335  SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2336                                            SrcReg64);
2337  SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2338                                            SrcReg64);
2339
2340  Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2341
2342  SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2343                                                dl, MVT::f64), 0);
2344  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2345                                       DstReg64, Hi32);
2346  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2347                                       DstReg64, Lo32);
2348  return DstReg64;
2349}
2350
2351// Lower a f128 load into two f64 loads.
2352static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2353{
2354  SDLoc dl(Op);
2355  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2356  assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2357         && "Unexpected node type");
2358
2359  unsigned alignment = LdNode->getAlignment();
2360  if (alignment > 8)
2361    alignment = 8;
2362
2363  SDValue Hi64 = DAG.getLoad(MVT::f64,
2364                             dl,
2365                             LdNode->getChain(),
2366                             LdNode->getBasePtr(),
2367                             LdNode->getPointerInfo(),
2368                             false, false, false, alignment);
2369  EVT addrVT = LdNode->getBasePtr().getValueType();
2370  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2371                              LdNode->getBasePtr(),
2372                              DAG.getConstant(8, addrVT));
2373  SDValue Lo64 = DAG.getLoad(MVT::f64,
2374                             dl,
2375                             LdNode->getChain(),
2376                             LoPtr,
2377                             LdNode->getPointerInfo(),
2378                             false, false, false, alignment);
2379
2380  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2381  SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2382
2383  SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2384                                       dl, MVT::f128);
2385  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2386                               MVT::f128,
2387                               SDValue(InFP128, 0),
2388                               Hi64,
2389                               SubRegEven);
2390  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2391                               MVT::f128,
2392                               SDValue(InFP128, 0),
2393                               Lo64,
2394                               SubRegOdd);
2395  SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2396                           SDValue(Lo64.getNode(), 1) };
2397  SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2398                                 &OutChains[0], 2);
2399  SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2400  return DAG.getMergeValues(Ops, 2, dl);
2401}
2402
2403// Lower a f128 store into two f64 stores.
2404static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2405  SDLoc dl(Op);
2406  StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2407  assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2408         && "Unexpected node type");
2409  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2410  SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2411
2412  SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2413                                    dl,
2414                                    MVT::f64,
2415                                    StNode->getValue(),
2416                                    SubRegEven);
2417  SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2418                                    dl,
2419                                    MVT::f64,
2420                                    StNode->getValue(),
2421                                    SubRegOdd);
2422
2423  unsigned alignment = StNode->getAlignment();
2424  if (alignment > 8)
2425    alignment = 8;
2426
2427  SDValue OutChains[2];
2428  OutChains[0] = DAG.getStore(StNode->getChain(),
2429                              dl,
2430                              SDValue(Hi64, 0),
2431                              StNode->getBasePtr(),
2432                              MachinePointerInfo(),
2433                              false, false, alignment);
2434  EVT addrVT = StNode->getBasePtr().getValueType();
2435  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2436                              StNode->getBasePtr(),
2437                              DAG.getConstant(8, addrVT));
2438  OutChains[1] = DAG.getStore(StNode->getChain(),
2439                             dl,
2440                             SDValue(Lo64, 0),
2441                             LoPtr,
2442                             MachinePointerInfo(),
2443                             false, false, alignment);
2444  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2445                     &OutChains[0], 2);
2446}
2447
2448static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
2449                         const SparcTargetLowering &TLI,
2450                         bool is64Bit) {
2451  if (Op.getValueType() == MVT::f64)
2452    return LowerF64Op(Op, DAG, ISD::FNEG);
2453  if (Op.getValueType() == MVT::f128)
2454    return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
2455  return Op;
2456}
2457
2458static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2459  if (Op.getValueType() == MVT::f64)
2460    return LowerF64Op(Op, DAG, ISD::FABS);
2461  if (Op.getValueType() != MVT::f128)
2462    return Op;
2463
2464  // Lower fabs on f128 to fabs on f64
2465  // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
2466
2467  SDLoc dl(Op);
2468  SDValue SrcReg128 = Op.getOperand(0);
2469  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2470                                            SrcReg128);
2471  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2472                                            SrcReg128);
2473  if (isV9)
2474    Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2475  else
2476    Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS);
2477
2478  SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2479                                                 dl, MVT::f128), 0);
2480  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2481                                        DstReg128, Hi64);
2482  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2483                                        DstReg128, Lo64);
2484  return DstReg128;
2485}
2486
2487static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2488
2489  if (Op.getValueType() != MVT::i64)
2490    return Op;
2491
2492  SDLoc dl(Op);
2493  SDValue Src1 = Op.getOperand(0);
2494  SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2495  SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2496                               DAG.getConstant(32, MVT::i64));
2497  Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2498
2499  SDValue Src2 = Op.getOperand(1);
2500  SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2501  SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2502                               DAG.getConstant(32, MVT::i64));
2503  Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2504
2505
2506  bool hasChain = false;
2507  unsigned hiOpc = Op.getOpcode();
2508  switch (Op.getOpcode()) {
2509  default: llvm_unreachable("Invalid opcode");
2510  case ISD::ADDC: hiOpc = ISD::ADDE; break;
2511  case ISD::ADDE: hasChain = true; break;
2512  case ISD::SUBC: hiOpc = ISD::SUBE; break;
2513  case ISD::SUBE: hasChain = true; break;
2514  }
2515  SDValue Lo;
2516  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2517  if (hasChain) {
2518    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2519                     Op.getOperand(2));
2520  } else {
2521    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2522  }
2523  SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2524  SDValue Carry = Hi.getValue(1);
2525
2526  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2527  Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2528  Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2529                   DAG.getConstant(32, MVT::i64));
2530
2531  SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2532  SDValue Ops[2] = { Dst, Carry };
2533  return DAG.getMergeValues(Ops, 2, dl);
2534}
2535
2536SDValue SparcTargetLowering::
2537LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2538
2539  bool hasHardQuad = Subtarget->hasHardQuad();
2540  bool is64Bit     = Subtarget->is64Bit();
2541  bool isV9        = Subtarget->isV9();
2542
2543  switch (Op.getOpcode()) {
2544  default: llvm_unreachable("Should not custom lower this!");
2545
2546  case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG, *this);
2547  case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
2548  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
2549  case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
2550  case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
2551  case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
2552  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG, *this,
2553                                                       hasHardQuad);
2554  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG, *this,
2555                                                       hasHardQuad);
2556  case ISD::FP_TO_UINT:         return LowerFP_TO_UINT(Op, DAG, *this,
2557                                                       hasHardQuad);
2558  case ISD::UINT_TO_FP:         return LowerUINT_TO_FP(Op, DAG, *this,
2559                                                       hasHardQuad);
2560  case ISD::BR_CC:              return LowerBR_CC(Op, DAG, *this,
2561                                                  hasHardQuad);
2562  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG, *this,
2563                                                      hasHardQuad);
2564  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
2565  case ISD::VAARG:              return LowerVAARG(Op, DAG);
2566  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2567
2568  case ISD::LOAD:               return LowerF128Load(Op, DAG);
2569  case ISD::STORE:              return LowerF128Store(Op, DAG);
2570  case ISD::FADD:               return LowerF128Op(Op, DAG,
2571                                       getLibcallName(RTLIB::ADD_F128), 2);
2572  case ISD::FSUB:               return LowerF128Op(Op, DAG,
2573                                       getLibcallName(RTLIB::SUB_F128), 2);
2574  case ISD::FMUL:               return LowerF128Op(Op, DAG,
2575                                       getLibcallName(RTLIB::MUL_F128), 2);
2576  case ISD::FDIV:               return LowerF128Op(Op, DAG,
2577                                       getLibcallName(RTLIB::DIV_F128), 2);
2578  case ISD::FSQRT:              return LowerF128Op(Op, DAG,
2579                                       getLibcallName(RTLIB::SQRT_F128),1);
2580  case ISD::FNEG:               return LowerFNEG(Op, DAG, *this, is64Bit);
2581  case ISD::FABS:               return LowerFABS(Op, DAG, isV9);
2582  case ISD::FP_EXTEND:          return LowerF128_FPEXTEND(Op, DAG, *this);
2583  case ISD::FP_ROUND:           return LowerF128_FPROUND(Op, DAG, *this);
2584  case ISD::ADDC:
2585  case ISD::ADDE:
2586  case ISD::SUBC:
2587  case ISD::SUBE:               return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2588  }
2589}
2590
2591MachineBasicBlock *
2592SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2593                                                 MachineBasicBlock *BB) const {
2594  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
2595  unsigned BROpcode;
2596  unsigned CC;
2597  DebugLoc dl = MI->getDebugLoc();
2598  // Figure out the conditional branch opcode to use for this select_cc.
2599  switch (MI->getOpcode()) {
2600  default: llvm_unreachable("Unknown SELECT_CC!");
2601  case SP::SELECT_CC_Int_ICC:
2602  case SP::SELECT_CC_FP_ICC:
2603  case SP::SELECT_CC_DFP_ICC:
2604  case SP::SELECT_CC_QFP_ICC:
2605    BROpcode = SP::BCOND;
2606    break;
2607  case SP::SELECT_CC_Int_FCC:
2608  case SP::SELECT_CC_FP_FCC:
2609  case SP::SELECT_CC_DFP_FCC:
2610  case SP::SELECT_CC_QFP_FCC:
2611    BROpcode = SP::FBCOND;
2612    break;
2613  }
2614
2615  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2616
2617  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2618  // control-flow pattern.  The incoming instruction knows the destination vreg
2619  // to set, the condition code register to branch on, the true/false values to
2620  // select between, and a branch opcode to use.
2621  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2622  MachineFunction::iterator It = BB;
2623  ++It;
2624
2625  //  thisMBB:
2626  //  ...
2627  //   TrueVal = ...
2628  //   [f]bCC copy1MBB
2629  //   fallthrough --> copy0MBB
2630  MachineBasicBlock *thisMBB = BB;
2631  MachineFunction *F = BB->getParent();
2632  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2633  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2634  F->insert(It, copy0MBB);
2635  F->insert(It, sinkMBB);
2636
2637  // Transfer the remainder of BB and its successor edges to sinkMBB.
2638  sinkMBB->splice(sinkMBB->begin(), BB,
2639                  llvm::next(MachineBasicBlock::iterator(MI)),
2640                  BB->end());
2641  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2642
2643  // Add the true and fallthrough blocks as its successors.
2644  BB->addSuccessor(copy0MBB);
2645  BB->addSuccessor(sinkMBB);
2646
2647  BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2648
2649  //  copy0MBB:
2650  //   %FalseValue = ...
2651  //   # fallthrough to sinkMBB
2652  BB = copy0MBB;
2653
2654  // Update machine-CFG edges
2655  BB->addSuccessor(sinkMBB);
2656
2657  //  sinkMBB:
2658  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2659  //  ...
2660  BB = sinkMBB;
2661  BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2662    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2663    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2664
2665  MI->eraseFromParent();   // The pseudo instruction is gone now.
2666  return BB;
2667}
2668
2669//===----------------------------------------------------------------------===//
2670//                         Sparc Inline Assembly Support
2671//===----------------------------------------------------------------------===//
2672
2673/// getConstraintType - Given a constraint letter, return the type of
2674/// constraint it is for this target.
2675SparcTargetLowering::ConstraintType
2676SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
2677  if (Constraint.size() == 1) {
2678    switch (Constraint[0]) {
2679    default:  break;
2680    case 'r': return C_RegisterClass;
2681    }
2682  }
2683
2684  return TargetLowering::getConstraintType(Constraint);
2685}
2686
2687std::pair<unsigned, const TargetRegisterClass*>
2688SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2689                                                  MVT VT) const {
2690  if (Constraint.size() == 1) {
2691    switch (Constraint[0]) {
2692    case 'r':
2693      return std::make_pair(0U, &SP::IntRegsRegClass);
2694    }
2695  }
2696
2697  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2698}
2699
2700bool
2701SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2702  // The Sparc target isn't yet aware of offsets.
2703  return false;
2704}
2705