SparcISelLowering.cpp revision 707e0184233f27e0e9f9aee0309f2daab8cfe7f8
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "SparcTargetMachine.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24using namespace llvm;
25
26
27//===----------------------------------------------------------------------===//
28// Calling Convention Implementation
29//===----------------------------------------------------------------------===//
30
31#include "SparcGenCallingConv.inc"
32
33static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
34  // CCValAssign - represent the assignment of the return value to locations.
35  SmallVector<CCValAssign, 16> RVLocs;
36  unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
37  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
38
39  // CCState - Info about the registers and stack slot.
40  CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
41
42  // Analize return values of ISD::RET
43  CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32);
44
45  // If this is the first return lowered for this function, add the regs to the
46  // liveout set for the function.
47  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
48    for (unsigned i = 0; i != RVLocs.size(); ++i)
49      if (RVLocs[i].isRegLoc())
50        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
51  }
52
53  SDOperand Chain = Op.getOperand(0);
54  SDOperand Flag;
55
56  // Copy the result values into the output registers.
57  for (unsigned i = 0; i != RVLocs.size(); ++i) {
58    CCValAssign &VA = RVLocs[i];
59    assert(VA.isRegLoc() && "Can only return in registers!");
60
61    // ISD::RET => ret chain, (regnum1,val1), ...
62    // So i*2+1 index only the regnums.
63    Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
64
65    // Guarantee that all emitted copies are stuck together with flags.
66    Flag = Chain.getValue(1);
67  }
68
69  if (Flag.Val)
70    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
71  return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
72}
73
74/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
75/// either one or two GPRs, including FP values.  TODO: we should pass FP values
76/// in FP registers for fastcc functions.
77std::vector<SDOperand>
78SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
79  MachineFunction &MF = DAG.getMachineFunction();
80  MachineRegisterInfo &RegInfo = MF.getRegInfo();
81  std::vector<SDOperand> ArgValues;
82
83  static const unsigned ArgRegs[] = {
84    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
85  };
86
87  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
88  unsigned ArgOffset = 68;
89
90  SDOperand Root = DAG.getRoot();
91  std::vector<SDOperand> OutChains;
92
93  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
94    MVT::ValueType ObjectVT = getValueType(I->getType());
95
96    switch (ObjectVT) {
97    default: assert(0 && "Unhandled argument type!");
98    case MVT::i1:
99    case MVT::i8:
100    case MVT::i16:
101    case MVT::i32:
102      if (I->use_empty()) {                // Argument is dead.
103        if (CurArgReg < ArgRegEnd) ++CurArgReg;
104        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
105      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
106        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
107        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
108        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
109        if (ObjectVT != MVT::i32) {
110          unsigned AssertOp = ISD::AssertSext;
111          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
112                            DAG.getValueType(ObjectVT));
113          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
114        }
115        ArgValues.push_back(Arg);
116      } else {
117        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
118        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
119        SDOperand Load;
120        if (ObjectVT == MVT::i32) {
121          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
122        } else {
123          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
124
125          // Sparc is big endian, so add an offset based on the ObjectVT.
126          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
127          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
128                              DAG.getConstant(Offset, MVT::i32));
129          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
130                                NULL, 0, ObjectVT);
131          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
132        }
133        ArgValues.push_back(Load);
134      }
135
136      ArgOffset += 4;
137      break;
138    case MVT::f32:
139      if (I->use_empty()) {                // Argument is dead.
140        if (CurArgReg < ArgRegEnd) ++CurArgReg;
141        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
142      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
143        // FP value is passed in an integer register.
144        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
145        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
146        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
147
148        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
149        ArgValues.push_back(Arg);
150      } else {
151        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
152        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
153        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
154        ArgValues.push_back(Load);
155      }
156      ArgOffset += 4;
157      break;
158
159    case MVT::i64:
160    case MVT::f64:
161      if (I->use_empty()) {                // Argument is dead.
162        if (CurArgReg < ArgRegEnd) ++CurArgReg;
163        if (CurArgReg < ArgRegEnd) ++CurArgReg;
164        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
165      } else {
166        SDOperand HiVal;
167        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
168          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
169          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
170          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
171        } else {
172          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
173          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
174          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
175        }
176
177        SDOperand LoVal;
178        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
179          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
180          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
181          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
182        } else {
183          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
184          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
185          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
186        }
187
188        // Compose the two halves together into an i64 unit.
189        SDOperand WholeValue =
190          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
191
192        // If we want a double, do a bit convert.
193        if (ObjectVT == MVT::f64)
194          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
195
196        ArgValues.push_back(WholeValue);
197      }
198      ArgOffset += 8;
199      break;
200    }
201  }
202
203  // Store remaining ArgRegs to the stack if this is a varargs function.
204  if (F.isVarArg()) {
205    // Remember the vararg offset for the va_start implementation.
206    VarArgsFrameOffset = ArgOffset;
207
208    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
209      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
210      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
211      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
212
213      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
214      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
215
216      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
217      ArgOffset += 4;
218    }
219  }
220
221  if (!OutChains.empty())
222    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
223                            &OutChains[0], OutChains.size()));
224
225  return ArgValues;
226}
227
228static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
229  unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
230  SDOperand Chain = Op.getOperand(0);
231  SDOperand Callee = Op.getOperand(4);
232  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
233
234#if 0
235  // Analyze operands of the call, assigning locations to each operand.
236  SmallVector<CCValAssign, 16> ArgLocs;
237  CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
238  CCInfo.AnalyzeCallOperands(Op.Val, CC_Sparc32);
239
240  // Get the size of the outgoing arguments stack space requirement.
241  unsigned ArgsSize = CCInfo.getNextStackOffset();
242  // FIXME: We can't use this until f64 is known to take two GPRs.
243#else
244  (void)CC_Sparc32;
245
246  // Count the size of the outgoing arguments.
247  unsigned ArgsSize = 0;
248  for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
249    switch (Op.getOperand(i).getValueType()) {
250      default: assert(0 && "Unknown value type!");
251      case MVT::i1:
252      case MVT::i8:
253      case MVT::i16:
254      case MVT::i32:
255      case MVT::f32:
256        ArgsSize += 4;
257        break;
258      case MVT::i64:
259      case MVT::f64:
260        ArgsSize += 8;
261        break;
262    }
263  }
264  if (ArgsSize > 4*6)
265    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
266  else
267    ArgsSize = 0;
268#endif
269
270  // Keep stack frames 8-byte aligned.
271  ArgsSize = (ArgsSize+7) & ~7;
272
273  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize));
274
275  SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
276  SmallVector<SDOperand, 8> MemOpChains;
277
278#if 0
279  // Walk the register/memloc assignments, inserting copies/loads.
280  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
281    CCValAssign &VA = ArgLocs[i];
282
283    // Arguments start after the 5 first operands of ISD::CALL
284    SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
285
286    // Promote the value if needed.
287    switch (VA.getLocInfo()) {
288    default: assert(0 && "Unknown loc info!");
289    case CCValAssign::Full: break;
290    case CCValAssign::SExt:
291      Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
292      break;
293    case CCValAssign::ZExt:
294      Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
295      break;
296    case CCValAssign::AExt:
297      Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
298      break;
299    }
300
301    // Arguments that can be passed on register must be kept at
302    // RegsToPass vector
303    if (VA.isRegLoc()) {
304      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
305      continue;
306    }
307
308    assert(VA.isMemLoc());
309
310    // Create a store off the stack pointer for this argument.
311    SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32);
312    // FIXME: VERIFY THAT 68 IS RIGHT.
313    SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
314    PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
315    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
316  }
317
318#else
319  static const unsigned ArgRegs[] = {
320    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
321  };
322  unsigned ArgOffset = 68;
323
324  for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
325    SDOperand Val = Op.getOperand(i);
326    MVT::ValueType ObjectVT = Val.getValueType();
327    SDOperand ValToStore(0, 0);
328    unsigned ObjSize;
329    switch (ObjectVT) {
330    default: assert(0 && "Unhandled argument type!");
331    case MVT::i32:
332      ObjSize = 4;
333
334      if (RegsToPass.size() >= 6) {
335        ValToStore = Val;
336      } else {
337        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
338      }
339      break;
340    case MVT::f32:
341      ObjSize = 4;
342      if (RegsToPass.size() >= 6) {
343        ValToStore = Val;
344      } else {
345        // Convert this to a FP value in an int reg.
346        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
347        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
348      }
349      break;
350    case MVT::f64:
351      ObjSize = 8;
352      // Otherwise, convert this to a FP value in int regs.
353      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
354      // FALL THROUGH
355    case MVT::i64:
356      ObjSize = 8;
357      if (RegsToPass.size() >= 6) {
358        ValToStore = Val;    // Whole thing is passed in memory.
359        break;
360      }
361
362      // Split the value into top and bottom part.  Top part goes in a reg.
363      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
364                                 DAG.getConstant(1, MVT::i32));
365      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
366                                 DAG.getConstant(0, MVT::i32));
367      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
368
369      if (RegsToPass.size() >= 6) {
370        ValToStore = Lo;
371        ArgOffset += 4;
372        ObjSize = 4;
373      } else {
374        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
375      }
376      break;
377    }
378
379    if (ValToStore.Val) {
380      SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32);
381      SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
382      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
383      MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
384    }
385    ArgOffset += ObjSize;
386  }
387#endif
388
389  // Emit all stores, make sure the occur before any copies into physregs.
390  if (!MemOpChains.empty())
391    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
392                        &MemOpChains[0], MemOpChains.size());
393
394  // Build a sequence of copy-to-reg nodes chained together with token
395  // chain and flag operands which copy the outgoing args into registers.
396  // The InFlag in necessary since all emited instructions must be
397  // stuck together.
398  SDOperand InFlag;
399  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
400    unsigned Reg = RegsToPass[i].first;
401    // Remap I0->I7 -> O0->O7.
402    if (Reg >= SP::I0 && Reg <= SP::I7)
403      Reg = Reg-SP::I0+SP::O0;
404
405    Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag);
406    InFlag = Chain.getValue(1);
407  }
408
409  // If the callee is a GlobalAddress node (quite common, every direct call is)
410  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
411  // Likewise ExternalSymbol -> TargetExternalSymbol.
412  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
413    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
414  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
415    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
416
417  std::vector<MVT::ValueType> NodeTys;
418  NodeTys.push_back(MVT::Other);   // Returns a chain
419  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
420  SDOperand Ops[] = { Chain, Callee, InFlag };
421  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
422  InFlag = Chain.getValue(1);
423
424  Chain = DAG.getCALLSEQ_END(Chain,
425                             DAG.getConstant(ArgsSize, MVT::i32),
426                             DAG.getConstant(0, MVT::i32), InFlag);
427  InFlag = Chain.getValue(1);
428
429  // Assign locations to each value returned by this call.
430  SmallVector<CCValAssign, 16> RVLocs;
431  CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
432
433  RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
434  SmallVector<SDOperand, 8> ResultVals;
435
436  // Copy all of the result registers out of their specified physreg.
437  for (unsigned i = 0; i != RVLocs.size(); ++i) {
438    unsigned Reg = RVLocs[i].getLocReg();
439
440    // Remap I0->I7 -> O0->O7.
441    if (Reg >= SP::I0 && Reg <= SP::I7)
442      Reg = Reg-SP::I0+SP::O0;
443
444    Chain = DAG.getCopyFromReg(Chain, Reg,
445                               RVLocs[i].getValVT(), InFlag).getValue(1);
446    InFlag = Chain.getValue(2);
447    ResultVals.push_back(Chain.getValue(0));
448  }
449
450  ResultVals.push_back(Chain);
451
452  // Merge everything together with a MERGE_VALUES node.
453  return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
454                     &ResultVals[0], ResultVals.size());
455}
456
457
458
459//===----------------------------------------------------------------------===//
460// TargetLowering Implementation
461//===----------------------------------------------------------------------===//
462
463/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
464/// condition.
465static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
466  switch (CC) {
467  default: assert(0 && "Unknown integer condition code!");
468  case ISD::SETEQ:  return SPCC::ICC_E;
469  case ISD::SETNE:  return SPCC::ICC_NE;
470  case ISD::SETLT:  return SPCC::ICC_L;
471  case ISD::SETGT:  return SPCC::ICC_G;
472  case ISD::SETLE:  return SPCC::ICC_LE;
473  case ISD::SETGE:  return SPCC::ICC_GE;
474  case ISD::SETULT: return SPCC::ICC_CS;
475  case ISD::SETULE: return SPCC::ICC_LEU;
476  case ISD::SETUGT: return SPCC::ICC_GU;
477  case ISD::SETUGE: return SPCC::ICC_CC;
478  }
479}
480
481/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
482/// FCC condition.
483static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
484  switch (CC) {
485  default: assert(0 && "Unknown fp condition code!");
486  case ISD::SETEQ:
487  case ISD::SETOEQ: return SPCC::FCC_E;
488  case ISD::SETNE:
489  case ISD::SETUNE: return SPCC::FCC_NE;
490  case ISD::SETLT:
491  case ISD::SETOLT: return SPCC::FCC_L;
492  case ISD::SETGT:
493  case ISD::SETOGT: return SPCC::FCC_G;
494  case ISD::SETLE:
495  case ISD::SETOLE: return SPCC::FCC_LE;
496  case ISD::SETGE:
497  case ISD::SETOGE: return SPCC::FCC_GE;
498  case ISD::SETULT: return SPCC::FCC_UL;
499  case ISD::SETULE: return SPCC::FCC_ULE;
500  case ISD::SETUGT: return SPCC::FCC_UG;
501  case ISD::SETUGE: return SPCC::FCC_UGE;
502  case ISD::SETUO:  return SPCC::FCC_U;
503  case ISD::SETO:   return SPCC::FCC_O;
504  case ISD::SETONE: return SPCC::FCC_LG;
505  case ISD::SETUEQ: return SPCC::FCC_UE;
506  }
507}
508
509
510SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
511  : TargetLowering(TM) {
512
513  // Set up the register classes.
514  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
515  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
516  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
517
518  // Turn FP extload into load/fextend
519  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
520  // Sparc doesn't have i1 sign extending load
521  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
522  // Turn FP truncstore into trunc + store.
523  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
524
525  // Custom legalize GlobalAddress nodes into LO/HI parts.
526  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
527  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
528  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
529
530  // Sparc doesn't have sext_inreg, replace them with shl/sra
531  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
532  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
533  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
534
535  // Sparc has no REM or DIVREM operations.
536  setOperationAction(ISD::UREM, MVT::i32, Expand);
537  setOperationAction(ISD::SREM, MVT::i32, Expand);
538  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
539  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
540
541  // Custom expand fp<->sint
542  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
543  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
544
545  // Expand fp<->uint
546  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
547  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
548
549  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
550  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
551
552  // Sparc has no select or setcc: expand to SELECT_CC.
553  setOperationAction(ISD::SELECT, MVT::i32, Expand);
554  setOperationAction(ISD::SELECT, MVT::f32, Expand);
555  setOperationAction(ISD::SELECT, MVT::f64, Expand);
556  setOperationAction(ISD::SETCC, MVT::i32, Expand);
557  setOperationAction(ISD::SETCC, MVT::f32, Expand);
558  setOperationAction(ISD::SETCC, MVT::f64, Expand);
559
560  // Sparc doesn't have BRCOND either, it has BR_CC.
561  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
562  setOperationAction(ISD::BRIND, MVT::Other, Expand);
563  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
564  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
565  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
566  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
567
568  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
569  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
570  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
571
572  // SPARC has no intrinsics for these particular operations.
573  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
574
575  setOperationAction(ISD::FSIN , MVT::f64, Expand);
576  setOperationAction(ISD::FCOS , MVT::f64, Expand);
577  setOperationAction(ISD::FREM , MVT::f64, Expand);
578  setOperationAction(ISD::FSIN , MVT::f32, Expand);
579  setOperationAction(ISD::FCOS , MVT::f32, Expand);
580  setOperationAction(ISD::FREM , MVT::f32, Expand);
581  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
582  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
583  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
584  setOperationAction(ISD::ROTL , MVT::i32, Expand);
585  setOperationAction(ISD::ROTR , MVT::i32, Expand);
586  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
587  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
588  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
589  setOperationAction(ISD::FPOW , MVT::f64, Expand);
590  setOperationAction(ISD::FPOW , MVT::f32, Expand);
591
592  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
593  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
594  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
595
596  // FIXME: Sparc provides these multiplies, but we don't have them yet.
597  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
598
599  // We don't have line number support yet.
600  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
601  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
602  setOperationAction(ISD::LABEL, MVT::Other, Expand);
603
604  // RET must be custom lowered, to meet ABI requirements
605  setOperationAction(ISD::RET               , MVT::Other, Custom);
606
607  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
608  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
609  // VAARG needs to be lowered to not do unaligned accesses for doubles.
610  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
611
612  // Use the default implementation.
613  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
614  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
615  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
616  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
617  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
618
619  // No debug info support yet.
620  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
621  setOperationAction(ISD::LABEL, MVT::Other, Expand);
622  setOperationAction(ISD::DECLARE, MVT::Other, Expand);
623
624  setStackPointerRegisterToSaveRestore(SP::O6);
625
626  if (TM.getSubtarget<SparcSubtarget>().isV9())
627    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
628
629  computeRegisterProperties();
630}
631
632const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
633  switch (Opcode) {
634  default: return 0;
635  case SPISD::CMPICC:     return "SPISD::CMPICC";
636  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
637  case SPISD::BRICC:      return "SPISD::BRICC";
638  case SPISD::BRFCC:      return "SPISD::BRFCC";
639  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
640  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
641  case SPISD::Hi:         return "SPISD::Hi";
642  case SPISD::Lo:         return "SPISD::Lo";
643  case SPISD::FTOI:       return "SPISD::FTOI";
644  case SPISD::ITOF:       return "SPISD::ITOF";
645  case SPISD::CALL:       return "SPISD::CALL";
646  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
647  }
648}
649
650/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
651/// be zero. Op is expected to be a target specific node. Used by DAG
652/// combiner.
653void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
654                                                         const APInt &Mask,
655                                                         APInt &KnownZero,
656                                                         APInt &KnownOne,
657                                                         const SelectionDAG &DAG,
658                                                         unsigned Depth) const {
659  APInt KnownZero2, KnownOne2;
660  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
661
662  switch (Op.getOpcode()) {
663  default: break;
664  case SPISD::SELECT_ICC:
665  case SPISD::SELECT_FCC:
666    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
667                          Depth+1);
668    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
669                          Depth+1);
670    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
671    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
672
673    // Only known if known in both the LHS and RHS.
674    KnownOne &= KnownOne2;
675    KnownZero &= KnownZero2;
676    break;
677  }
678}
679
680// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
681// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
682static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
683                             ISD::CondCode CC, unsigned &SPCC) {
684  if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
685      CC == ISD::SETNE &&
686      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
687        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
688       (LHS.getOpcode() == SPISD::SELECT_FCC &&
689        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
690      isa<ConstantSDNode>(LHS.getOperand(0)) &&
691      isa<ConstantSDNode>(LHS.getOperand(1)) &&
692      cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
693      cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
694    SDOperand CMPCC = LHS.getOperand(3);
695    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
696    LHS = CMPCC.getOperand(0);
697    RHS = CMPCC.getOperand(1);
698  }
699}
700
701static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) {
702  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
703  SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
704  SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
705  SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
706  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
707}
708
709static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) {
710  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
711  Constant *C = N->getConstVal();
712  SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
713  SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
714  SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
715  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
716}
717
718static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
719  // Convert the fp value to integer in an FP register.
720  assert(Op.getValueType() == MVT::i32);
721  Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
722  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
723}
724
725static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
726  assert(Op.getOperand(0).getValueType() == MVT::i32);
727  SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
728  // Convert the int value to FP in an FP register.
729  return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
730}
731
732static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
733  SDOperand Chain = Op.getOperand(0);
734  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
735  SDOperand LHS = Op.getOperand(2);
736  SDOperand RHS = Op.getOperand(3);
737  SDOperand Dest = Op.getOperand(4);
738  unsigned Opc, SPCC = ~0U;
739
740  // If this is a br_cc of a "setcc", and if the setcc got lowered into
741  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
742  LookThroughSetCC(LHS, RHS, CC, SPCC);
743
744  // Get the condition flag.
745  SDOperand CompareFlag;
746  if (LHS.getValueType() == MVT::i32) {
747    std::vector<MVT::ValueType> VTs;
748    VTs.push_back(MVT::i32);
749    VTs.push_back(MVT::Flag);
750    SDOperand Ops[2] = { LHS, RHS };
751    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
752    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
753    Opc = SPISD::BRICC;
754  } else {
755    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
756    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
757    Opc = SPISD::BRFCC;
758  }
759  return DAG.getNode(Opc, MVT::Other, Chain, Dest,
760                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
761}
762
763static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
764  SDOperand LHS = Op.getOperand(0);
765  SDOperand RHS = Op.getOperand(1);
766  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
767  SDOperand TrueVal = Op.getOperand(2);
768  SDOperand FalseVal = Op.getOperand(3);
769  unsigned Opc, SPCC = ~0U;
770
771  // If this is a select_cc of a "setcc", and if the setcc got lowered into
772  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
773  LookThroughSetCC(LHS, RHS, CC, SPCC);
774
775  SDOperand CompareFlag;
776  if (LHS.getValueType() == MVT::i32) {
777    std::vector<MVT::ValueType> VTs;
778    VTs.push_back(LHS.getValueType());   // subcc returns a value
779    VTs.push_back(MVT::Flag);
780    SDOperand Ops[2] = { LHS, RHS };
781    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
782    Opc = SPISD::SELECT_ICC;
783    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
784  } else {
785    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
786    Opc = SPISD::SELECT_FCC;
787    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
788  }
789  return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
790                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
791}
792
793static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
794                              SparcTargetLowering &TLI) {
795  // vastart just stores the address of the VarArgsFrameIndex slot into the
796  // memory location argument.
797  SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
798                                 DAG.getRegister(SP::I6, MVT::i32),
799                                 DAG.getConstant(TLI.getVarArgsFrameOffset(),
800                                                 MVT::i32));
801  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
802  return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
803}
804
805static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
806  SDNode *Node = Op.Val;
807  MVT::ValueType VT = Node->getValueType(0);
808  SDOperand InChain = Node->getOperand(0);
809  SDOperand VAListPtr = Node->getOperand(1);
810  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
811  SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
812  // Increment the pointer, VAList, to the next vaarg
813  SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
814                                  DAG.getConstant(MVT::getSizeInBits(VT)/8,
815                                                  MVT::i32));
816  // Store the incremented VAList to the legalized pointer
817  InChain = DAG.getStore(VAList.getValue(1), NextPtr,
818                         VAListPtr, SV, 0);
819  // Load the actual argument out of the pointer VAList, unless this is an
820  // f64 load.
821  if (VT != MVT::f64)
822    return DAG.getLoad(VT, InChain, VAList, NULL, 0);
823
824  // Otherwise, load it as i64, then do a bitconvert.
825  SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
826
827  // Bit-Convert the value to f64.
828  SDOperand Ops[2] = {
829    DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
830    V.getValue(1)
831  };
832  return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::f64, MVT::Other),
833                     Ops, 2);
834}
835
836static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) {
837  SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
838  SDOperand Size  = Op.getOperand(1);  // Legalize the size.
839
840  unsigned SPReg = SP::O6;
841  SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
842  SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
843  Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
844
845  // The resultant pointer is actually 16 words from the bottom of the stack,
846  // to provide a register spill area.
847  SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
848                                 DAG.getConstant(96, MVT::i32));
849  std::vector<MVT::ValueType> Tys;
850  Tys.push_back(MVT::i32);
851  Tys.push_back(MVT::Other);
852  SDOperand Ops[2] = { NewVal, Chain };
853  return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
854}
855
856
857SDOperand SparcTargetLowering::
858LowerOperation(SDOperand Op, SelectionDAG &DAG) {
859  switch (Op.getOpcode()) {
860  default: assert(0 && "Should not custom lower this!");
861  // Frame & Return address.  Currently unimplemented
862  case ISD::RETURNADDR: return SDOperand();
863  case ISD::FRAMEADDR:  return SDOperand();
864  case ISD::GlobalTLSAddress:
865    assert(0 && "TLS not implemented for Sparc.");
866  case ISD::GlobalAddress:      return LowerGLOBALADDRESS(Op, DAG);
867  case ISD::ConstantPool:       return LowerCONSTANTPOOL(Op, DAG);
868  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
869  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
870  case ISD::BR_CC:              return LowerBR_CC(Op, DAG);
871  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
872  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
873  case ISD::VAARG:              return LowerVAARG(Op, DAG);
874  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
875  case ISD::CALL:               return LowerCALL(Op, DAG);
876  case ISD::RET:                return LowerRET(Op, DAG);
877  }
878}
879
880MachineBasicBlock *
881SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
882                                                 MachineBasicBlock *BB) {
883  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
884  unsigned BROpcode;
885  unsigned CC;
886  // Figure out the conditional branch opcode to use for this select_cc.
887  switch (MI->getOpcode()) {
888  default: assert(0 && "Unknown SELECT_CC!");
889  case SP::SELECT_CC_Int_ICC:
890  case SP::SELECT_CC_FP_ICC:
891  case SP::SELECT_CC_DFP_ICC:
892    BROpcode = SP::BCOND;
893    break;
894  case SP::SELECT_CC_Int_FCC:
895  case SP::SELECT_CC_FP_FCC:
896  case SP::SELECT_CC_DFP_FCC:
897    BROpcode = SP::FBCOND;
898    break;
899  }
900
901  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
902
903  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
904  // control-flow pattern.  The incoming instruction knows the destination vreg
905  // to set, the condition code register to branch on, the true/false values to
906  // select between, and a branch opcode to use.
907  const BasicBlock *LLVM_BB = BB->getBasicBlock();
908  ilist<MachineBasicBlock>::iterator It = BB;
909  ++It;
910
911  //  thisMBB:
912  //  ...
913  //   TrueVal = ...
914  //   [f]bCC copy1MBB
915  //   fallthrough --> copy0MBB
916  MachineBasicBlock *thisMBB = BB;
917  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
918  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
919  BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
920  MachineFunction *F = BB->getParent();
921  F->getBasicBlockList().insert(It, copy0MBB);
922  F->getBasicBlockList().insert(It, sinkMBB);
923  // Update machine-CFG edges by first adding all successors of the current
924  // block to the new block which will contain the Phi node for the select.
925  for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
926      e = BB->succ_end(); i != e; ++i)
927    sinkMBB->addSuccessor(*i);
928  // Next, remove all successors of the current block, and add the true
929  // and fallthrough blocks as its successors.
930  while(!BB->succ_empty())
931    BB->removeSuccessor(BB->succ_begin());
932  BB->addSuccessor(copy0MBB);
933  BB->addSuccessor(sinkMBB);
934
935  //  copy0MBB:
936  //   %FalseValue = ...
937  //   # fallthrough to sinkMBB
938  BB = copy0MBB;
939
940  // Update machine-CFG edges
941  BB->addSuccessor(sinkMBB);
942
943  //  sinkMBB:
944  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
945  //  ...
946  BB = sinkMBB;
947  BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
948    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
949    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
950
951  delete MI;   // The pseudo instruction is gone now.
952  return BB;
953}
954
955