SparcISelLowering.cpp revision 7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcMachineFunctionInfo.h" 17#include "SparcRegisterInfo.h" 18#include "SparcTargetMachine.h" 19#include "MCTargetDesc/SparcBaseInfo.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/SelectionDAG.h" 26#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 27#include "llvm/IR/DerivedTypes.h" 28#include "llvm/IR/Function.h" 29#include "llvm/IR/Module.h" 30#include "llvm/Support/ErrorHandling.h" 31using namespace llvm; 32 33 34//===----------------------------------------------------------------------===// 35// Calling Convention Implementation 36//===----------------------------------------------------------------------===// 37 38static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 39 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 40 ISD::ArgFlagsTy &ArgFlags, CCState &State) 41{ 42 assert (ArgFlags.isSRet()); 43 44 // Assign SRet argument. 45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 46 0, 47 LocVT, LocInfo)); 48 return true; 49} 50 51static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 52 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, CCState &State) 54{ 55 static const uint16_t RegList[] = { 56 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 57 }; 58 // Try to get first reg. 59 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 60 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 61 } else { 62 // Assign whole thing in stack. 63 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 64 State.AllocateStack(8,4), 65 LocVT, LocInfo)); 66 return true; 67 } 68 69 // Try to get second reg. 70 if (unsigned Reg = State.AllocateReg(RegList, 6)) 71 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 72 else 73 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 74 State.AllocateStack(4,4), 75 LocVT, LocInfo)); 76 return true; 77} 78 79// Allocate a full-sized argument for the 64-bit ABI. 80static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, 81 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 82 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 83 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) && 84 "Can't handle non-64 bits locations"); 85 86 // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. 87 unsigned Offset = State.AllocateStack(8, 8); 88 unsigned Reg = 0; 89 90 if (LocVT == MVT::i64 && Offset < 6*8) 91 // Promote integers to %i0-%i5. 92 Reg = SP::I0 + Offset/8; 93 else if (LocVT == MVT::f64 && Offset < 16*8) 94 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). 95 Reg = SP::D0 + Offset/8; 96 else if (LocVT == MVT::f32 && Offset < 16*8) 97 // Promote floats to %f1, %f3, ... 98 Reg = SP::F1 + Offset/4; 99 100 // Promote to register when possible, otherwise use the stack slot. 101 if (Reg) { 102 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 103 return true; 104 } 105 106 // This argument goes on the stack in an 8-byte slot. 107 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to 108 // the right-aligned float. The first 4 bytes of the stack slot are undefined. 109 if (LocVT == MVT::f32) 110 Offset += 4; 111 112 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 113 return true; 114} 115 116// Allocate a half-sized argument for the 64-bit ABI. 117// 118// This is used when passing { float, int } structs by value in registers. 119static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, 120 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 121 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 122 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); 123 unsigned Offset = State.AllocateStack(4, 4); 124 125 if (LocVT == MVT::f32 && Offset < 16*8) { 126 // Promote floats to %f0-%f31. 127 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, 128 LocVT, LocInfo)); 129 return true; 130 } 131 132 if (LocVT == MVT::i32 && Offset < 6*8) { 133 // Promote integers to %i0-%i5, using half the register. 134 unsigned Reg = SP::I0 + Offset/8; 135 LocVT = MVT::i64; 136 LocInfo = CCValAssign::AExt; 137 138 // Set the Custom bit if this i32 goes in the high bits of a register. 139 if (Offset % 8 == 0) 140 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, 141 LocVT, LocInfo)); 142 else 143 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 144 return true; 145 } 146 147 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 148 return true; 149} 150 151#include "SparcGenCallingConv.inc" 152 153// The calling conventions in SparcCallingConv.td are described in terms of the 154// callee's register window. This function translates registers to the 155// corresponding caller window %o register. 156static unsigned toCallerWindow(unsigned Reg) { 157 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); 158 if (Reg >= SP::I0 && Reg <= SP::I7) 159 return Reg - SP::I0 + SP::O0; 160 return Reg; 161} 162 163SDValue 164SparcTargetLowering::LowerReturn(SDValue Chain, 165 CallingConv::ID CallConv, bool IsVarArg, 166 const SmallVectorImpl<ISD::OutputArg> &Outs, 167 const SmallVectorImpl<SDValue> &OutVals, 168 SDLoc DL, SelectionDAG &DAG) const { 169 if (Subtarget->is64Bit()) 170 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 171 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 172} 173 174SDValue 175SparcTargetLowering::LowerReturn_32(SDValue Chain, 176 CallingConv::ID CallConv, bool IsVarArg, 177 const SmallVectorImpl<ISD::OutputArg> &Outs, 178 const SmallVectorImpl<SDValue> &OutVals, 179 SDLoc DL, SelectionDAG &DAG) const { 180 MachineFunction &MF = DAG.getMachineFunction(); 181 182 // CCValAssign - represent the assignment of the return value to locations. 183 SmallVector<CCValAssign, 16> RVLocs; 184 185 // CCState - Info about the registers and stack slot. 186 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 187 DAG.getTarget(), RVLocs, *DAG.getContext()); 188 189 // Analyze return values. 190 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 191 192 SDValue Flag; 193 SmallVector<SDValue, 4> RetOps(1, Chain); 194 // Make room for the return address offset. 195 RetOps.push_back(SDValue()); 196 197 // Copy the result values into the output registers. 198 for (unsigned i = 0; i != RVLocs.size(); ++i) { 199 CCValAssign &VA = RVLocs[i]; 200 assert(VA.isRegLoc() && "Can only return in registers!"); 201 202 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), 203 OutVals[i], Flag); 204 205 // Guarantee that all emitted copies are stuck together with flags. 206 Flag = Chain.getValue(1); 207 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 208 } 209 210 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot 211 // If the function returns a struct, copy the SRetReturnReg to I0 212 if (MF.getFunction()->hasStructRetAttr()) { 213 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 214 unsigned Reg = SFI->getSRetReturnReg(); 215 if (!Reg) 216 llvm_unreachable("sret virtual register not created in the entry block"); 217 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 218 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); 219 Flag = Chain.getValue(1); 220 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); 221 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 222 } 223 224 RetOps[0] = Chain; // Update chain. 225 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 226 227 // Add the flag if we have it. 228 if (Flag.getNode()) 229 RetOps.push_back(Flag); 230 231 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 232 &RetOps[0], RetOps.size()); 233} 234 235// Lower return values for the 64-bit ABI. 236// Return values are passed the exactly the same way as function arguments. 237SDValue 238SparcTargetLowering::LowerReturn_64(SDValue Chain, 239 CallingConv::ID CallConv, bool IsVarArg, 240 const SmallVectorImpl<ISD::OutputArg> &Outs, 241 const SmallVectorImpl<SDValue> &OutVals, 242 SDLoc DL, SelectionDAG &DAG) const { 243 // CCValAssign - represent the assignment of the return value to locations. 244 SmallVector<CCValAssign, 16> RVLocs; 245 246 // CCState - Info about the registers and stack slot. 247 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 248 DAG.getTarget(), RVLocs, *DAG.getContext()); 249 250 // Analyze return values. 251 CCInfo.AnalyzeReturn(Outs, CC_Sparc64); 252 253 SDValue Flag; 254 SmallVector<SDValue, 4> RetOps(1, Chain); 255 256 // The second operand on the return instruction is the return address offset. 257 // The return address is always %i7+8 with the 64-bit ABI. 258 RetOps.push_back(DAG.getConstant(8, MVT::i32)); 259 260 // Copy the result values into the output registers. 261 for (unsigned i = 0; i != RVLocs.size(); ++i) { 262 CCValAssign &VA = RVLocs[i]; 263 assert(VA.isRegLoc() && "Can only return in registers!"); 264 SDValue OutVal = OutVals[i]; 265 266 // Integer return values must be sign or zero extended by the callee. 267 switch (VA.getLocInfo()) { 268 case CCValAssign::SExt: 269 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 270 break; 271 case CCValAssign::ZExt: 272 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); 273 break; 274 case CCValAssign::AExt: 275 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); 276 default: 277 break; 278 } 279 280 // The custom bit on an i32 return value indicates that it should be passed 281 // in the high bits of the register. 282 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 283 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 284 DAG.getConstant(32, MVT::i32)); 285 286 // The next value may go in the low bits of the same register. 287 // Handle both at once. 288 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { 289 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); 290 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); 291 // Skip the next value, it's already done. 292 ++i; 293 } 294 } 295 296 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); 297 298 // Guarantee that all emitted copies are stuck together with flags. 299 Flag = Chain.getValue(1); 300 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 301 } 302 303 RetOps[0] = Chain; // Update chain. 304 305 // Add the flag if we have it. 306 if (Flag.getNode()) 307 RetOps.push_back(Flag); 308 309 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 310 &RetOps[0], RetOps.size()); 311} 312 313SDValue SparcTargetLowering:: 314LowerFormalArguments(SDValue Chain, 315 CallingConv::ID CallConv, 316 bool IsVarArg, 317 const SmallVectorImpl<ISD::InputArg> &Ins, 318 SDLoc DL, 319 SelectionDAG &DAG, 320 SmallVectorImpl<SDValue> &InVals) const { 321 if (Subtarget->is64Bit()) 322 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins, 323 DL, DAG, InVals); 324 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins, 325 DL, DAG, InVals); 326} 327 328/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are 329/// passed in either one or two GPRs, including FP values. TODO: we should 330/// pass FP values in FP registers for fastcc functions. 331SDValue SparcTargetLowering:: 332LowerFormalArguments_32(SDValue Chain, 333 CallingConv::ID CallConv, 334 bool isVarArg, 335 const SmallVectorImpl<ISD::InputArg> &Ins, 336 SDLoc dl, 337 SelectionDAG &DAG, 338 SmallVectorImpl<SDValue> &InVals) const { 339 MachineFunction &MF = DAG.getMachineFunction(); 340 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 341 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 342 343 // Assign locations to all of the incoming arguments. 344 SmallVector<CCValAssign, 16> ArgLocs; 345 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 346 getTargetMachine(), ArgLocs, *DAG.getContext()); 347 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 348 349 const unsigned StackOffset = 92; 350 351 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 352 CCValAssign &VA = ArgLocs[i]; 353 354 if (i == 0 && Ins[i].Flags.isSRet()) { 355 // Get SRet from [%fp+64]. 356 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 357 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 358 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 359 MachinePointerInfo(), 360 false, false, false, 0); 361 InVals.push_back(Arg); 362 continue; 363 } 364 365 if (VA.isRegLoc()) { 366 if (VA.needsCustom()) { 367 assert(VA.getLocVT() == MVT::f64); 368 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 369 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 370 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 371 372 assert(i+1 < e); 373 CCValAssign &NextVA = ArgLocs[++i]; 374 375 SDValue LoVal; 376 if (NextVA.isMemLoc()) { 377 int FrameIdx = MF.getFrameInfo()-> 378 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 379 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 380 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 381 MachinePointerInfo(), 382 false, false, false, 0); 383 } else { 384 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 385 &SP::IntRegsRegClass); 386 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 387 } 388 SDValue WholeValue = 389 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 390 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 391 InVals.push_back(WholeValue); 392 continue; 393 } 394 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 395 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 396 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 397 if (VA.getLocVT() == MVT::f32) 398 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 399 else if (VA.getLocVT() != MVT::i32) { 400 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 401 DAG.getValueType(VA.getLocVT())); 402 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 403 } 404 InVals.push_back(Arg); 405 continue; 406 } 407 408 assert(VA.isMemLoc()); 409 410 unsigned Offset = VA.getLocMemOffset()+StackOffset; 411 412 if (VA.needsCustom()) { 413 assert(VA.getValVT() == MVT::f64); 414 // If it is double-word aligned, just load. 415 if (Offset % 8 == 0) { 416 int FI = MF.getFrameInfo()->CreateFixedObject(8, 417 Offset, 418 true); 419 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 420 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 421 MachinePointerInfo(), 422 false,false, false, 0); 423 InVals.push_back(Load); 424 continue; 425 } 426 427 int FI = MF.getFrameInfo()->CreateFixedObject(4, 428 Offset, 429 true); 430 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 431 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 432 MachinePointerInfo(), 433 false, false, false, 0); 434 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 435 Offset+4, 436 true); 437 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 438 439 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 440 MachinePointerInfo(), 441 false, false, false, 0); 442 443 SDValue WholeValue = 444 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 445 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 446 InVals.push_back(WholeValue); 447 continue; 448 } 449 450 int FI = MF.getFrameInfo()->CreateFixedObject(4, 451 Offset, 452 true); 453 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 454 SDValue Load ; 455 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 456 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 457 MachinePointerInfo(), 458 false, false, false, 0); 459 } else { 460 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 461 // Sparc is big endian, so add an offset based on the ObjectVT. 462 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 463 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 464 DAG.getConstant(Offset, MVT::i32)); 465 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 466 MachinePointerInfo(), 467 VA.getValVT(), false, false,0); 468 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 469 } 470 InVals.push_back(Load); 471 } 472 473 if (MF.getFunction()->hasStructRetAttr()) { 474 // Copy the SRet Argument to SRetReturnReg. 475 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 476 unsigned Reg = SFI->getSRetReturnReg(); 477 if (!Reg) { 478 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 479 SFI->setSRetReturnReg(Reg); 480 } 481 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 482 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 483 } 484 485 // Store remaining ArgRegs to the stack if this is a varargs function. 486 if (isVarArg) { 487 static const uint16_t ArgRegs[] = { 488 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 489 }; 490 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 491 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 492 unsigned ArgOffset = CCInfo.getNextStackOffset(); 493 if (NumAllocated == 6) 494 ArgOffset += StackOffset; 495 else { 496 assert(!ArgOffset); 497 ArgOffset = 68+4*NumAllocated; 498 } 499 500 // Remember the vararg offset for the va_start implementation. 501 FuncInfo->setVarArgsFrameOffset(ArgOffset); 502 503 std::vector<SDValue> OutChains; 504 505 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 506 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 507 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 508 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 509 510 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 511 true); 512 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 513 514 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 515 MachinePointerInfo(), 516 false, false, 0)); 517 ArgOffset += 4; 518 } 519 520 if (!OutChains.empty()) { 521 OutChains.push_back(Chain); 522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 523 &OutChains[0], OutChains.size()); 524 } 525 } 526 527 return Chain; 528} 529 530// Lower formal arguments for the 64 bit ABI. 531SDValue SparcTargetLowering:: 532LowerFormalArguments_64(SDValue Chain, 533 CallingConv::ID CallConv, 534 bool IsVarArg, 535 const SmallVectorImpl<ISD::InputArg> &Ins, 536 SDLoc DL, 537 SelectionDAG &DAG, 538 SmallVectorImpl<SDValue> &InVals) const { 539 MachineFunction &MF = DAG.getMachineFunction(); 540 541 // Analyze arguments according to CC_Sparc64. 542 SmallVector<CCValAssign, 16> ArgLocs; 543 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 544 getTargetMachine(), ArgLocs, *DAG.getContext()); 545 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); 546 547 // The argument array begins at %fp+BIAS+128, after the register save area. 548 const unsigned ArgArea = 128; 549 550 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 551 CCValAssign &VA = ArgLocs[i]; 552 if (VA.isRegLoc()) { 553 // This argument is passed in a register. 554 // All integer register arguments are promoted by the caller to i64. 555 556 // Create a virtual register for the promoted live-in value. 557 unsigned VReg = MF.addLiveIn(VA.getLocReg(), 558 getRegClassFor(VA.getLocVT())); 559 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); 560 561 // Get the high bits for i32 struct elements. 562 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 563 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, 564 DAG.getConstant(32, MVT::i32)); 565 566 // The caller promoted the argument, so insert an Assert?ext SDNode so we 567 // won't promote the value again in this function. 568 switch (VA.getLocInfo()) { 569 case CCValAssign::SExt: 570 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, 571 DAG.getValueType(VA.getValVT())); 572 break; 573 case CCValAssign::ZExt: 574 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, 575 DAG.getValueType(VA.getValVT())); 576 break; 577 default: 578 break; 579 } 580 581 // Truncate the register down to the argument type. 582 if (VA.isExtInLoc()) 583 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); 584 585 InVals.push_back(Arg); 586 continue; 587 } 588 589 // The registers are exhausted. This argument was passed on the stack. 590 assert(VA.isMemLoc()); 591 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the 592 // beginning of the arguments area at %fp+BIAS+128. 593 unsigned Offset = VA.getLocMemOffset() + ArgArea; 594 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; 595 // Adjust offset for extended arguments, SPARC is big-endian. 596 // The caller will have written the full slot with extended bytes, but we 597 // prefer our own extending loads. 598 if (VA.isExtInLoc()) 599 Offset += 8 - ValSize; 600 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true); 601 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, 602 DAG.getFrameIndex(FI, getPointerTy()), 603 MachinePointerInfo::getFixedStack(FI), 604 false, false, false, 0)); 605 } 606 607 if (!IsVarArg) 608 return Chain; 609 610 // This function takes variable arguments, some of which may have been passed 611 // in registers %i0-%i5. Variable floating point arguments are never passed 612 // in floating point registers. They go on %i0-%i5 or on the stack like 613 // integer arguments. 614 // 615 // The va_start intrinsic needs to know the offset to the first variable 616 // argument. 617 unsigned ArgOffset = CCInfo.getNextStackOffset(); 618 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 619 // Skip the 128 bytes of register save area. 620 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea + 621 Subtarget->getStackPointerBias()); 622 623 // Save the variable arguments that were passed in registers. 624 // The caller is required to reserve stack space for 6 arguments regardless 625 // of how many arguments were actually passed. 626 SmallVector<SDValue, 8> OutChains; 627 for (; ArgOffset < 6*8; ArgOffset += 8) { 628 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); 629 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 630 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true); 631 OutChains.push_back(DAG.getStore(Chain, DL, VArg, 632 DAG.getFrameIndex(FI, getPointerTy()), 633 MachinePointerInfo::getFixedStack(FI), 634 false, false, 0)); 635 } 636 637 if (!OutChains.empty()) 638 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 639 &OutChains[0], OutChains.size()); 640 641 return Chain; 642} 643 644SDValue 645SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 646 SmallVectorImpl<SDValue> &InVals) const { 647 if (Subtarget->is64Bit()) 648 return LowerCall_64(CLI, InVals); 649 return LowerCall_32(CLI, InVals); 650} 651 652static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, 653 ImmutableCallSite *CS) { 654 if (CS) 655 return CS->hasFnAttr(Attribute::ReturnsTwice); 656 657 const Function *CalleeFn = 0; 658 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 659 CalleeFn = dyn_cast<Function>(G->getGlobal()); 660 } else if (ExternalSymbolSDNode *E = 661 dyn_cast<ExternalSymbolSDNode>(Callee)) { 662 const Function *Fn = DAG.getMachineFunction().getFunction(); 663 const Module *M = Fn->getParent(); 664 const char *CalleeName = E->getSymbol(); 665 CalleeFn = M->getFunction(CalleeName); 666 } 667 668 if (!CalleeFn) 669 return false; 670 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice); 671} 672 673// Lower a call for the 32-bit ABI. 674SDValue 675SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 676 SmallVectorImpl<SDValue> &InVals) const { 677 SelectionDAG &DAG = CLI.DAG; 678 SDLoc &dl = CLI.DL; 679 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 680 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 681 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 682 SDValue Chain = CLI.Chain; 683 SDValue Callee = CLI.Callee; 684 bool &isTailCall = CLI.IsTailCall; 685 CallingConv::ID CallConv = CLI.CallConv; 686 bool isVarArg = CLI.IsVarArg; 687 688 // Sparc target does not yet support tail call optimization. 689 isTailCall = false; 690 691 // Analyze operands of the call, assigning locations to each operand. 692 SmallVector<CCValAssign, 16> ArgLocs; 693 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 694 DAG.getTarget(), ArgLocs, *DAG.getContext()); 695 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 696 697 // Get the size of the outgoing arguments stack space requirement. 698 unsigned ArgsSize = CCInfo.getNextStackOffset(); 699 700 // Keep stack frames 8-byte aligned. 701 ArgsSize = (ArgsSize+7) & ~7; 702 703 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 704 705 // Create local copies for byval args. 706 SmallVector<SDValue, 8> ByValArgs; 707 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 708 ISD::ArgFlagsTy Flags = Outs[i].Flags; 709 if (!Flags.isByVal()) 710 continue; 711 712 SDValue Arg = OutVals[i]; 713 unsigned Size = Flags.getByValSize(); 714 unsigned Align = Flags.getByValAlign(); 715 716 int FI = MFI->CreateStackObject(Size, Align, false); 717 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 718 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 719 720 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 721 false, // isVolatile, 722 (Size <= 32), // AlwaysInline if size <= 32 723 MachinePointerInfo(), MachinePointerInfo()); 724 ByValArgs.push_back(FIPtr); 725 } 726 727 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), 728 dl); 729 730 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 731 SmallVector<SDValue, 8> MemOpChains; 732 733 const unsigned StackOffset = 92; 734 bool hasStructRetAttr = false; 735 // Walk the register/memloc assignments, inserting copies/loads. 736 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 737 i != e; 738 ++i, ++realArgIdx) { 739 CCValAssign &VA = ArgLocs[i]; 740 SDValue Arg = OutVals[realArgIdx]; 741 742 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 743 744 // Use local copy if it is a byval arg. 745 if (Flags.isByVal()) 746 Arg = ByValArgs[byvalArgIdx++]; 747 748 // Promote the value if needed. 749 switch (VA.getLocInfo()) { 750 default: llvm_unreachable("Unknown loc info!"); 751 case CCValAssign::Full: break; 752 case CCValAssign::SExt: 753 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 754 break; 755 case CCValAssign::ZExt: 756 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 757 break; 758 case CCValAssign::AExt: 759 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 760 break; 761 case CCValAssign::BCvt: 762 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 763 break; 764 } 765 766 if (Flags.isSRet()) { 767 assert(VA.needsCustom()); 768 // store SRet argument in %sp+64 769 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 770 SDValue PtrOff = DAG.getIntPtrConstant(64); 771 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 772 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 773 MachinePointerInfo(), 774 false, false, 0)); 775 hasStructRetAttr = true; 776 continue; 777 } 778 779 if (VA.needsCustom()) { 780 assert(VA.getLocVT() == MVT::f64); 781 782 if (VA.isMemLoc()) { 783 unsigned Offset = VA.getLocMemOffset() + StackOffset; 784 // if it is double-word aligned, just store. 785 if (Offset % 8 == 0) { 786 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 787 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 788 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 789 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 790 MachinePointerInfo(), 791 false, false, 0)); 792 continue; 793 } 794 } 795 796 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 797 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 798 Arg, StackPtr, MachinePointerInfo(), 799 false, false, 0); 800 // Sparc is big-endian, so the high part comes first. 801 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 802 MachinePointerInfo(), false, false, false, 0); 803 // Increment the pointer to the other half. 804 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 805 DAG.getIntPtrConstant(4)); 806 // Load the low part. 807 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 808 MachinePointerInfo(), false, false, false, 0); 809 810 if (VA.isRegLoc()) { 811 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 812 assert(i+1 != e); 813 CCValAssign &NextVA = ArgLocs[++i]; 814 if (NextVA.isRegLoc()) { 815 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 816 } else { 817 // Store the low part in stack. 818 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 819 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 820 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 821 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 822 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 823 MachinePointerInfo(), 824 false, false, 0)); 825 } 826 } else { 827 unsigned Offset = VA.getLocMemOffset() + StackOffset; 828 // Store the high part. 829 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 830 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 831 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 832 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 833 MachinePointerInfo(), 834 false, false, 0)); 835 // Store the low part. 836 PtrOff = DAG.getIntPtrConstant(Offset+4); 837 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 838 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 839 MachinePointerInfo(), 840 false, false, 0)); 841 } 842 continue; 843 } 844 845 // Arguments that can be passed on register must be kept at 846 // RegsToPass vector 847 if (VA.isRegLoc()) { 848 if (VA.getLocVT() != MVT::f32) { 849 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 850 continue; 851 } 852 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 853 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 854 continue; 855 } 856 857 assert(VA.isMemLoc()); 858 859 // Create a store off the stack pointer for this argument. 860 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 861 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 862 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 863 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 864 MachinePointerInfo(), 865 false, false, 0)); 866 } 867 868 869 // Emit all stores, make sure the occur before any copies into physregs. 870 if (!MemOpChains.empty()) 871 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 872 &MemOpChains[0], MemOpChains.size()); 873 874 // Build a sequence of copy-to-reg nodes chained together with token 875 // chain and flag operands which copy the outgoing args into registers. 876 // The InFlag in necessary since all emitted instructions must be 877 // stuck together. 878 SDValue InFlag; 879 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 880 unsigned Reg = toCallerWindow(RegsToPass[i].first); 881 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 882 InFlag = Chain.getValue(1); 883 } 884 885 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 886 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); 887 888 // If the callee is a GlobalAddress node (quite common, every direct call is) 889 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 890 // Likewise ExternalSymbol -> TargetExternalSymbol. 891 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 892 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 893 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 894 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 895 896 // Returns a chain & a flag for retval copy to use 897 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 898 SmallVector<SDValue, 8> Ops; 899 Ops.push_back(Chain); 900 Ops.push_back(Callee); 901 if (hasStructRetAttr) 902 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 903 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 904 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), 905 RegsToPass[i].second.getValueType())); 906 907 // Add a register mask operand representing the call-preserved registers. 908 const SparcRegisterInfo *TRI = 909 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); 910 const uint32_t *Mask = ((hasReturnsTwice) 911 ? TRI->getRTCallPreservedMask(CallConv) 912 : TRI->getCallPreservedMask(CallConv)); 913 assert(Mask && "Missing call preserved mask for calling convention"); 914 Ops.push_back(DAG.getRegisterMask(Mask)); 915 916 if (InFlag.getNode()) 917 Ops.push_back(InFlag); 918 919 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 920 InFlag = Chain.getValue(1); 921 922 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 923 DAG.getIntPtrConstant(0, true), InFlag, dl); 924 InFlag = Chain.getValue(1); 925 926 // Assign locations to each value returned by this call. 927 SmallVector<CCValAssign, 16> RVLocs; 928 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 929 DAG.getTarget(), RVLocs, *DAG.getContext()); 930 931 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 932 933 // Copy all of the result registers out of their specified physreg. 934 for (unsigned i = 0; i != RVLocs.size(); ++i) { 935 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), 936 RVLocs[i].getValVT(), InFlag).getValue(1); 937 InFlag = Chain.getValue(2); 938 InVals.push_back(Chain.getValue(0)); 939 } 940 941 return Chain; 942} 943 944// This functions returns true if CalleeName is a ABI function that returns 945// a long double (fp128). 946static bool isFP128ABICall(const char *CalleeName) 947{ 948 static const char *const ABICalls[] = 949 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div", 950 "_Q_sqrt", "_Q_neg", 951 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq", 952 "_Q_lltoq", "_Q_ulltoq", 953 0 954 }; 955 for (const char * const *I = ABICalls; *I != 0; ++I) 956 if (strcmp(CalleeName, *I) == 0) 957 return true; 958 return false; 959} 960 961unsigned 962SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 963{ 964 const Function *CalleeFn = 0; 965 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 966 CalleeFn = dyn_cast<Function>(G->getGlobal()); 967 } else if (ExternalSymbolSDNode *E = 968 dyn_cast<ExternalSymbolSDNode>(Callee)) { 969 const Function *Fn = DAG.getMachineFunction().getFunction(); 970 const Module *M = Fn->getParent(); 971 const char *CalleeName = E->getSymbol(); 972 CalleeFn = M->getFunction(CalleeName); 973 if (!CalleeFn && isFP128ABICall(CalleeName)) 974 return 16; // Return sizeof(fp128) 975 } 976 977 if (!CalleeFn) 978 return 0; 979 980 assert(CalleeFn->hasStructRetAttr() && 981 "Callee does not have the StructRet attribute."); 982 983 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 984 Type *ElementTy = Ty->getElementType(); 985 return getDataLayout()->getTypeAllocSize(ElementTy); 986} 987 988 989// Fixup floating point arguments in the ... part of a varargs call. 990// 991// The SPARC v9 ABI requires that floating point arguments are treated the same 992// as integers when calling a varargs function. This does not apply to the 993// fixed arguments that are part of the function's prototype. 994// 995// This function post-processes a CCValAssign array created by 996// AnalyzeCallOperands(). 997static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, 998 ArrayRef<ISD::OutputArg> Outs) { 999 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1000 const CCValAssign &VA = ArgLocs[i]; 1001 // FIXME: What about f32 arguments? C promotes them to f64 when calling 1002 // varargs functions. 1003 if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64) 1004 continue; 1005 // The fixed arguments to a varargs function still go in FP registers. 1006 if (Outs[VA.getValNo()].IsFixed) 1007 continue; 1008 1009 // This floating point argument should be reassigned. 1010 CCValAssign NewVA; 1011 1012 // Determine the offset into the argument array. 1013 unsigned Offset = 8 * (VA.getLocReg() - SP::D0); 1014 assert(Offset < 16*8 && "Offset out of range, bad register enum?"); 1015 1016 if (Offset < 6*8) { 1017 // This argument should go in %i0-%i5. 1018 unsigned IReg = SP::I0 + Offset/8; 1019 // Full register, just bitconvert into i64. 1020 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), 1021 IReg, MVT::i64, CCValAssign::BCvt); 1022 } else { 1023 // This needs to go to memory, we're out of integer registers. 1024 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), 1025 Offset, VA.getLocVT(), VA.getLocInfo()); 1026 } 1027 ArgLocs[i] = NewVA; 1028 } 1029} 1030 1031// Lower a call for the 64-bit ABI. 1032SDValue 1033SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 1034 SmallVectorImpl<SDValue> &InVals) const { 1035 SelectionDAG &DAG = CLI.DAG; 1036 SDLoc DL = CLI.DL; 1037 SDValue Chain = CLI.Chain; 1038 1039 // Sparc target does not yet support tail call optimization. 1040 CLI.IsTailCall = false; 1041 1042 // Analyze operands of the call, assigning locations to each operand. 1043 SmallVector<CCValAssign, 16> ArgLocs; 1044 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1045 DAG.getTarget(), ArgLocs, *DAG.getContext()); 1046 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); 1047 1048 // Get the size of the outgoing arguments stack space requirement. 1049 // The stack offset computed by CC_Sparc64 includes all arguments. 1050 // Called functions expect 6 argument words to exist in the stack frame, used 1051 // or not. 1052 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); 1053 1054 // Keep stack frames 16-byte aligned. 1055 ArgsSize = RoundUpToAlignment(ArgsSize, 16); 1056 1057 // Varargs calls require special treatment. 1058 if (CLI.IsVarArg) 1059 fixupVariableFloatArgs(ArgLocs, CLI.Outs); 1060 1061 // Adjust the stack pointer to make room for the arguments. 1062 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls 1063 // with more than 6 arguments. 1064 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1065 DL); 1066 1067 // Collect the set of registers to pass to the function and their values. 1068 // This will be emitted as a sequence of CopyToReg nodes glued to the call 1069 // instruction. 1070 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1071 1072 // Collect chains from all the memory opeations that copy arguments to the 1073 // stack. They must follow the stack pointer adjustment above and precede the 1074 // call instruction itself. 1075 SmallVector<SDValue, 8> MemOpChains; 1076 1077 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1078 const CCValAssign &VA = ArgLocs[i]; 1079 SDValue Arg = CLI.OutVals[i]; 1080 1081 // Promote the value if needed. 1082 switch (VA.getLocInfo()) { 1083 default: 1084 llvm_unreachable("Unknown location info!"); 1085 case CCValAssign::Full: 1086 break; 1087 case CCValAssign::SExt: 1088 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 1089 break; 1090 case CCValAssign::ZExt: 1091 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 1092 break; 1093 case CCValAssign::AExt: 1094 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 1095 break; 1096 case CCValAssign::BCvt: 1097 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 1098 break; 1099 } 1100 1101 if (VA.isRegLoc()) { 1102 // The custom bit on an i32 return value indicates that it should be 1103 // passed in the high bits of the register. 1104 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 1105 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, 1106 DAG.getConstant(32, MVT::i32)); 1107 1108 // The next value may go in the low bits of the same register. 1109 // Handle both at once. 1110 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && 1111 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { 1112 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, 1113 CLI.OutVals[i+1]); 1114 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); 1115 // Skip the next value, it's already done. 1116 ++i; 1117 } 1118 } 1119 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); 1120 continue; 1121 } 1122 1123 assert(VA.isMemLoc()); 1124 1125 // Create a store off the stack pointer for this argument. 1126 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 1127 // The argument area starts at %fp+BIAS+128 in the callee frame, 1128 // %sp+BIAS+128 in ours. 1129 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + 1130 Subtarget->getStackPointerBias() + 1131 128); 1132 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 1133 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, 1134 MachinePointerInfo(), 1135 false, false, 0)); 1136 } 1137 1138 // Emit all stores, make sure they occur before the call. 1139 if (!MemOpChains.empty()) 1140 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 1141 &MemOpChains[0], MemOpChains.size()); 1142 1143 // Build a sequence of CopyToReg nodes glued together with token chain and 1144 // glue operands which copy the outgoing args into registers. The InGlue is 1145 // necessary since all emitted instructions must be stuck together in order 1146 // to pass the live physical registers. 1147 SDValue InGlue; 1148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1149 Chain = DAG.getCopyToReg(Chain, DL, 1150 RegsToPass[i].first, RegsToPass[i].second, InGlue); 1151 InGlue = Chain.getValue(1); 1152 } 1153 1154 // If the callee is a GlobalAddress node (quite common, every direct call is) 1155 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1156 // Likewise ExternalSymbol -> TargetExternalSymbol. 1157 SDValue Callee = CLI.Callee; 1158 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); 1159 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1160 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy()); 1161 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1162 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 1163 1164 // Build the operands for the call instruction itself. 1165 SmallVector<SDValue, 8> Ops; 1166 Ops.push_back(Chain); 1167 Ops.push_back(Callee); 1168 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1169 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1170 RegsToPass[i].second.getValueType())); 1171 1172 // Add a register mask operand representing the call-preserved registers. 1173 const SparcRegisterInfo *TRI = 1174 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); 1175 const uint32_t *Mask = ((hasReturnsTwice) 1176 ? TRI->getRTCallPreservedMask(CLI.CallConv) 1177 : TRI->getCallPreservedMask(CLI.CallConv)); 1178 assert(Mask && "Missing call preserved mask for calling convention"); 1179 Ops.push_back(DAG.getRegisterMask(Mask)); 1180 1181 // Make sure the CopyToReg nodes are glued to the call instruction which 1182 // consumes the registers. 1183 if (InGlue.getNode()) 1184 Ops.push_back(InGlue); 1185 1186 // Now the call itself. 1187 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1188 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size()); 1189 InGlue = Chain.getValue(1); 1190 1191 // Revert the stack pointer immediately after the call. 1192 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1193 DAG.getIntPtrConstant(0, true), InGlue, DL); 1194 InGlue = Chain.getValue(1); 1195 1196 // Now extract the return values. This is more or less the same as 1197 // LowerFormalArguments_64. 1198 1199 // Assign locations to each value returned by this call. 1200 SmallVector<CCValAssign, 16> RVLocs; 1201 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1202 DAG.getTarget(), RVLocs, *DAG.getContext()); 1203 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64); 1204 1205 // Copy all of the result registers out of their specified physreg. 1206 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1207 CCValAssign &VA = RVLocs[i]; 1208 unsigned Reg = toCallerWindow(VA.getLocReg()); 1209 1210 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can 1211 // reside in the same register in the high and low bits. Reuse the 1212 // CopyFromReg previous node to avoid duplicate copies. 1213 SDValue RV; 1214 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1))) 1215 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) 1216 RV = Chain.getValue(0); 1217 1218 // But usually we'll create a new CopyFromReg for a different register. 1219 if (!RV.getNode()) { 1220 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue); 1221 Chain = RV.getValue(1); 1222 InGlue = Chain.getValue(2); 1223 } 1224 1225 // Get the high bits for i32 struct elements. 1226 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 1227 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, 1228 DAG.getConstant(32, MVT::i32)); 1229 1230 // The callee promoted the return value, so insert an Assert?ext SDNode so 1231 // we won't promote the value again in this function. 1232 switch (VA.getLocInfo()) { 1233 case CCValAssign::SExt: 1234 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, 1235 DAG.getValueType(VA.getValVT())); 1236 break; 1237 case CCValAssign::ZExt: 1238 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, 1239 DAG.getValueType(VA.getValVT())); 1240 break; 1241 default: 1242 break; 1243 } 1244 1245 // Truncate the register down to the return value type. 1246 if (VA.isExtInLoc()) 1247 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); 1248 1249 InVals.push_back(RV); 1250 } 1251 1252 return Chain; 1253} 1254 1255//===----------------------------------------------------------------------===// 1256// TargetLowering Implementation 1257//===----------------------------------------------------------------------===// 1258 1259/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 1260/// condition. 1261static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 1262 switch (CC) { 1263 default: llvm_unreachable("Unknown integer condition code!"); 1264 case ISD::SETEQ: return SPCC::ICC_E; 1265 case ISD::SETNE: return SPCC::ICC_NE; 1266 case ISD::SETLT: return SPCC::ICC_L; 1267 case ISD::SETGT: return SPCC::ICC_G; 1268 case ISD::SETLE: return SPCC::ICC_LE; 1269 case ISD::SETGE: return SPCC::ICC_GE; 1270 case ISD::SETULT: return SPCC::ICC_CS; 1271 case ISD::SETULE: return SPCC::ICC_LEU; 1272 case ISD::SETUGT: return SPCC::ICC_GU; 1273 case ISD::SETUGE: return SPCC::ICC_CC; 1274 } 1275} 1276 1277/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 1278/// FCC condition. 1279static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 1280 switch (CC) { 1281 default: llvm_unreachable("Unknown fp condition code!"); 1282 case ISD::SETEQ: 1283 case ISD::SETOEQ: return SPCC::FCC_E; 1284 case ISD::SETNE: 1285 case ISD::SETUNE: return SPCC::FCC_NE; 1286 case ISD::SETLT: 1287 case ISD::SETOLT: return SPCC::FCC_L; 1288 case ISD::SETGT: 1289 case ISD::SETOGT: return SPCC::FCC_G; 1290 case ISD::SETLE: 1291 case ISD::SETOLE: return SPCC::FCC_LE; 1292 case ISD::SETGE: 1293 case ISD::SETOGE: return SPCC::FCC_GE; 1294 case ISD::SETULT: return SPCC::FCC_UL; 1295 case ISD::SETULE: return SPCC::FCC_ULE; 1296 case ISD::SETUGT: return SPCC::FCC_UG; 1297 case ISD::SETUGE: return SPCC::FCC_UGE; 1298 case ISD::SETUO: return SPCC::FCC_U; 1299 case ISD::SETO: return SPCC::FCC_O; 1300 case ISD::SETONE: return SPCC::FCC_LG; 1301 case ISD::SETUEQ: return SPCC::FCC_UE; 1302 } 1303} 1304 1305SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 1306 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 1307 Subtarget = &TM.getSubtarget<SparcSubtarget>(); 1308 1309 // Set up the register classes. 1310 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); 1311 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); 1312 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); 1313 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); 1314 if (Subtarget->is64Bit()) 1315 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); 1316 1317 // Turn FP extload into load/fextend 1318 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1319 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 1320 1321 // Sparc doesn't have i1 sign extending load 1322 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1323 1324 // Turn FP truncstore into trunc + store. 1325 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1326 setTruncStoreAction(MVT::f128, MVT::f32, Expand); 1327 setTruncStoreAction(MVT::f128, MVT::f64, Expand); 1328 1329 // Custom legalize GlobalAddress nodes into LO/HI parts. 1330 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); 1331 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); 1332 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); 1333 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom); 1334 1335 // Sparc doesn't have sext_inreg, replace them with shl/sra 1336 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 1337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 1338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1339 1340 // Sparc has no REM or DIVREM operations. 1341 setOperationAction(ISD::UREM, MVT::i32, Expand); 1342 setOperationAction(ISD::SREM, MVT::i32, Expand); 1343 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1344 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1345 1346 // ... nor does SparcV9. 1347 if (Subtarget->is64Bit()) { 1348 setOperationAction(ISD::UREM, MVT::i64, Expand); 1349 setOperationAction(ISD::SREM, MVT::i64, Expand); 1350 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 1351 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 1352 } 1353 1354 // Custom expand fp<->sint 1355 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 1356 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1357 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 1358 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 1359 1360 // Custom Expand fp<->uint 1361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 1362 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 1363 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 1364 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 1365 1366 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 1367 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 1368 1369 // Sparc has no select or setcc: expand to SELECT_CC. 1370 setOperationAction(ISD::SELECT, MVT::i32, Expand); 1371 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1372 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1373 setOperationAction(ISD::SELECT, MVT::f128, Expand); 1374 1375 setOperationAction(ISD::SETCC, MVT::i32, Expand); 1376 setOperationAction(ISD::SETCC, MVT::f32, Expand); 1377 setOperationAction(ISD::SETCC, MVT::f64, Expand); 1378 setOperationAction(ISD::SETCC, MVT::f128, Expand); 1379 1380 // Sparc doesn't have BRCOND either, it has BR_CC. 1381 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1382 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1383 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1384 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1385 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1386 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 1387 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 1388 1389 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1390 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1391 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1392 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 1393 1394 if (Subtarget->is64Bit()) { 1395 setOperationAction(ISD::ADDC, MVT::i64, Custom); 1396 setOperationAction(ISD::ADDE, MVT::i64, Custom); 1397 setOperationAction(ISD::SUBC, MVT::i64, Custom); 1398 setOperationAction(ISD::SUBE, MVT::i64, Custom); 1399 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 1400 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 1401 setOperationAction(ISD::SELECT, MVT::i64, Expand); 1402 setOperationAction(ISD::SETCC, MVT::i64, Expand); 1403 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 1404 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1405 1406 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 1407 setOperationAction(ISD::CTTZ , MVT::i64, Expand); 1408 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 1409 setOperationAction(ISD::CTLZ , MVT::i64, Expand); 1410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 1411 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 1412 setOperationAction(ISD::ROTL , MVT::i64, Expand); 1413 setOperationAction(ISD::ROTR , MVT::i64, Expand); 1414 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 1415 } 1416 1417 // FIXME: There are instructions available for ATOMIC_FENCE 1418 // on SparcV8 and later. 1419 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 1420 1421 if (!Subtarget->isV9()) { 1422 // SparcV8 does not have FNEGD and FABSD. 1423 setOperationAction(ISD::FNEG, MVT::f64, Custom); 1424 setOperationAction(ISD::FABS, MVT::f64, Custom); 1425 } 1426 1427 setOperationAction(ISD::FSIN , MVT::f128, Expand); 1428 setOperationAction(ISD::FCOS , MVT::f128, Expand); 1429 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); 1430 setOperationAction(ISD::FREM , MVT::f128, Expand); 1431 setOperationAction(ISD::FMA , MVT::f128, Expand); 1432 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1433 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1434 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1435 setOperationAction(ISD::FREM , MVT::f64, Expand); 1436 setOperationAction(ISD::FMA , MVT::f64, Expand); 1437 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1438 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1439 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1440 setOperationAction(ISD::FREM , MVT::f32, Expand); 1441 setOperationAction(ISD::FMA , MVT::f32, Expand); 1442 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 1443 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1444 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1445 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1446 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1447 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1448 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1449 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1450 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); 1451 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1452 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1453 setOperationAction(ISD::FPOW , MVT::f128, Expand); 1454 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1455 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1456 1457 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1458 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1459 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1460 1461 // FIXME: Sparc provides these multiplies, but we don't have them yet. 1462 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1463 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1464 1465 if (Subtarget->is64Bit()) { 1466 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 1467 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 1468 setOperationAction(ISD::MULHU, MVT::i64, Expand); 1469 setOperationAction(ISD::MULHS, MVT::i64, Expand); 1470 } 1471 1472 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1473 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1474 // VAARG needs to be lowered to not do unaligned accesses for doubles. 1475 setOperationAction(ISD::VAARG , MVT::Other, Custom); 1476 1477 // Use the default implementation. 1478 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1479 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1480 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1481 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1482 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1483 1484 setExceptionPointerRegister(SP::I0); 1485 setExceptionSelectorRegister(SP::I1); 1486 1487 setStackPointerRegisterToSaveRestore(SP::O6); 1488 1489 if (Subtarget->isV9()) 1490 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 1491 1492 if (Subtarget->isV9() && Subtarget->hasHardQuad()) { 1493 setOperationAction(ISD::LOAD, MVT::f128, Legal); 1494 setOperationAction(ISD::STORE, MVT::f128, Legal); 1495 } else { 1496 setOperationAction(ISD::LOAD, MVT::f128, Custom); 1497 setOperationAction(ISD::STORE, MVT::f128, Custom); 1498 } 1499 1500 if (Subtarget->hasHardQuad()) { 1501 setOperationAction(ISD::FADD, MVT::f128, Legal); 1502 setOperationAction(ISD::FSUB, MVT::f128, Legal); 1503 setOperationAction(ISD::FMUL, MVT::f128, Legal); 1504 setOperationAction(ISD::FDIV, MVT::f128, Legal); 1505 setOperationAction(ISD::FSQRT, MVT::f128, Legal); 1506 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); 1507 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); 1508 if (Subtarget->isV9()) { 1509 setOperationAction(ISD::FNEG, MVT::f128, Legal); 1510 setOperationAction(ISD::FABS, MVT::f128, Legal); 1511 } else { 1512 setOperationAction(ISD::FNEG, MVT::f128, Custom); 1513 setOperationAction(ISD::FABS, MVT::f128, Custom); 1514 } 1515 1516 if (!Subtarget->is64Bit()) { 1517 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); 1518 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); 1519 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); 1520 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); 1521 } 1522 1523 } else { 1524 // Custom legalize f128 operations. 1525 1526 setOperationAction(ISD::FADD, MVT::f128, Custom); 1527 setOperationAction(ISD::FSUB, MVT::f128, Custom); 1528 setOperationAction(ISD::FMUL, MVT::f128, Custom); 1529 setOperationAction(ISD::FDIV, MVT::f128, Custom); 1530 setOperationAction(ISD::FSQRT, MVT::f128, Custom); 1531 setOperationAction(ISD::FNEG, MVT::f128, Custom); 1532 setOperationAction(ISD::FABS, MVT::f128, Custom); 1533 1534 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); 1535 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); 1536 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); 1537 1538 // Setup Runtime library names. 1539 if (Subtarget->is64Bit()) { 1540 setLibcallName(RTLIB::ADD_F128, "_Qp_add"); 1541 setLibcallName(RTLIB::SUB_F128, "_Qp_sub"); 1542 setLibcallName(RTLIB::MUL_F128, "_Qp_mul"); 1543 setLibcallName(RTLIB::DIV_F128, "_Qp_div"); 1544 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt"); 1545 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi"); 1546 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui"); 1547 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq"); 1548 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq"); 1549 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox"); 1550 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux"); 1551 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq"); 1552 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq"); 1553 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq"); 1554 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq"); 1555 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos"); 1556 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod"); 1557 } else { 1558 setLibcallName(RTLIB::ADD_F128, "_Q_add"); 1559 setLibcallName(RTLIB::SUB_F128, "_Q_sub"); 1560 setLibcallName(RTLIB::MUL_F128, "_Q_mul"); 1561 setLibcallName(RTLIB::DIV_F128, "_Q_div"); 1562 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt"); 1563 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi"); 1564 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou"); 1565 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq"); 1566 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq"); 1567 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); 1568 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); 1569 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); 1570 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); 1571 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq"); 1572 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq"); 1573 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos"); 1574 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod"); 1575 } 1576 } 1577 1578 setMinFunctionAlignment(2); 1579 1580 computeRegisterProperties(); 1581} 1582 1583const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 1584 switch (Opcode) { 1585 default: return 0; 1586 case SPISD::CMPICC: return "SPISD::CMPICC"; 1587 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 1588 case SPISD::BRICC: return "SPISD::BRICC"; 1589 case SPISD::BRXCC: return "SPISD::BRXCC"; 1590 case SPISD::BRFCC: return "SPISD::BRFCC"; 1591 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 1592 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; 1593 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 1594 case SPISD::Hi: return "SPISD::Hi"; 1595 case SPISD::Lo: return "SPISD::Lo"; 1596 case SPISD::FTOI: return "SPISD::FTOI"; 1597 case SPISD::ITOF: return "SPISD::ITOF"; 1598 case SPISD::FTOX: return "SPISD::FTOX"; 1599 case SPISD::XTOF: return "SPISD::XTOF"; 1600 case SPISD::CALL: return "SPISD::CALL"; 1601 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 1602 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 1603 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 1604 case SPISD::TLS_ADD: return "SPISD::TLS_ADD"; 1605 case SPISD::TLS_LD: return "SPISD::TLS_LD"; 1606 case SPISD::TLS_CALL: return "SPISD::TLS_CALL"; 1607 } 1608} 1609 1610EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 1611 if (!VT.isVector()) 1612 return MVT::i32; 1613 return VT.changeVectorElementTypeToInteger(); 1614} 1615 1616/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 1617/// be zero. Op is expected to be a target specific node. Used by DAG 1618/// combiner. 1619void SparcTargetLowering::computeMaskedBitsForTargetNode 1620 (const SDValue Op, 1621 APInt &KnownZero, 1622 APInt &KnownOne, 1623 const SelectionDAG &DAG, 1624 unsigned Depth) const { 1625 APInt KnownZero2, KnownOne2; 1626 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1627 1628 switch (Op.getOpcode()) { 1629 default: break; 1630 case SPISD::SELECT_ICC: 1631 case SPISD::SELECT_XCC: 1632 case SPISD::SELECT_FCC: 1633 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); 1634 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); 1635 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1636 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1637 1638 // Only known if known in both the LHS and RHS. 1639 KnownOne &= KnownOne2; 1640 KnownZero &= KnownZero2; 1641 break; 1642 } 1643} 1644 1645// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 1646// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 1647static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 1648 ISD::CondCode CC, unsigned &SPCC) { 1649 if (isa<ConstantSDNode>(RHS) && 1650 cast<ConstantSDNode>(RHS)->isNullValue() && 1651 CC == ISD::SETNE && 1652 (((LHS.getOpcode() == SPISD::SELECT_ICC || 1653 LHS.getOpcode() == SPISD::SELECT_XCC) && 1654 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 1655 (LHS.getOpcode() == SPISD::SELECT_FCC && 1656 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 1657 isa<ConstantSDNode>(LHS.getOperand(0)) && 1658 isa<ConstantSDNode>(LHS.getOperand(1)) && 1659 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 1660 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 1661 SDValue CMPCC = LHS.getOperand(3); 1662 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 1663 LHS = CMPCC.getOperand(0); 1664 RHS = CMPCC.getOperand(1); 1665 } 1666} 1667 1668// Convert to a target node and set target flags. 1669SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, 1670 SelectionDAG &DAG) const { 1671 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) 1672 return DAG.getTargetGlobalAddress(GA->getGlobal(), 1673 SDLoc(GA), 1674 GA->getValueType(0), 1675 GA->getOffset(), TF); 1676 1677 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) 1678 return DAG.getTargetConstantPool(CP->getConstVal(), 1679 CP->getValueType(0), 1680 CP->getAlignment(), 1681 CP->getOffset(), TF); 1682 1683 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) 1684 return DAG.getTargetBlockAddress(BA->getBlockAddress(), 1685 Op.getValueType(), 1686 0, 1687 TF); 1688 1689 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) 1690 return DAG.getTargetExternalSymbol(ES->getSymbol(), 1691 ES->getValueType(0), TF); 1692 1693 llvm_unreachable("Unhandled address SDNode"); 1694} 1695 1696// Split Op into high and low parts according to HiTF and LoTF. 1697// Return an ADD node combining the parts. 1698SDValue SparcTargetLowering::makeHiLoPair(SDValue Op, 1699 unsigned HiTF, unsigned LoTF, 1700 SelectionDAG &DAG) const { 1701 SDLoc DL(Op); 1702 EVT VT = Op.getValueType(); 1703 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG)); 1704 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); 1705 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1706} 1707 1708// Build SDNodes for producing an address from a GlobalAddress, ConstantPool, 1709// or ExternalSymbol SDNode. 1710SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { 1711 SDLoc DL(Op); 1712 EVT VT = getPointerTy(); 1713 1714 // Handle PIC mode first. 1715 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1716 // This is the pic32 code model, the GOT is known to be smaller than 4GB. 1717 SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1718 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT); 1719 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo); 1720 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this 1721 // function has calls. 1722 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1723 MFI->setHasCalls(true); 1724 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr, 1725 MachinePointerInfo::getGOT(), false, false, false, 0); 1726 } 1727 1728 // This is one of the absolute code models. 1729 switch(getTargetMachine().getCodeModel()) { 1730 default: 1731 llvm_unreachable("Unsupported absolute code model"); 1732 case CodeModel::JITDefault: 1733 case CodeModel::Small: 1734 // abs32. 1735 return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1736 case CodeModel::Medium: { 1737 // abs44. 1738 SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG); 1739 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); 1740 SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG); 1741 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); 1742 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); 1743 } 1744 case CodeModel::Large: { 1745 // abs64. 1746 SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG); 1747 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); 1748 SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1749 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1750 } 1751 } 1752} 1753 1754SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 1755 SelectionDAG &DAG) const { 1756 return makeAddress(Op, DAG); 1757} 1758 1759SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 1760 SelectionDAG &DAG) const { 1761 return makeAddress(Op, DAG); 1762} 1763 1764SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op, 1765 SelectionDAG &DAG) const { 1766 return makeAddress(Op, DAG); 1767} 1768 1769SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1770 SelectionDAG &DAG) const { 1771 1772 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1773 SDLoc DL(GA); 1774 const GlobalValue *GV = GA->getGlobal(); 1775 EVT PtrVT = getPointerTy(); 1776 1777 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1778 1779 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1780 unsigned HiTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_HI22 1781 : SPII::MO_TLS_LDM_HI22); 1782 unsigned LoTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_LO10 1783 : SPII::MO_TLS_LDM_LO10); 1784 unsigned addTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_ADD 1785 : SPII::MO_TLS_LDM_ADD); 1786 unsigned callTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_CALL 1787 : SPII::MO_TLS_LDM_CALL); 1788 1789 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG); 1790 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); 1791 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo, 1792 withTargetFlags(Op, addTF, DAG)); 1793 1794 SDValue Chain = DAG.getEntryNode(); 1795 SDValue InFlag; 1796 1797 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL); 1798 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); 1799 InFlag = Chain.getValue(1); 1800 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT); 1801 SDValue Symbol = withTargetFlags(Op, callTF, DAG); 1802 1803 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1804 SmallVector<SDValue, 4> Ops; 1805 Ops.push_back(Chain); 1806 Ops.push_back(Callee); 1807 Ops.push_back(Symbol); 1808 Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); 1809 const uint32_t *Mask = getTargetMachine() 1810 .getRegisterInfo()->getCallPreservedMask(CallingConv::C); 1811 assert(Mask && "Missing call preserved mask for calling convention"); 1812 Ops.push_back(DAG.getRegisterMask(Mask)); 1813 Ops.push_back(InFlag); 1814 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, &Ops[0], Ops.size()); 1815 InFlag = Chain.getValue(1); 1816 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true), 1817 DAG.getIntPtrConstant(0, true), InFlag, DL); 1818 InFlag = Chain.getValue(1); 1819 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); 1820 1821 if (model != TLSModel::LocalDynamic) 1822 return Ret; 1823 1824 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, 1825 withTargetFlags(Op, SPII::MO_TLS_LDO_HIX22, DAG)); 1826 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, 1827 withTargetFlags(Op, SPII::MO_TLS_LDO_LOX10, DAG)); 1828 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); 1829 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo, 1830 withTargetFlags(Op, SPII::MO_TLS_LDO_ADD, DAG)); 1831 } 1832 1833 if (model == TLSModel::InitialExec) { 1834 unsigned ldTF = ((PtrVT == MVT::i64)? SPII::MO_TLS_IE_LDX 1835 : SPII::MO_TLS_IE_LD); 1836 1837 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); 1838 1839 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this 1840 // function has calls. 1841 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1842 MFI->setHasCalls(true); 1843 1844 SDValue TGA = makeHiLoPair(Op, 1845 SPII::MO_TLS_IE_HI22, SPII::MO_TLS_IE_LO10, DAG); 1846 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); 1847 SDValue Offset = DAG.getNode(SPISD::TLS_LD, 1848 DL, PtrVT, Ptr, 1849 withTargetFlags(Op, ldTF, DAG)); 1850 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, 1851 DAG.getRegister(SP::G7, PtrVT), Offset, 1852 withTargetFlags(Op, SPII::MO_TLS_IE_ADD, DAG)); 1853 } 1854 1855 assert(model == TLSModel::LocalExec); 1856 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, 1857 withTargetFlags(Op, SPII::MO_TLS_LE_HIX22, DAG)); 1858 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, 1859 withTargetFlags(Op, SPII::MO_TLS_LE_LOX10, DAG)); 1860 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); 1861 1862 return DAG.getNode(ISD::ADD, DL, PtrVT, 1863 DAG.getRegister(SP::G7, PtrVT), Offset); 1864} 1865 1866SDValue 1867SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, 1868 SDValue Arg, SDLoc DL, 1869 SelectionDAG &DAG) const { 1870 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1871 EVT ArgVT = Arg.getValueType(); 1872 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1873 1874 ArgListEntry Entry; 1875 Entry.Node = Arg; 1876 Entry.Ty = ArgTy; 1877 1878 if (ArgTy->isFP128Ty()) { 1879 // Create a stack object and pass the pointer to the library function. 1880 int FI = MFI->CreateStackObject(16, 8, false); 1881 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 1882 Chain = DAG.getStore(Chain, 1883 DL, 1884 Entry.Node, 1885 FIPtr, 1886 MachinePointerInfo(), 1887 false, 1888 false, 1889 8); 1890 1891 Entry.Node = FIPtr; 1892 Entry.Ty = PointerType::getUnqual(ArgTy); 1893 } 1894 Args.push_back(Entry); 1895 return Chain; 1896} 1897 1898SDValue 1899SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG, 1900 const char *LibFuncName, 1901 unsigned numArgs) const { 1902 1903 ArgListTy Args; 1904 1905 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1906 1907 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy()); 1908 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext()); 1909 Type *RetTyABI = RetTy; 1910 SDValue Chain = DAG.getEntryNode(); 1911 SDValue RetPtr; 1912 1913 if (RetTy->isFP128Ty()) { 1914 // Create a Stack Object to receive the return value of type f128. 1915 ArgListEntry Entry; 1916 int RetFI = MFI->CreateStackObject(16, 8, false); 1917 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy()); 1918 Entry.Node = RetPtr; 1919 Entry.Ty = PointerType::getUnqual(RetTy); 1920 if (!Subtarget->is64Bit()) 1921 Entry.isSRet = true; 1922 Entry.isReturned = false; 1923 Args.push_back(Entry); 1924 RetTyABI = Type::getVoidTy(*DAG.getContext()); 1925 } 1926 1927 assert(Op->getNumOperands() >= numArgs && "Not enough operands!"); 1928 for (unsigned i = 0, e = numArgs; i != e; ++i) { 1929 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG); 1930 } 1931 TargetLowering:: 1932 CallLoweringInfo CLI(Chain, 1933 RetTyABI, 1934 false, false, false, false, 1935 0, CallingConv::C, 1936 false, false, true, 1937 Callee, Args, DAG, SDLoc(Op)); 1938 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 1939 1940 // chain is in second result. 1941 if (RetTyABI == RetTy) 1942 return CallInfo.first; 1943 1944 assert (RetTy->isFP128Ty() && "Unexpected return type!"); 1945 1946 Chain = CallInfo.second; 1947 1948 // Load RetPtr to get the return value. 1949 return DAG.getLoad(Op.getValueType(), 1950 SDLoc(Op), 1951 Chain, 1952 RetPtr, 1953 MachinePointerInfo(), 1954 false, false, false, 8); 1955} 1956 1957SDValue 1958SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, 1959 unsigned &SPCC, 1960 SDLoc DL, 1961 SelectionDAG &DAG) const { 1962 1963 const char *LibCall = 0; 1964 bool is64Bit = Subtarget->is64Bit(); 1965 switch(SPCC) { 1966 default: llvm_unreachable("Unhandled conditional code!"); 1967 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break; 1968 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break; 1969 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break; 1970 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break; 1971 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break; 1972 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break; 1973 case SPCC::FCC_UL : 1974 case SPCC::FCC_ULE: 1975 case SPCC::FCC_UG : 1976 case SPCC::FCC_UGE: 1977 case SPCC::FCC_U : 1978 case SPCC::FCC_O : 1979 case SPCC::FCC_LG : 1980 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break; 1981 } 1982 1983 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy()); 1984 Type *RetTy = Type::getInt32Ty(*DAG.getContext()); 1985 ArgListTy Args; 1986 SDValue Chain = DAG.getEntryNode(); 1987 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG); 1988 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG); 1989 1990 TargetLowering:: 1991 CallLoweringInfo CLI(Chain, 1992 RetTy, 1993 false, false, false, false, 1994 0, CallingConv::C, 1995 false, false, true, 1996 Callee, Args, DAG, DL); 1997 1998 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 1999 2000 // result is in first, and chain is in second result. 2001 SDValue Result = CallInfo.first; 2002 2003 switch(SPCC) { 2004 default: { 2005 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2006 SPCC = SPCC::ICC_NE; 2007 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2008 } 2009 case SPCC::FCC_UL : { 2010 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType()); 2011 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2012 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2013 SPCC = SPCC::ICC_NE; 2014 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2015 } 2016 case SPCC::FCC_ULE: { 2017 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType()); 2018 SPCC = SPCC::ICC_NE; 2019 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2020 } 2021 case SPCC::FCC_UG : { 2022 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); 2023 SPCC = SPCC::ICC_G; 2024 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2025 } 2026 case SPCC::FCC_UGE: { 2027 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); 2028 SPCC = SPCC::ICC_NE; 2029 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2030 } 2031 2032 case SPCC::FCC_U : { 2033 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); 2034 SPCC = SPCC::ICC_E; 2035 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2036 } 2037 case SPCC::FCC_O : { 2038 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); 2039 SPCC = SPCC::ICC_NE; 2040 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2041 } 2042 case SPCC::FCC_LG : { 2043 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); 2044 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2045 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2046 SPCC = SPCC::ICC_NE; 2047 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2048 } 2049 case SPCC::FCC_UE : { 2050 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); 2051 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2052 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2053 SPCC = SPCC::ICC_E; 2054 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2055 } 2056 } 2057} 2058 2059static SDValue 2060LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, 2061 const SparcTargetLowering &TLI) { 2062 2063 if (Op.getOperand(0).getValueType() == MVT::f64) 2064 return TLI.LowerF128Op(Op, DAG, 2065 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1); 2066 2067 if (Op.getOperand(0).getValueType() == MVT::f32) 2068 return TLI.LowerF128Op(Op, DAG, 2069 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1); 2070 2071 llvm_unreachable("fpextend with non-float operand!"); 2072 return SDValue(0, 0); 2073} 2074 2075static SDValue 2076LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, 2077 const SparcTargetLowering &TLI) { 2078 // FP_ROUND on f64 and f32 are legal. 2079 if (Op.getOperand(0).getValueType() != MVT::f128) 2080 return Op; 2081 2082 if (Op.getValueType() == MVT::f64) 2083 return TLI.LowerF128Op(Op, DAG, 2084 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1); 2085 if (Op.getValueType() == MVT::f32) 2086 return TLI.LowerF128Op(Op, DAG, 2087 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1); 2088 2089 llvm_unreachable("fpround to non-float!"); 2090 return SDValue(0, 0); 2091} 2092 2093static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, 2094 const SparcTargetLowering &TLI, 2095 bool hasHardQuad) { 2096 SDLoc dl(Op); 2097 EVT VT = Op.getValueType(); 2098 assert(VT == MVT::i32 || VT == MVT::i64); 2099 2100 // Expand f128 operations to fp128 abi calls. 2101 if (Op.getOperand(0).getValueType() == MVT::f128 2102 && (!hasHardQuad || !TLI.isTypeLegal(VT))) { 2103 const char *libName = TLI.getLibcallName(VT == MVT::i32 2104 ? RTLIB::FPTOSINT_F128_I32 2105 : RTLIB::FPTOSINT_F128_I64); 2106 return TLI.LowerF128Op(Op, DAG, libName, 1); 2107 } 2108 2109 // Expand if the resulting type is illegal. 2110 if (!TLI.isTypeLegal(VT)) 2111 return SDValue(0, 0); 2112 2113 // Otherwise, Convert the fp value to integer in an FP register. 2114 if (VT == MVT::i32) 2115 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 2116 else 2117 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0)); 2118 2119 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 2120} 2121 2122static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, 2123 const SparcTargetLowering &TLI, 2124 bool hasHardQuad) { 2125 SDLoc dl(Op); 2126 EVT OpVT = Op.getOperand(0).getValueType(); 2127 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); 2128 2129 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; 2130 2131 // Expand f128 operations to fp128 ABI calls. 2132 if (Op.getValueType() == MVT::f128 2133 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { 2134 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 2135 ? RTLIB::SINTTOFP_I32_F128 2136 : RTLIB::SINTTOFP_I64_F128); 2137 return TLI.LowerF128Op(Op, DAG, libName, 1); 2138 } 2139 2140 // Expand if the operand type is illegal. 2141 if (!TLI.isTypeLegal(OpVT)) 2142 return SDValue(0, 0); 2143 2144 // Otherwise, Convert the int value to FP in an FP register. 2145 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); 2146 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; 2147 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp); 2148} 2149 2150static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, 2151 const SparcTargetLowering &TLI, 2152 bool hasHardQuad) { 2153 SDLoc dl(Op); 2154 EVT VT = Op.getValueType(); 2155 2156 // Expand if it does not involve f128 or the target has support for 2157 // quad floating point instructions and the resulting type is legal. 2158 if (Op.getOperand(0).getValueType() != MVT::f128 || 2159 (hasHardQuad && TLI.isTypeLegal(VT))) 2160 return SDValue(0, 0); 2161 2162 assert(VT == MVT::i32 || VT == MVT::i64); 2163 2164 return TLI.LowerF128Op(Op, DAG, 2165 TLI.getLibcallName(VT == MVT::i32 2166 ? RTLIB::FPTOUINT_F128_I32 2167 : RTLIB::FPTOUINT_F128_I64), 2168 1); 2169} 2170 2171static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, 2172 const SparcTargetLowering &TLI, 2173 bool hasHardQuad) { 2174 SDLoc dl(Op); 2175 EVT OpVT = Op.getOperand(0).getValueType(); 2176 assert(OpVT == MVT::i32 || OpVT == MVT::i64); 2177 2178 // Expand if it does not involve f128 or the target has support for 2179 // quad floating point instructions and the operand type is legal. 2180 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) 2181 return SDValue(0, 0); 2182 2183 return TLI.LowerF128Op(Op, DAG, 2184 TLI.getLibcallName(OpVT == MVT::i32 2185 ? RTLIB::UINTTOFP_I32_F128 2186 : RTLIB::UINTTOFP_I64_F128), 2187 1); 2188} 2189 2190static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 2191 const SparcTargetLowering &TLI, 2192 bool hasHardQuad) { 2193 SDValue Chain = Op.getOperand(0); 2194 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2195 SDValue LHS = Op.getOperand(2); 2196 SDValue RHS = Op.getOperand(3); 2197 SDValue Dest = Op.getOperand(4); 2198 SDLoc dl(Op); 2199 unsigned Opc, SPCC = ~0U; 2200 2201 // If this is a br_cc of a "setcc", and if the setcc got lowered into 2202 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 2203 LookThroughSetCC(LHS, RHS, CC, SPCC); 2204 2205 // Get the condition flag. 2206 SDValue CompareFlag; 2207 if (LHS.getValueType().isInteger()) { 2208 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); 2209 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 2210 // 32-bit compares use the icc flags, 64-bit uses the xcc flags. 2211 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; 2212 } else { 2213 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { 2214 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2215 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); 2216 Opc = SPISD::BRICC; 2217 } else { 2218 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 2219 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2220 Opc = SPISD::BRFCC; 2221 } 2222 } 2223 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 2224 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 2225} 2226 2227static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 2228 const SparcTargetLowering &TLI, 2229 bool hasHardQuad) { 2230 SDValue LHS = Op.getOperand(0); 2231 SDValue RHS = Op.getOperand(1); 2232 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2233 SDValue TrueVal = Op.getOperand(2); 2234 SDValue FalseVal = Op.getOperand(3); 2235 SDLoc dl(Op); 2236 unsigned Opc, SPCC = ~0U; 2237 2238 // If this is a select_cc of a "setcc", and if the setcc got lowered into 2239 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 2240 LookThroughSetCC(LHS, RHS, CC, SPCC); 2241 2242 SDValue CompareFlag; 2243 if (LHS.getValueType().isInteger()) { 2244 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); 2245 Opc = LHS.getValueType() == MVT::i32 ? 2246 SPISD::SELECT_ICC : SPISD::SELECT_XCC; 2247 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 2248 } else { 2249 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { 2250 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2251 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); 2252 Opc = SPISD::SELECT_ICC; 2253 } else { 2254 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 2255 Opc = SPISD::SELECT_FCC; 2256 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2257 } 2258 } 2259 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 2260 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 2261} 2262 2263static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 2264 const SparcTargetLowering &TLI) { 2265 MachineFunction &MF = DAG.getMachineFunction(); 2266 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 2267 2268 // Need frame address to find the address of VarArgsFrameIndex. 2269 MF.getFrameInfo()->setFrameAddressIsTaken(true); 2270 2271 // vastart just stores the address of the VarArgsFrameIndex slot into the 2272 // memory location argument. 2273 SDLoc DL(Op); 2274 SDValue Offset = 2275 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), 2276 DAG.getRegister(SP::I6, TLI.getPointerTy()), 2277 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset())); 2278 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2279 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), 2280 MachinePointerInfo(SV), false, false, 0); 2281} 2282 2283static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 2284 SDNode *Node = Op.getNode(); 2285 EVT VT = Node->getValueType(0); 2286 SDValue InChain = Node->getOperand(0); 2287 SDValue VAListPtr = Node->getOperand(1); 2288 EVT PtrVT = VAListPtr.getValueType(); 2289 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2290 SDLoc DL(Node); 2291 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr, 2292 MachinePointerInfo(SV), false, false, false, 0); 2293 // Increment the pointer, VAList, to the next vaarg. 2294 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, 2295 DAG.getIntPtrConstant(VT.getSizeInBits()/8)); 2296 // Store the incremented VAList to the legalized pointer. 2297 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, 2298 VAListPtr, MachinePointerInfo(SV), false, false, 0); 2299 // Load the actual argument out of the pointer VAList. 2300 // We can't count on greater alignment than the word size. 2301 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(), 2302 false, false, false, 2303 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8); 2304} 2305 2306static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 2307 const SparcSubtarget *Subtarget) { 2308 SDValue Chain = Op.getOperand(0); // Legalize the chain. 2309 SDValue Size = Op.getOperand(1); // Legalize the size. 2310 EVT VT = Size->getValueType(0); 2311 SDLoc dl(Op); 2312 2313 unsigned SPReg = SP::O6; 2314 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 2315 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 2316 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 2317 2318 // The resultant pointer is actually 16 words from the bottom of the stack, 2319 // to provide a register spill area. 2320 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96; 2321 regSpillArea += Subtarget->getStackPointerBias(); 2322 2323 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, 2324 DAG.getConstant(regSpillArea, VT)); 2325 SDValue Ops[2] = { NewVal, Chain }; 2326 return DAG.getMergeValues(Ops, 2, dl); 2327} 2328 2329 2330static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 2331 SDLoc dl(Op); 2332 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 2333 dl, MVT::Other, DAG.getEntryNode()); 2334 return Chain; 2335} 2336 2337static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 2338 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2339 MFI->setFrameAddressIsTaken(true); 2340 2341 EVT VT = Op.getValueType(); 2342 SDLoc dl(Op); 2343 unsigned FrameReg = SP::I6; 2344 2345 uint64_t depth = Op.getConstantOperandVal(0); 2346 2347 SDValue FrameAddr; 2348 if (depth == 0) 2349 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 2350 else { 2351 // flush first to make sure the windowed registers' values are in stack 2352 SDValue Chain = getFLUSHW(Op, DAG); 2353 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 2354 2355 for (uint64_t i = 0; i != depth; ++i) { 2356 SDValue Ptr = DAG.getNode(ISD::ADD, 2357 dl, MVT::i32, 2358 FrameAddr, DAG.getIntPtrConstant(56)); 2359 FrameAddr = DAG.getLoad(MVT::i32, dl, 2360 Chain, 2361 Ptr, 2362 MachinePointerInfo(), false, false, false, 0); 2363 } 2364 } 2365 return FrameAddr; 2366} 2367 2368static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, 2369 const SparcTargetLowering &TLI) { 2370 MachineFunction &MF = DAG.getMachineFunction(); 2371 MachineFrameInfo *MFI = MF.getFrameInfo(); 2372 MFI->setReturnAddressIsTaken(true); 2373 2374 EVT VT = Op.getValueType(); 2375 SDLoc dl(Op); 2376 uint64_t depth = Op.getConstantOperandVal(0); 2377 2378 SDValue RetAddr; 2379 if (depth == 0) { 2380 unsigned RetReg = MF.addLiveIn(SP::I7, 2381 TLI.getRegClassFor(TLI.getPointerTy())); 2382 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 2383 } else { 2384 // Need frame address to find return address of the caller. 2385 MFI->setFrameAddressIsTaken(true); 2386 2387 // flush first to make sure the windowed registers' values are in stack 2388 SDValue Chain = getFLUSHW(Op, DAG); 2389 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 2390 2391 for (uint64_t i = 0; i != depth; ++i) { 2392 SDValue Ptr = DAG.getNode(ISD::ADD, 2393 dl, MVT::i32, 2394 RetAddr, 2395 DAG.getIntPtrConstant((i == depth-1)?60:56)); 2396 RetAddr = DAG.getLoad(MVT::i32, dl, 2397 Chain, 2398 Ptr, 2399 MachinePointerInfo(), false, false, false, 0); 2400 } 2401 } 2402 return RetAddr; 2403} 2404 2405static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) 2406{ 2407 SDLoc dl(Op); 2408 2409 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); 2410 assert(opcode == ISD::FNEG || opcode == ISD::FABS); 2411 2412 // Lower fneg/fabs on f64 to fneg/fabs on f32. 2413 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd. 2414 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd. 2415 2416 SDValue SrcReg64 = Op.getOperand(0); 2417 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, 2418 SrcReg64); 2419 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, 2420 SrcReg64); 2421 2422 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); 2423 2424 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2425 dl, MVT::f64), 0); 2426 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, 2427 DstReg64, Hi32); 2428 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, 2429 DstReg64, Lo32); 2430 return DstReg64; 2431} 2432 2433// Lower a f128 load into two f64 loads. 2434static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) 2435{ 2436 SDLoc dl(Op); 2437 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode()); 2438 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF 2439 && "Unexpected node type"); 2440 2441 unsigned alignment = LdNode->getAlignment(); 2442 if (alignment > 8) 2443 alignment = 8; 2444 2445 SDValue Hi64 = DAG.getLoad(MVT::f64, 2446 dl, 2447 LdNode->getChain(), 2448 LdNode->getBasePtr(), 2449 LdNode->getPointerInfo(), 2450 false, false, false, alignment); 2451 EVT addrVT = LdNode->getBasePtr().getValueType(); 2452 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, 2453 LdNode->getBasePtr(), 2454 DAG.getConstant(8, addrVT)); 2455 SDValue Lo64 = DAG.getLoad(MVT::f64, 2456 dl, 2457 LdNode->getChain(), 2458 LoPtr, 2459 LdNode->getPointerInfo(), 2460 false, false, false, alignment); 2461 2462 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); 2463 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); 2464 2465 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2466 dl, MVT::f128); 2467 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 2468 MVT::f128, 2469 SDValue(InFP128, 0), 2470 Hi64, 2471 SubRegEven); 2472 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 2473 MVT::f128, 2474 SDValue(InFP128, 0), 2475 Lo64, 2476 SubRegOdd); 2477 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1), 2478 SDValue(Lo64.getNode(), 1) }; 2479 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2480 &OutChains[0], 2); 2481 SDValue Ops[2] = {SDValue(InFP128,0), OutChain}; 2482 return DAG.getMergeValues(Ops, 2, dl); 2483} 2484 2485// Lower a f128 store into two f64 stores. 2486static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { 2487 SDLoc dl(Op); 2488 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode()); 2489 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF 2490 && "Unexpected node type"); 2491 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); 2492 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); 2493 2494 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, 2495 dl, 2496 MVT::f64, 2497 StNode->getValue(), 2498 SubRegEven); 2499 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, 2500 dl, 2501 MVT::f64, 2502 StNode->getValue(), 2503 SubRegOdd); 2504 2505 unsigned alignment = StNode->getAlignment(); 2506 if (alignment > 8) 2507 alignment = 8; 2508 2509 SDValue OutChains[2]; 2510 OutChains[0] = DAG.getStore(StNode->getChain(), 2511 dl, 2512 SDValue(Hi64, 0), 2513 StNode->getBasePtr(), 2514 MachinePointerInfo(), 2515 false, false, alignment); 2516 EVT addrVT = StNode->getBasePtr().getValueType(); 2517 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, 2518 StNode->getBasePtr(), 2519 DAG.getConstant(8, addrVT)); 2520 OutChains[1] = DAG.getStore(StNode->getChain(), 2521 dl, 2522 SDValue(Lo64, 0), 2523 LoPtr, 2524 MachinePointerInfo(), 2525 false, false, alignment); 2526 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2527 &OutChains[0], 2); 2528} 2529 2530static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG, 2531 const SparcTargetLowering &TLI, 2532 bool is64Bit) { 2533 if (Op.getValueType() == MVT::f64) 2534 return LowerF64Op(Op, DAG, ISD::FNEG); 2535 if (Op.getValueType() == MVT::f128) 2536 return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1); 2537 return Op; 2538} 2539 2540static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { 2541 if (Op.getValueType() == MVT::f64) 2542 return LowerF64Op(Op, DAG, ISD::FABS); 2543 if (Op.getValueType() != MVT::f128) 2544 return Op; 2545 2546 // Lower fabs on f128 to fabs on f64 2547 // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64 2548 2549 SDLoc dl(Op); 2550 SDValue SrcReg128 = Op.getOperand(0); 2551 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, 2552 SrcReg128); 2553 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, 2554 SrcReg128); 2555 if (isV9) 2556 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); 2557 else 2558 Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS); 2559 2560 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2561 dl, MVT::f128), 0); 2562 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, 2563 DstReg128, Hi64); 2564 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, 2565 DstReg128, Lo64); 2566 return DstReg128; 2567} 2568 2569static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 2570 2571 if (Op.getValueType() != MVT::i64) 2572 return Op; 2573 2574 SDLoc dl(Op); 2575 SDValue Src1 = Op.getOperand(0); 2576 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); 2577 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, 2578 DAG.getConstant(32, MVT::i64)); 2579 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); 2580 2581 SDValue Src2 = Op.getOperand(1); 2582 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); 2583 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, 2584 DAG.getConstant(32, MVT::i64)); 2585 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); 2586 2587 2588 bool hasChain = false; 2589 unsigned hiOpc = Op.getOpcode(); 2590 switch (Op.getOpcode()) { 2591 default: llvm_unreachable("Invalid opcode"); 2592 case ISD::ADDC: hiOpc = ISD::ADDE; break; 2593 case ISD::ADDE: hasChain = true; break; 2594 case ISD::SUBC: hiOpc = ISD::SUBE; break; 2595 case ISD::SUBE: hasChain = true; break; 2596 } 2597 SDValue Lo; 2598 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue); 2599 if (hasChain) { 2600 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo, 2601 Op.getOperand(2)); 2602 } else { 2603 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo); 2604 } 2605 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1)); 2606 SDValue Carry = Hi.getValue(1); 2607 2608 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); 2609 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); 2610 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, 2611 DAG.getConstant(32, MVT::i64)); 2612 2613 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); 2614 SDValue Ops[2] = { Dst, Carry }; 2615 return DAG.getMergeValues(Ops, 2, dl); 2616} 2617 2618SDValue SparcTargetLowering:: 2619LowerOperation(SDValue Op, SelectionDAG &DAG) const { 2620 2621 bool hasHardQuad = Subtarget->hasHardQuad(); 2622 bool is64Bit = Subtarget->is64Bit(); 2623 bool isV9 = Subtarget->isV9(); 2624 2625 switch (Op.getOpcode()) { 2626 default: llvm_unreachable("Should not custom lower this!"); 2627 2628 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this); 2629 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 2630 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2631 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2632 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 2633 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2634 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, 2635 hasHardQuad); 2636 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, 2637 hasHardQuad); 2638 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, 2639 hasHardQuad); 2640 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, 2641 hasHardQuad); 2642 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, 2643 hasHardQuad); 2644 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, 2645 hasHardQuad); 2646 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 2647 case ISD::VAARG: return LowerVAARG(Op, DAG); 2648 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, 2649 Subtarget); 2650 2651 case ISD::LOAD: return LowerF128Load(Op, DAG); 2652 case ISD::STORE: return LowerF128Store(Op, DAG); 2653 case ISD::FADD: return LowerF128Op(Op, DAG, 2654 getLibcallName(RTLIB::ADD_F128), 2); 2655 case ISD::FSUB: return LowerF128Op(Op, DAG, 2656 getLibcallName(RTLIB::SUB_F128), 2); 2657 case ISD::FMUL: return LowerF128Op(Op, DAG, 2658 getLibcallName(RTLIB::MUL_F128), 2); 2659 case ISD::FDIV: return LowerF128Op(Op, DAG, 2660 getLibcallName(RTLIB::DIV_F128), 2); 2661 case ISD::FSQRT: return LowerF128Op(Op, DAG, 2662 getLibcallName(RTLIB::SQRT_F128),1); 2663 case ISD::FNEG: return LowerFNEG(Op, DAG, *this, is64Bit); 2664 case ISD::FABS: return LowerFABS(Op, DAG, isV9); 2665 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); 2666 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); 2667 case ISD::ADDC: 2668 case ISD::ADDE: 2669 case ISD::SUBC: 2670 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 2671 } 2672} 2673 2674MachineBasicBlock * 2675SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 2676 MachineBasicBlock *BB) const { 2677 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 2678 unsigned BROpcode; 2679 unsigned CC; 2680 DebugLoc dl = MI->getDebugLoc(); 2681 // Figure out the conditional branch opcode to use for this select_cc. 2682 switch (MI->getOpcode()) { 2683 default: llvm_unreachable("Unknown SELECT_CC!"); 2684 case SP::SELECT_CC_Int_ICC: 2685 case SP::SELECT_CC_FP_ICC: 2686 case SP::SELECT_CC_DFP_ICC: 2687 case SP::SELECT_CC_QFP_ICC: 2688 BROpcode = SP::BCOND; 2689 break; 2690 case SP::SELECT_CC_Int_FCC: 2691 case SP::SELECT_CC_FP_FCC: 2692 case SP::SELECT_CC_DFP_FCC: 2693 case SP::SELECT_CC_QFP_FCC: 2694 BROpcode = SP::FBCOND; 2695 break; 2696 } 2697 2698 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 2699 2700 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2701 // control-flow pattern. The incoming instruction knows the destination vreg 2702 // to set, the condition code register to branch on, the true/false values to 2703 // select between, and a branch opcode to use. 2704 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2705 MachineFunction::iterator It = BB; 2706 ++It; 2707 2708 // thisMBB: 2709 // ... 2710 // TrueVal = ... 2711 // [f]bCC copy1MBB 2712 // fallthrough --> copy0MBB 2713 MachineBasicBlock *thisMBB = BB; 2714 MachineFunction *F = BB->getParent(); 2715 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 2716 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 2717 F->insert(It, copy0MBB); 2718 F->insert(It, sinkMBB); 2719 2720 // Transfer the remainder of BB and its successor edges to sinkMBB. 2721 sinkMBB->splice(sinkMBB->begin(), BB, 2722 llvm::next(MachineBasicBlock::iterator(MI)), 2723 BB->end()); 2724 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 2725 2726 // Add the true and fallthrough blocks as its successors. 2727 BB->addSuccessor(copy0MBB); 2728 BB->addSuccessor(sinkMBB); 2729 2730 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 2731 2732 // copy0MBB: 2733 // %FalseValue = ... 2734 // # fallthrough to sinkMBB 2735 BB = copy0MBB; 2736 2737 // Update machine-CFG edges 2738 BB->addSuccessor(sinkMBB); 2739 2740 // sinkMBB: 2741 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2742 // ... 2743 BB = sinkMBB; 2744 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 2745 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 2746 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 2747 2748 MI->eraseFromParent(); // The pseudo instruction is gone now. 2749 return BB; 2750} 2751 2752//===----------------------------------------------------------------------===// 2753// Sparc Inline Assembly Support 2754//===----------------------------------------------------------------------===// 2755 2756/// getConstraintType - Given a constraint letter, return the type of 2757/// constraint it is for this target. 2758SparcTargetLowering::ConstraintType 2759SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 2760 if (Constraint.size() == 1) { 2761 switch (Constraint[0]) { 2762 default: break; 2763 case 'r': return C_RegisterClass; 2764 } 2765 } 2766 2767 return TargetLowering::getConstraintType(Constraint); 2768} 2769 2770std::pair<unsigned, const TargetRegisterClass*> 2771SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 2772 MVT VT) const { 2773 if (Constraint.size() == 1) { 2774 switch (Constraint[0]) { 2775 case 'r': 2776 return std::make_pair(0U, &SP::IntRegsRegClass); 2777 } 2778 } 2779 2780 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2781} 2782 2783bool 2784SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2785 // The Sparc target isn't yet aware of offsets. 2786 return false; 2787} 2788 2789void SparcTargetLowering::ReplaceNodeResults(SDNode *N, 2790 SmallVectorImpl<SDValue>& Results, 2791 SelectionDAG &DAG) const { 2792 2793 SDLoc dl(N); 2794 2795 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL; 2796 2797 switch (N->getOpcode()) { 2798 default: 2799 llvm_unreachable("Do not know how to custom type legalize this operation!"); 2800 2801 case ISD::FP_TO_SINT: 2802 case ISD::FP_TO_UINT: 2803 // Custom lower only if it involves f128 or i64. 2804 if (N->getOperand(0).getValueType() != MVT::f128 2805 || N->getValueType(0) != MVT::i64) 2806 return; 2807 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) 2808 ? RTLIB::FPTOSINT_F128_I64 2809 : RTLIB::FPTOUINT_F128_I64); 2810 2811 Results.push_back(LowerF128Op(SDValue(N, 0), 2812 DAG, 2813 getLibcallName(libCall), 2814 1)); 2815 return; 2816 2817 case ISD::SINT_TO_FP: 2818 case ISD::UINT_TO_FP: 2819 // Custom lower only if it involves f128 or i64. 2820 if (N->getValueType(0) != MVT::f128 2821 || N->getOperand(0).getValueType() != MVT::i64) 2822 return; 2823 2824 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) 2825 ? RTLIB::SINTTOFP_I64_F128 2826 : RTLIB::UINTTOFP_I64_F128); 2827 2828 Results.push_back(LowerF128Op(SDValue(N, 0), 2829 DAG, 2830 getLibcallName(libCall), 2831 1)); 2832 return; 2833 } 2834} 2835