SparcISelLowering.cpp revision 89f530ebbfa91d1583a72d86dc6ca2804f4f450d
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcMachineFunctionInfo.h" 17#include "SparcTargetMachine.h" 18#include "MCTargetDesc/SparcBaseInfo.h" 19#include "llvm/CodeGen/CallingConvLower.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26#include "llvm/IR/DerivedTypes.h" 27#include "llvm/IR/Function.h" 28#include "llvm/IR/Module.h" 29#include "llvm/Support/ErrorHandling.h" 30using namespace llvm; 31 32 33//===----------------------------------------------------------------------===// 34// Calling Convention Implementation 35//===----------------------------------------------------------------------===// 36 37static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 38 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 39 ISD::ArgFlagsTy &ArgFlags, CCState &State) 40{ 41 assert (ArgFlags.isSRet()); 42 43 //Assign SRet argument 44 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 45 0, 46 LocVT, LocInfo)); 47 return true; 48} 49 50static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 51 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 52 ISD::ArgFlagsTy &ArgFlags, CCState &State) 53{ 54 static const uint16_t RegList[] = { 55 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 56 }; 57 //Try to get first reg 58 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 59 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 60 } else { 61 //Assign whole thing in stack 62 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 63 State.AllocateStack(8,4), 64 LocVT, LocInfo)); 65 return true; 66 } 67 68 //Try to get second reg 69 if (unsigned Reg = State.AllocateReg(RegList, 6)) 70 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 71 else 72 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 73 State.AllocateStack(4,4), 74 LocVT, LocInfo)); 75 return true; 76} 77 78// Allocate a full-sized argument for the 64-bit ABI. 79static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, 80 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 81 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 82 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) && 83 "Can't handle non-64 bits locations"); 84 85 // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. 86 unsigned Offset = State.AllocateStack(8, 8); 87 unsigned Reg = 0; 88 89 if (LocVT == MVT::i64 && Offset < 6*8) 90 // Promote integers to %i0-%i5. 91 Reg = SP::I0 + Offset/8; 92 else if (LocVT == MVT::f64 && Offset < 16*8) 93 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). 94 Reg = SP::D0 + Offset/8; 95 else if (LocVT == MVT::f32 && Offset < 16*8) 96 // Promote floats to %f1, %f3, ... 97 Reg = SP::F1 + Offset/4; 98 99 // Promote to register when possible, otherwise use the stack slot. 100 if (Reg) { 101 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 102 return true; 103 } 104 105 // This argument goes on the stack in an 8-byte slot. 106 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to 107 // the right-aligned float. The first 4 bytes of the stack slot are undefined. 108 if (LocVT == MVT::f32) 109 Offset += 4; 110 111 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 112 return true; 113} 114 115// Allocate a half-sized argument for the 64-bit ABI. 116// 117// This is used when passing { float, int } structs by value in registers. 118static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, 119 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 120 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 121 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); 122 unsigned Offset = State.AllocateStack(4, 4); 123 124 if (LocVT == MVT::f32 && Offset < 16*8) { 125 // Promote floats to %f0-%f31. 126 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, 127 LocVT, LocInfo)); 128 return true; 129 } 130 131 if (LocVT == MVT::i32 && Offset < 6*8) { 132 // Promote integers to %i0-%i5, using half the register. 133 unsigned Reg = SP::I0 + Offset/8; 134 LocVT = MVT::i64; 135 LocInfo = CCValAssign::AExt; 136 137 // Set the Custom bit if this i32 goes in the high bits of a register. 138 if (Offset % 8 == 0) 139 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, 140 LocVT, LocInfo)); 141 else 142 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 143 return true; 144 } 145 146 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 147 return true; 148} 149 150#include "SparcGenCallingConv.inc" 151 152// The calling conventions in SparcCallingConv.td are described in terms of the 153// callee's register window. This function translates registers to the 154// corresponding caller window %o register. 155static unsigned toCallerWindow(unsigned Reg) { 156 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); 157 if (Reg >= SP::I0 && Reg <= SP::I7) 158 return Reg - SP::I0 + SP::O0; 159 return Reg; 160} 161 162SDValue 163SparcTargetLowering::LowerReturn(SDValue Chain, 164 CallingConv::ID CallConv, bool IsVarArg, 165 const SmallVectorImpl<ISD::OutputArg> &Outs, 166 const SmallVectorImpl<SDValue> &OutVals, 167 DebugLoc DL, SelectionDAG &DAG) const { 168 if (Subtarget->is64Bit()) 169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 171} 172 173SDValue 174SparcTargetLowering::LowerReturn_32(SDValue Chain, 175 CallingConv::ID CallConv, bool IsVarArg, 176 const SmallVectorImpl<ISD::OutputArg> &Outs, 177 const SmallVectorImpl<SDValue> &OutVals, 178 DebugLoc DL, SelectionDAG &DAG) const { 179 MachineFunction &MF = DAG.getMachineFunction(); 180 181 // CCValAssign - represent the assignment of the return value to locations. 182 SmallVector<CCValAssign, 16> RVLocs; 183 184 // CCState - Info about the registers and stack slot. 185 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 186 DAG.getTarget(), RVLocs, *DAG.getContext()); 187 188 // Analyze return values. 189 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 190 191 SDValue Flag; 192 SmallVector<SDValue, 4> RetOps(1, Chain); 193 // Make room for the return address offset. 194 RetOps.push_back(SDValue()); 195 196 // Copy the result values into the output registers. 197 for (unsigned i = 0; i != RVLocs.size(); ++i) { 198 CCValAssign &VA = RVLocs[i]; 199 assert(VA.isRegLoc() && "Can only return in registers!"); 200 201 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), 202 OutVals[i], Flag); 203 204 // Guarantee that all emitted copies are stuck together with flags. 205 Flag = Chain.getValue(1); 206 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 207 } 208 209 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot 210 // If the function returns a struct, copy the SRetReturnReg to I0 211 if (MF.getFunction()->hasStructRetAttr()) { 212 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 213 unsigned Reg = SFI->getSRetReturnReg(); 214 if (!Reg) 215 llvm_unreachable("sret virtual register not created in the entry block"); 216 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 217 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); 218 Flag = Chain.getValue(1); 219 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); 220 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 221 } 222 223 RetOps[0] = Chain; // Update chain. 224 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 225 226 // Add the flag if we have it. 227 if (Flag.getNode()) 228 RetOps.push_back(Flag); 229 230 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 231 &RetOps[0], RetOps.size()); 232} 233 234// Lower return values for the 64-bit ABI. 235// Return values are passed the exactly the same way as function arguments. 236SDValue 237SparcTargetLowering::LowerReturn_64(SDValue Chain, 238 CallingConv::ID CallConv, bool IsVarArg, 239 const SmallVectorImpl<ISD::OutputArg> &Outs, 240 const SmallVectorImpl<SDValue> &OutVals, 241 DebugLoc DL, SelectionDAG &DAG) const { 242 // CCValAssign - represent the assignment of the return value to locations. 243 SmallVector<CCValAssign, 16> RVLocs; 244 245 // CCState - Info about the registers and stack slot. 246 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 247 DAG.getTarget(), RVLocs, *DAG.getContext()); 248 249 // Analyze return values. 250 CCInfo.AnalyzeReturn(Outs, CC_Sparc64); 251 252 SDValue Flag; 253 SmallVector<SDValue, 4> RetOps(1, Chain); 254 255 // The second operand on the return instruction is the return address offset. 256 // The return address is always %i7+8 with the 64-bit ABI. 257 RetOps.push_back(DAG.getConstant(8, MVT::i32)); 258 259 // Copy the result values into the output registers. 260 for (unsigned i = 0; i != RVLocs.size(); ++i) { 261 CCValAssign &VA = RVLocs[i]; 262 assert(VA.isRegLoc() && "Can only return in registers!"); 263 SDValue OutVal = OutVals[i]; 264 265 // Integer return values must be sign or zero extended by the callee. 266 switch (VA.getLocInfo()) { 267 case CCValAssign::SExt: 268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 269 break; 270 case CCValAssign::ZExt: 271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); 272 break; 273 case CCValAssign::AExt: 274 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); 275 default: 276 break; 277 } 278 279 // The custom bit on an i32 return value indicates that it should be passed 280 // in the high bits of the register. 281 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 282 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 283 DAG.getConstant(32, MVT::i32)); 284 285 // The next value may go in the low bits of the same register. 286 // Handle both at once. 287 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { 288 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); 289 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); 290 // Skip the next value, it's already done. 291 ++i; 292 } 293 } 294 295 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); 296 297 // Guarantee that all emitted copies are stuck together with flags. 298 Flag = Chain.getValue(1); 299 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 300 } 301 302 RetOps[0] = Chain; // Update chain. 303 304 // Add the flag if we have it. 305 if (Flag.getNode()) 306 RetOps.push_back(Flag); 307 308 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 309 &RetOps[0], RetOps.size()); 310} 311 312SDValue SparcTargetLowering:: 313LowerFormalArguments(SDValue Chain, 314 CallingConv::ID CallConv, 315 bool IsVarArg, 316 const SmallVectorImpl<ISD::InputArg> &Ins, 317 DebugLoc DL, 318 SelectionDAG &DAG, 319 SmallVectorImpl<SDValue> &InVals) const { 320 if (Subtarget->is64Bit()) 321 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins, 322 DL, DAG, InVals); 323 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins, 324 DL, DAG, InVals); 325} 326 327/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are 328/// passed in either one or two GPRs, including FP values. TODO: we should 329/// pass FP values in FP registers for fastcc functions. 330SDValue SparcTargetLowering:: 331LowerFormalArguments_32(SDValue Chain, 332 CallingConv::ID CallConv, 333 bool isVarArg, 334 const SmallVectorImpl<ISD::InputArg> &Ins, 335 DebugLoc dl, 336 SelectionDAG &DAG, 337 SmallVectorImpl<SDValue> &InVals) const { 338 MachineFunction &MF = DAG.getMachineFunction(); 339 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 340 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 341 342 // Assign locations to all of the incoming arguments. 343 SmallVector<CCValAssign, 16> ArgLocs; 344 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 345 getTargetMachine(), ArgLocs, *DAG.getContext()); 346 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 347 348 const unsigned StackOffset = 92; 349 350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 351 CCValAssign &VA = ArgLocs[i]; 352 353 if (i == 0 && Ins[i].Flags.isSRet()) { 354 //Get SRet from [%fp+64] 355 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 356 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 357 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 358 MachinePointerInfo(), 359 false, false, false, 0); 360 InVals.push_back(Arg); 361 continue; 362 } 363 364 if (VA.isRegLoc()) { 365 if (VA.needsCustom()) { 366 assert(VA.getLocVT() == MVT::f64); 367 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 368 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 369 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 370 371 assert(i+1 < e); 372 CCValAssign &NextVA = ArgLocs[++i]; 373 374 SDValue LoVal; 375 if (NextVA.isMemLoc()) { 376 int FrameIdx = MF.getFrameInfo()-> 377 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 378 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 379 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 380 MachinePointerInfo(), 381 false, false, false, 0); 382 } else { 383 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 384 &SP::IntRegsRegClass); 385 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 386 } 387 SDValue WholeValue = 388 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 389 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 390 InVals.push_back(WholeValue); 391 continue; 392 } 393 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 395 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 396 if (VA.getLocVT() == MVT::f32) 397 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 398 else if (VA.getLocVT() != MVT::i32) { 399 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 400 DAG.getValueType(VA.getLocVT())); 401 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 402 } 403 InVals.push_back(Arg); 404 continue; 405 } 406 407 assert(VA.isMemLoc()); 408 409 unsigned Offset = VA.getLocMemOffset()+StackOffset; 410 411 if (VA.needsCustom()) { 412 assert(VA.getValVT() == MVT::f64); 413 //If it is double-word aligned, just load. 414 if (Offset % 8 == 0) { 415 int FI = MF.getFrameInfo()->CreateFixedObject(8, 416 Offset, 417 true); 418 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 419 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 420 MachinePointerInfo(), 421 false,false, false, 0); 422 InVals.push_back(Load); 423 continue; 424 } 425 426 int FI = MF.getFrameInfo()->CreateFixedObject(4, 427 Offset, 428 true); 429 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 430 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 431 MachinePointerInfo(), 432 false, false, false, 0); 433 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 434 Offset+4, 435 true); 436 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 437 438 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 439 MachinePointerInfo(), 440 false, false, false, 0); 441 442 SDValue WholeValue = 443 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 444 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 445 InVals.push_back(WholeValue); 446 continue; 447 } 448 449 int FI = MF.getFrameInfo()->CreateFixedObject(4, 450 Offset, 451 true); 452 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 453 SDValue Load ; 454 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 455 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 456 MachinePointerInfo(), 457 false, false, false, 0); 458 } else { 459 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 460 // Sparc is big endian, so add an offset based on the ObjectVT. 461 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 462 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 463 DAG.getConstant(Offset, MVT::i32)); 464 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 465 MachinePointerInfo(), 466 VA.getValVT(), false, false,0); 467 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 468 } 469 InVals.push_back(Load); 470 } 471 472 if (MF.getFunction()->hasStructRetAttr()) { 473 //Copy the SRet Argument to SRetReturnReg 474 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 475 unsigned Reg = SFI->getSRetReturnReg(); 476 if (!Reg) { 477 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 478 SFI->setSRetReturnReg(Reg); 479 } 480 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 481 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 482 } 483 484 // Store remaining ArgRegs to the stack if this is a varargs function. 485 if (isVarArg) { 486 static const uint16_t ArgRegs[] = { 487 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 488 }; 489 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 490 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 491 unsigned ArgOffset = CCInfo.getNextStackOffset(); 492 if (NumAllocated == 6) 493 ArgOffset += StackOffset; 494 else { 495 assert(!ArgOffset); 496 ArgOffset = 68+4*NumAllocated; 497 } 498 499 // Remember the vararg offset for the va_start implementation. 500 FuncInfo->setVarArgsFrameOffset(ArgOffset); 501 502 std::vector<SDValue> OutChains; 503 504 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 505 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 506 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 507 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 508 509 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 510 true); 511 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 512 513 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 514 MachinePointerInfo(), 515 false, false, 0)); 516 ArgOffset += 4; 517 } 518 519 if (!OutChains.empty()) { 520 OutChains.push_back(Chain); 521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 522 &OutChains[0], OutChains.size()); 523 } 524 } 525 526 return Chain; 527} 528 529// Lower formal arguments for the 64 bit ABI. 530SDValue SparcTargetLowering:: 531LowerFormalArguments_64(SDValue Chain, 532 CallingConv::ID CallConv, 533 bool IsVarArg, 534 const SmallVectorImpl<ISD::InputArg> &Ins, 535 DebugLoc DL, 536 SelectionDAG &DAG, 537 SmallVectorImpl<SDValue> &InVals) const { 538 MachineFunction &MF = DAG.getMachineFunction(); 539 540 // Analyze arguments according to CC_Sparc64. 541 SmallVector<CCValAssign, 16> ArgLocs; 542 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 543 getTargetMachine(), ArgLocs, *DAG.getContext()); 544 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); 545 546 // The argument array begins at %fp+BIAS+128, after the register save area. 547 const unsigned ArgArea = 128; 548 549 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 550 CCValAssign &VA = ArgLocs[i]; 551 if (VA.isRegLoc()) { 552 // This argument is passed in a register. 553 // All integer register arguments are promoted by the caller to i64. 554 555 // Create a virtual register for the promoted live-in value. 556 unsigned VReg = MF.addLiveIn(VA.getLocReg(), 557 getRegClassFor(VA.getLocVT())); 558 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); 559 560 // Get the high bits for i32 struct elements. 561 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 562 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, 563 DAG.getConstant(32, MVT::i32)); 564 565 // The caller promoted the argument, so insert an Assert?ext SDNode so we 566 // won't promote the value again in this function. 567 switch (VA.getLocInfo()) { 568 case CCValAssign::SExt: 569 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, 570 DAG.getValueType(VA.getValVT())); 571 break; 572 case CCValAssign::ZExt: 573 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, 574 DAG.getValueType(VA.getValVT())); 575 break; 576 default: 577 break; 578 } 579 580 // Truncate the register down to the argument type. 581 if (VA.isExtInLoc()) 582 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); 583 584 InVals.push_back(Arg); 585 continue; 586 } 587 588 // The registers are exhausted. This argument was passed on the stack. 589 assert(VA.isMemLoc()); 590 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the 591 // beginning of the arguments area at %fp+BIAS+128. 592 unsigned Offset = VA.getLocMemOffset() + ArgArea; 593 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; 594 // Adjust offset for extended arguments, SPARC is big-endian. 595 // The caller will have written the full slot with extended bytes, but we 596 // prefer our own extending loads. 597 if (VA.isExtInLoc()) 598 Offset += 8 - ValSize; 599 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true); 600 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, 601 DAG.getFrameIndex(FI, getPointerTy()), 602 MachinePointerInfo::getFixedStack(FI), 603 false, false, false, 0)); 604 } 605 606 if (!IsVarArg) 607 return Chain; 608 609 // This function takes variable arguments, some of which may have been passed 610 // in registers %i0-%i5. Variable floating point arguments are never passed 611 // in floating point registers. They go on %i0-%i5 or on the stack like 612 // integer arguments. 613 // 614 // The va_start intrinsic needs to know the offset to the first variable 615 // argument. 616 unsigned ArgOffset = CCInfo.getNextStackOffset(); 617 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 618 // Skip the 128 bytes of register save area. 619 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea + 620 Subtarget->getStackPointerBias()); 621 622 // Save the variable arguments that were passed in registers. 623 // The caller is required to reserve stack space for 6 arguments regardless 624 // of how many arguments were actually passed. 625 SmallVector<SDValue, 8> OutChains; 626 for (; ArgOffset < 6*8; ArgOffset += 8) { 627 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); 628 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 629 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true); 630 OutChains.push_back(DAG.getStore(Chain, DL, VArg, 631 DAG.getFrameIndex(FI, getPointerTy()), 632 MachinePointerInfo::getFixedStack(FI), 633 false, false, 0)); 634 } 635 636 if (!OutChains.empty()) 637 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 638 &OutChains[0], OutChains.size()); 639 640 return Chain; 641} 642 643SDValue 644SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 645 SmallVectorImpl<SDValue> &InVals) const { 646 if (Subtarget->is64Bit()) 647 return LowerCall_64(CLI, InVals); 648 return LowerCall_32(CLI, InVals); 649} 650 651// Lower a call for the 32-bit ABI. 652SDValue 653SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 654 SmallVectorImpl<SDValue> &InVals) const { 655 SelectionDAG &DAG = CLI.DAG; 656 DebugLoc &dl = CLI.DL; 657 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 658 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 659 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 660 SDValue Chain = CLI.Chain; 661 SDValue Callee = CLI.Callee; 662 bool &isTailCall = CLI.IsTailCall; 663 CallingConv::ID CallConv = CLI.CallConv; 664 bool isVarArg = CLI.IsVarArg; 665 666 // Sparc target does not yet support tail call optimization. 667 isTailCall = false; 668 669 // Analyze operands of the call, assigning locations to each operand. 670 SmallVector<CCValAssign, 16> ArgLocs; 671 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 672 DAG.getTarget(), ArgLocs, *DAG.getContext()); 673 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 674 675 // Get the size of the outgoing arguments stack space requirement. 676 unsigned ArgsSize = CCInfo.getNextStackOffset(); 677 678 // Keep stack frames 8-byte aligned. 679 ArgsSize = (ArgsSize+7) & ~7; 680 681 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 682 683 //Create local copies for byval args. 684 SmallVector<SDValue, 8> ByValArgs; 685 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 686 ISD::ArgFlagsTy Flags = Outs[i].Flags; 687 if (!Flags.isByVal()) 688 continue; 689 690 SDValue Arg = OutVals[i]; 691 unsigned Size = Flags.getByValSize(); 692 unsigned Align = Flags.getByValAlign(); 693 694 int FI = MFI->CreateStackObject(Size, Align, false); 695 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 696 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 697 698 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 699 false, //isVolatile, 700 (Size <= 32), //AlwaysInline if size <= 32 701 MachinePointerInfo(), MachinePointerInfo()); 702 ByValArgs.push_back(FIPtr); 703 } 704 705 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 706 707 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 708 SmallVector<SDValue, 8> MemOpChains; 709 710 const unsigned StackOffset = 92; 711 bool hasStructRetAttr = false; 712 // Walk the register/memloc assignments, inserting copies/loads. 713 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 714 i != e; 715 ++i, ++realArgIdx) { 716 CCValAssign &VA = ArgLocs[i]; 717 SDValue Arg = OutVals[realArgIdx]; 718 719 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 720 721 //Use local copy if it is a byval arg. 722 if (Flags.isByVal()) 723 Arg = ByValArgs[byvalArgIdx++]; 724 725 // Promote the value if needed. 726 switch (VA.getLocInfo()) { 727 default: llvm_unreachable("Unknown loc info!"); 728 case CCValAssign::Full: break; 729 case CCValAssign::SExt: 730 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 731 break; 732 case CCValAssign::ZExt: 733 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 734 break; 735 case CCValAssign::AExt: 736 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 737 break; 738 case CCValAssign::BCvt: 739 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 740 break; 741 } 742 743 if (Flags.isSRet()) { 744 assert(VA.needsCustom()); 745 // store SRet argument in %sp+64 746 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 747 SDValue PtrOff = DAG.getIntPtrConstant(64); 748 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 749 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 750 MachinePointerInfo(), 751 false, false, 0)); 752 hasStructRetAttr = true; 753 continue; 754 } 755 756 if (VA.needsCustom()) { 757 assert(VA.getLocVT() == MVT::f64); 758 759 if (VA.isMemLoc()) { 760 unsigned Offset = VA.getLocMemOffset() + StackOffset; 761 //if it is double-word aligned, just store. 762 if (Offset % 8 == 0) { 763 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 764 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 765 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 766 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 767 MachinePointerInfo(), 768 false, false, 0)); 769 continue; 770 } 771 } 772 773 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 774 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 775 Arg, StackPtr, MachinePointerInfo(), 776 false, false, 0); 777 // Sparc is big-endian, so the high part comes first. 778 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 779 MachinePointerInfo(), false, false, false, 0); 780 // Increment the pointer to the other half. 781 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 782 DAG.getIntPtrConstant(4)); 783 // Load the low part. 784 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 785 MachinePointerInfo(), false, false, false, 0); 786 787 if (VA.isRegLoc()) { 788 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 789 assert(i+1 != e); 790 CCValAssign &NextVA = ArgLocs[++i]; 791 if (NextVA.isRegLoc()) { 792 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 793 } else { 794 //Store the low part in stack. 795 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 796 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 797 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 798 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 799 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 800 MachinePointerInfo(), 801 false, false, 0)); 802 } 803 } else { 804 unsigned Offset = VA.getLocMemOffset() + StackOffset; 805 // Store the high part. 806 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 807 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 808 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 809 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 810 MachinePointerInfo(), 811 false, false, 0)); 812 // Store the low part. 813 PtrOff = DAG.getIntPtrConstant(Offset+4); 814 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 815 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 816 MachinePointerInfo(), 817 false, false, 0)); 818 } 819 continue; 820 } 821 822 // Arguments that can be passed on register must be kept at 823 // RegsToPass vector 824 if (VA.isRegLoc()) { 825 if (VA.getLocVT() != MVT::f32) { 826 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 827 continue; 828 } 829 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 830 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 831 continue; 832 } 833 834 assert(VA.isMemLoc()); 835 836 // Create a store off the stack pointer for this argument. 837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 838 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 839 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 840 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 841 MachinePointerInfo(), 842 false, false, 0)); 843 } 844 845 846 // Emit all stores, make sure the occur before any copies into physregs. 847 if (!MemOpChains.empty()) 848 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 849 &MemOpChains[0], MemOpChains.size()); 850 851 // Build a sequence of copy-to-reg nodes chained together with token 852 // chain and flag operands which copy the outgoing args into registers. 853 // The InFlag in necessary since all emitted instructions must be 854 // stuck together. 855 SDValue InFlag; 856 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 857 unsigned Reg = toCallerWindow(RegsToPass[i].first); 858 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 859 InFlag = Chain.getValue(1); 860 } 861 862 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 863 864 // If the callee is a GlobalAddress node (quite common, every direct call is) 865 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 866 // Likewise ExternalSymbol -> TargetExternalSymbol. 867 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 868 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 869 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 870 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 871 872 // Returns a chain & a flag for retval copy to use 873 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 874 SmallVector<SDValue, 8> Ops; 875 Ops.push_back(Chain); 876 Ops.push_back(Callee); 877 if (hasStructRetAttr) 878 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 879 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 880 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), 881 RegsToPass[i].second.getValueType())); 882 if (InFlag.getNode()) 883 Ops.push_back(InFlag); 884 885 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 886 InFlag = Chain.getValue(1); 887 888 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 889 DAG.getIntPtrConstant(0, true), InFlag); 890 InFlag = Chain.getValue(1); 891 892 // Assign locations to each value returned by this call. 893 SmallVector<CCValAssign, 16> RVLocs; 894 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 895 DAG.getTarget(), RVLocs, *DAG.getContext()); 896 897 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 898 899 // Copy all of the result registers out of their specified physreg. 900 for (unsigned i = 0; i != RVLocs.size(); ++i) { 901 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), 902 RVLocs[i].getValVT(), InFlag).getValue(1); 903 InFlag = Chain.getValue(2); 904 InVals.push_back(Chain.getValue(0)); 905 } 906 907 return Chain; 908} 909 910unsigned 911SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 912{ 913 const Function *CalleeFn = 0; 914 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 915 CalleeFn = dyn_cast<Function>(G->getGlobal()); 916 } else if (ExternalSymbolSDNode *E = 917 dyn_cast<ExternalSymbolSDNode>(Callee)) { 918 const Function *Fn = DAG.getMachineFunction().getFunction(); 919 const Module *M = Fn->getParent(); 920 CalleeFn = M->getFunction(E->getSymbol()); 921 } 922 923 if (!CalleeFn) 924 return 0; 925 926 assert(CalleeFn->hasStructRetAttr() && 927 "Callee does not have the StructRet attribute."); 928 929 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 930 Type *ElementTy = Ty->getElementType(); 931 return getDataLayout()->getTypeAllocSize(ElementTy); 932} 933 934 935// Fixup floating point arguments in the ... part of a varargs call. 936// 937// The SPARC v9 ABI requires that floating point arguments are treated the same 938// as integers when calling a varargs function. This does not apply to the 939// fixed arguments that are part of the function's prototype. 940// 941// This function post-processes a CCValAssign array created by 942// AnalyzeCallOperands(). 943static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, 944 ArrayRef<ISD::OutputArg> Outs) { 945 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 946 const CCValAssign &VA = ArgLocs[i]; 947 // FIXME: What about f32 arguments? C promotes them to f64 when calling 948 // varargs functions. 949 if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64) 950 continue; 951 // The fixed arguments to a varargs function still go in FP registers. 952 if (Outs[VA.getValNo()].IsFixed) 953 continue; 954 955 // This floating point argument should be reassigned. 956 CCValAssign NewVA; 957 958 // Determine the offset into the argument array. 959 unsigned Offset = 8 * (VA.getLocReg() - SP::D0); 960 assert(Offset < 16*8 && "Offset out of range, bad register enum?"); 961 962 if (Offset < 6*8) { 963 // This argument should go in %i0-%i5. 964 unsigned IReg = SP::I0 + Offset/8; 965 // Full register, just bitconvert into i64. 966 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), 967 IReg, MVT::i64, CCValAssign::BCvt); 968 } else { 969 // This needs to go to memory, we're out of integer registers. 970 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), 971 Offset, VA.getLocVT(), VA.getLocInfo()); 972 } 973 ArgLocs[i] = NewVA; 974 } 975} 976 977// Lower a call for the 64-bit ABI. 978SDValue 979SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 980 SmallVectorImpl<SDValue> &InVals) const { 981 SelectionDAG &DAG = CLI.DAG; 982 DebugLoc DL = CLI.DL; 983 SDValue Chain = CLI.Chain; 984 985 // Analyze operands of the call, assigning locations to each operand. 986 SmallVector<CCValAssign, 16> ArgLocs; 987 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 988 DAG.getTarget(), ArgLocs, *DAG.getContext()); 989 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); 990 991 // Get the size of the outgoing arguments stack space requirement. 992 // The stack offset computed by CC_Sparc64 includes all arguments. 993 // Called functions expect 6 argument words to exist in the stack frame, used 994 // or not. 995 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); 996 997 // Keep stack frames 16-byte aligned. 998 ArgsSize = RoundUpToAlignment(ArgsSize, 16); 999 1000 // Varargs calls require special treatment. 1001 if (CLI.IsVarArg) 1002 fixupVariableFloatArgs(ArgLocs, CLI.Outs); 1003 1004 // Adjust the stack pointer to make room for the arguments. 1005 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls 1006 // with more than 6 arguments. 1007 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 1008 1009 // Collect the set of registers to pass to the function and their values. 1010 // This will be emitted as a sequence of CopyToReg nodes glued to the call 1011 // instruction. 1012 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1013 1014 // Collect chains from all the memory opeations that copy arguments to the 1015 // stack. They must follow the stack pointer adjustment above and precede the 1016 // call instruction itself. 1017 SmallVector<SDValue, 8> MemOpChains; 1018 1019 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1020 const CCValAssign &VA = ArgLocs[i]; 1021 SDValue Arg = CLI.OutVals[i]; 1022 1023 // Promote the value if needed. 1024 switch (VA.getLocInfo()) { 1025 default: 1026 llvm_unreachable("Unknown location info!"); 1027 case CCValAssign::Full: 1028 break; 1029 case CCValAssign::SExt: 1030 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 1031 break; 1032 case CCValAssign::ZExt: 1033 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 1034 break; 1035 case CCValAssign::AExt: 1036 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 1037 break; 1038 case CCValAssign::BCvt: 1039 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 1040 break; 1041 } 1042 1043 if (VA.isRegLoc()) { 1044 // The custom bit on an i32 return value indicates that it should be 1045 // passed in the high bits of the register. 1046 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 1047 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, 1048 DAG.getConstant(32, MVT::i32)); 1049 1050 // The next value may go in the low bits of the same register. 1051 // Handle both at once. 1052 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && 1053 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { 1054 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, 1055 CLI.OutVals[i+1]); 1056 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); 1057 // Skip the next value, it's already done. 1058 ++i; 1059 } 1060 } 1061 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); 1062 continue; 1063 } 1064 1065 assert(VA.isMemLoc()); 1066 1067 // Create a store off the stack pointer for this argument. 1068 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 1069 // The argument area starts at %fp+BIAS+128 in the callee frame, 1070 // %sp+BIAS+128 in ours. 1071 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + 1072 Subtarget->getStackPointerBias() + 1073 128); 1074 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 1075 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, 1076 MachinePointerInfo(), 1077 false, false, 0)); 1078 } 1079 1080 // Emit all stores, make sure they occur before the call. 1081 if (!MemOpChains.empty()) 1082 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 1083 &MemOpChains[0], MemOpChains.size()); 1084 1085 // Build a sequence of CopyToReg nodes glued together with token chain and 1086 // glue operands which copy the outgoing args into registers. The InGlue is 1087 // necessary since all emitted instructions must be stuck together in order 1088 // to pass the live physical registers. 1089 SDValue InGlue; 1090 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1091 Chain = DAG.getCopyToReg(Chain, DL, 1092 RegsToPass[i].first, RegsToPass[i].second, InGlue); 1093 InGlue = Chain.getValue(1); 1094 } 1095 1096 // If the callee is a GlobalAddress node (quite common, every direct call is) 1097 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1098 // Likewise ExternalSymbol -> TargetExternalSymbol. 1099 SDValue Callee = CLI.Callee; 1100 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1101 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy()); 1102 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1103 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 1104 1105 // Build the operands for the call instruction itself. 1106 SmallVector<SDValue, 8> Ops; 1107 Ops.push_back(Chain); 1108 Ops.push_back(Callee); 1109 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1110 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1111 RegsToPass[i].second.getValueType())); 1112 1113 // Make sure the CopyToReg nodes are glued to the call instruction which 1114 // consumes the registers. 1115 if (InGlue.getNode()) 1116 Ops.push_back(InGlue); 1117 1118 // Now the call itself. 1119 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1120 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size()); 1121 InGlue = Chain.getValue(1); 1122 1123 // Revert the stack pointer immediately after the call. 1124 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1125 DAG.getIntPtrConstant(0, true), InGlue); 1126 InGlue = Chain.getValue(1); 1127 1128 // Now extract the return values. This is more or less the same as 1129 // LowerFormalArguments_64. 1130 1131 // Assign locations to each value returned by this call. 1132 SmallVector<CCValAssign, 16> RVLocs; 1133 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1134 DAG.getTarget(), RVLocs, *DAG.getContext()); 1135 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64); 1136 1137 // Copy all of the result registers out of their specified physreg. 1138 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1139 CCValAssign &VA = RVLocs[i]; 1140 unsigned Reg = toCallerWindow(VA.getLocReg()); 1141 1142 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can 1143 // reside in the same register in the high and low bits. Reuse the 1144 // CopyFromReg previous node to avoid duplicate copies. 1145 SDValue RV; 1146 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1))) 1147 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) 1148 RV = Chain.getValue(0); 1149 1150 // But usually we'll create a new CopyFromReg for a different register. 1151 if (!RV.getNode()) { 1152 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue); 1153 Chain = RV.getValue(1); 1154 InGlue = Chain.getValue(2); 1155 } 1156 1157 // Get the high bits for i32 struct elements. 1158 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 1159 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, 1160 DAG.getConstant(32, MVT::i32)); 1161 1162 // The callee promoted the return value, so insert an Assert?ext SDNode so 1163 // we won't promote the value again in this function. 1164 switch (VA.getLocInfo()) { 1165 case CCValAssign::SExt: 1166 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, 1167 DAG.getValueType(VA.getValVT())); 1168 break; 1169 case CCValAssign::ZExt: 1170 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, 1171 DAG.getValueType(VA.getValVT())); 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 // Truncate the register down to the return value type. 1178 if (VA.isExtInLoc()) 1179 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); 1180 1181 InVals.push_back(RV); 1182 } 1183 1184 return Chain; 1185} 1186 1187//===----------------------------------------------------------------------===// 1188// TargetLowering Implementation 1189//===----------------------------------------------------------------------===// 1190 1191/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 1192/// condition. 1193static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 1194 switch (CC) { 1195 default: llvm_unreachable("Unknown integer condition code!"); 1196 case ISD::SETEQ: return SPCC::ICC_E; 1197 case ISD::SETNE: return SPCC::ICC_NE; 1198 case ISD::SETLT: return SPCC::ICC_L; 1199 case ISD::SETGT: return SPCC::ICC_G; 1200 case ISD::SETLE: return SPCC::ICC_LE; 1201 case ISD::SETGE: return SPCC::ICC_GE; 1202 case ISD::SETULT: return SPCC::ICC_CS; 1203 case ISD::SETULE: return SPCC::ICC_LEU; 1204 case ISD::SETUGT: return SPCC::ICC_GU; 1205 case ISD::SETUGE: return SPCC::ICC_CC; 1206 } 1207} 1208 1209/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 1210/// FCC condition. 1211static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 1212 switch (CC) { 1213 default: llvm_unreachable("Unknown fp condition code!"); 1214 case ISD::SETEQ: 1215 case ISD::SETOEQ: return SPCC::FCC_E; 1216 case ISD::SETNE: 1217 case ISD::SETUNE: return SPCC::FCC_NE; 1218 case ISD::SETLT: 1219 case ISD::SETOLT: return SPCC::FCC_L; 1220 case ISD::SETGT: 1221 case ISD::SETOGT: return SPCC::FCC_G; 1222 case ISD::SETLE: 1223 case ISD::SETOLE: return SPCC::FCC_LE; 1224 case ISD::SETGE: 1225 case ISD::SETOGE: return SPCC::FCC_GE; 1226 case ISD::SETULT: return SPCC::FCC_UL; 1227 case ISD::SETULE: return SPCC::FCC_ULE; 1228 case ISD::SETUGT: return SPCC::FCC_UG; 1229 case ISD::SETUGE: return SPCC::FCC_UGE; 1230 case ISD::SETUO: return SPCC::FCC_U; 1231 case ISD::SETO: return SPCC::FCC_O; 1232 case ISD::SETONE: return SPCC::FCC_LG; 1233 case ISD::SETUEQ: return SPCC::FCC_UE; 1234 } 1235} 1236 1237SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 1238 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 1239 Subtarget = &TM.getSubtarget<SparcSubtarget>(); 1240 1241 // Set up the register classes. 1242 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); 1243 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); 1244 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); 1245 if (Subtarget->is64Bit()) 1246 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); 1247 1248 // Turn FP extload into load/fextend 1249 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1250 // Sparc doesn't have i1 sign extending load 1251 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1252 // Turn FP truncstore into trunc + store. 1253 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1254 1255 // Custom legalize GlobalAddress nodes into LO/HI parts. 1256 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); 1257 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); 1258 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); 1259 1260 // Sparc doesn't have sext_inreg, replace them with shl/sra 1261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 1262 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 1263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1264 1265 // Sparc has no REM or DIVREM operations. 1266 setOperationAction(ISD::UREM, MVT::i32, Expand); 1267 setOperationAction(ISD::SREM, MVT::i32, Expand); 1268 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1269 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1270 1271 // Custom expand fp<->sint 1272 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 1273 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1274 1275 // Expand fp<->uint 1276 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1277 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1278 1279 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 1280 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 1281 1282 // Sparc has no select or setcc: expand to SELECT_CC. 1283 setOperationAction(ISD::SELECT, MVT::i32, Expand); 1284 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1285 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1286 setOperationAction(ISD::SETCC, MVT::i32, Expand); 1287 setOperationAction(ISD::SETCC, MVT::f32, Expand); 1288 setOperationAction(ISD::SETCC, MVT::f64, Expand); 1289 1290 // Sparc doesn't have BRCOND either, it has BR_CC. 1291 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1292 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1293 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1294 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1295 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1296 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 1297 1298 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1299 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1300 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1301 1302 if (Subtarget->is64Bit()) { 1303 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 1304 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 1305 setOperationAction(ISD::SELECT, MVT::i64, Expand); 1306 setOperationAction(ISD::SETCC, MVT::i64, Expand); 1307 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 1308 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1309 } 1310 1311 // FIXME: There are instructions available for ATOMIC_FENCE 1312 // on SparcV8 and later. 1313 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 1314 1315 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1316 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1317 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1318 setOperationAction(ISD::FREM , MVT::f64, Expand); 1319 setOperationAction(ISD::FMA , MVT::f64, Expand); 1320 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1321 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1322 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1323 setOperationAction(ISD::FREM , MVT::f32, Expand); 1324 setOperationAction(ISD::FMA , MVT::f32, Expand); 1325 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 1326 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1328 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1329 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1330 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1331 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1332 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1333 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1334 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1335 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1336 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1337 1338 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1339 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1340 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1341 1342 // FIXME: Sparc provides these multiplies, but we don't have them yet. 1343 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1344 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1345 1346 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 1347 1348 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1349 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1350 // VAARG needs to be lowered to not do unaligned accesses for doubles. 1351 setOperationAction(ISD::VAARG , MVT::Other, Custom); 1352 1353 // Use the default implementation. 1354 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1355 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1356 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1357 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1358 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1359 1360 // No debug info support yet. 1361 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 1362 1363 setStackPointerRegisterToSaveRestore(SP::O6); 1364 1365 if (TM.getSubtarget<SparcSubtarget>().isV9()) 1366 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 1367 1368 setMinFunctionAlignment(2); 1369 1370 computeRegisterProperties(); 1371} 1372 1373const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 1374 switch (Opcode) { 1375 default: return 0; 1376 case SPISD::CMPICC: return "SPISD::CMPICC"; 1377 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 1378 case SPISD::BRICC: return "SPISD::BRICC"; 1379 case SPISD::BRXCC: return "SPISD::BRXCC"; 1380 case SPISD::BRFCC: return "SPISD::BRFCC"; 1381 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 1382 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; 1383 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 1384 case SPISD::Hi: return "SPISD::Hi"; 1385 case SPISD::Lo: return "SPISD::Lo"; 1386 case SPISD::FTOI: return "SPISD::FTOI"; 1387 case SPISD::ITOF: return "SPISD::ITOF"; 1388 case SPISD::CALL: return "SPISD::CALL"; 1389 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 1390 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 1391 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 1392 } 1393} 1394 1395/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 1396/// be zero. Op is expected to be a target specific node. Used by DAG 1397/// combiner. 1398void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1399 APInt &KnownZero, 1400 APInt &KnownOne, 1401 const SelectionDAG &DAG, 1402 unsigned Depth) const { 1403 APInt KnownZero2, KnownOne2; 1404 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1405 1406 switch (Op.getOpcode()) { 1407 default: break; 1408 case SPISD::SELECT_ICC: 1409 case SPISD::SELECT_XCC: 1410 case SPISD::SELECT_FCC: 1411 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); 1412 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); 1413 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1414 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1415 1416 // Only known if known in both the LHS and RHS. 1417 KnownOne &= KnownOne2; 1418 KnownZero &= KnownZero2; 1419 break; 1420 } 1421} 1422 1423// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 1424// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 1425static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 1426 ISD::CondCode CC, unsigned &SPCC) { 1427 if (isa<ConstantSDNode>(RHS) && 1428 cast<ConstantSDNode>(RHS)->isNullValue() && 1429 CC == ISD::SETNE && 1430 (((LHS.getOpcode() == SPISD::SELECT_ICC || 1431 LHS.getOpcode() == SPISD::SELECT_XCC) && 1432 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 1433 (LHS.getOpcode() == SPISD::SELECT_FCC && 1434 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 1435 isa<ConstantSDNode>(LHS.getOperand(0)) && 1436 isa<ConstantSDNode>(LHS.getOperand(1)) && 1437 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 1438 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 1439 SDValue CMPCC = LHS.getOperand(3); 1440 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 1441 LHS = CMPCC.getOperand(0); 1442 RHS = CMPCC.getOperand(1); 1443 } 1444} 1445 1446// Convert to a target node and set target flags. 1447SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, 1448 SelectionDAG &DAG) const { 1449 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) 1450 return DAG.getTargetGlobalAddress(GA->getGlobal(), 1451 GA->getDebugLoc(), 1452 GA->getValueType(0), 1453 GA->getOffset(), TF); 1454 1455 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) 1456 return DAG.getTargetConstantPool(CP->getConstVal(), 1457 CP->getValueType(0), 1458 CP->getAlignment(), 1459 CP->getOffset(), TF); 1460 1461 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) 1462 return DAG.getTargetExternalSymbol(ES->getSymbol(), 1463 ES->getValueType(0), TF); 1464 1465 llvm_unreachable("Unhandled address SDNode"); 1466} 1467 1468// Split Op into high and low parts according to HiTF and LoTF. 1469// Return an ADD node combining the parts. 1470SDValue SparcTargetLowering::makeHiLoPair(SDValue Op, 1471 unsigned HiTF, unsigned LoTF, 1472 SelectionDAG &DAG) const { 1473 DebugLoc DL = Op.getDebugLoc(); 1474 EVT VT = Op.getValueType(); 1475 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG)); 1476 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); 1477 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1478} 1479 1480// Build SDNodes for producing an address from a GlobalAddress, ConstantPool, 1481// or ExternalSymbol SDNode. 1482SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { 1483 DebugLoc DL = Op.getDebugLoc(); 1484 EVT VT = getPointerTy(); 1485 1486 // Handle PIC mode first. 1487 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1488 // This is the pic32 code model, the GOT is known to be smaller than 4GB. 1489 SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1490 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT); 1491 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo); 1492 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr, 1493 MachinePointerInfo::getGOT(), false, false, false, 0); 1494 } 1495 1496 // This is one of the absolute code models. 1497 switch(getTargetMachine().getCodeModel()) { 1498 default: 1499 llvm_unreachable("Unsupported absolute code model"); 1500 case CodeModel::Small: 1501 // abs32. 1502 return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1503 case CodeModel::Medium: { 1504 // abs44. 1505 SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG); 1506 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); 1507 SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG); 1508 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); 1509 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); 1510 } 1511 case CodeModel::Large: { 1512 // abs64. 1513 SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG); 1514 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); 1515 SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1516 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1517 } 1518 } 1519} 1520 1521SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 1522 SelectionDAG &DAG) const { 1523 return makeAddress(Op, DAG); 1524} 1525 1526SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 1527 SelectionDAG &DAG) const { 1528 return makeAddress(Op, DAG); 1529} 1530 1531static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 1532 DebugLoc dl = Op.getDebugLoc(); 1533 // Convert the fp value to integer in an FP register. 1534 assert(Op.getValueType() == MVT::i32); 1535 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 1536 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 1537} 1538 1539static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1540 DebugLoc dl = Op.getDebugLoc(); 1541 assert(Op.getOperand(0).getValueType() == MVT::i32); 1542 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 1543 // Convert the int value to FP in an FP register. 1544 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 1545} 1546 1547static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 1548 SDValue Chain = Op.getOperand(0); 1549 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1550 SDValue LHS = Op.getOperand(2); 1551 SDValue RHS = Op.getOperand(3); 1552 SDValue Dest = Op.getOperand(4); 1553 DebugLoc dl = Op.getDebugLoc(); 1554 unsigned Opc, SPCC = ~0U; 1555 1556 // If this is a br_cc of a "setcc", and if the setcc got lowered into 1557 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 1558 LookThroughSetCC(LHS, RHS, CC, SPCC); 1559 1560 // Get the condition flag. 1561 SDValue CompareFlag; 1562 if (LHS.getValueType().isInteger()) { 1563 EVT VTs[] = { LHS.getValueType(), MVT::Glue }; 1564 SDValue Ops[2] = { LHS, RHS }; 1565 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 1566 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 1567 // 32-bit compares use the icc flags, 64-bit uses the xcc flags. 1568 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; 1569 } else { 1570 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 1571 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 1572 Opc = SPISD::BRFCC; 1573 } 1574 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 1575 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 1576} 1577 1578static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 1579 SDValue LHS = Op.getOperand(0); 1580 SDValue RHS = Op.getOperand(1); 1581 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1582 SDValue TrueVal = Op.getOperand(2); 1583 SDValue FalseVal = Op.getOperand(3); 1584 DebugLoc dl = Op.getDebugLoc(); 1585 unsigned Opc, SPCC = ~0U; 1586 1587 // If this is a select_cc of a "setcc", and if the setcc got lowered into 1588 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 1589 LookThroughSetCC(LHS, RHS, CC, SPCC); 1590 1591 SDValue CompareFlag; 1592 if (LHS.getValueType().isInteger()) { 1593 // subcc returns a value 1594 EVT VTs[] = { LHS.getValueType(), MVT::Glue }; 1595 SDValue Ops[2] = { LHS, RHS }; 1596 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 1597 Opc = LHS.getValueType() == MVT::i32 ? 1598 SPISD::SELECT_ICC : SPISD::SELECT_XCC; 1599 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 1600 } else { 1601 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 1602 Opc = SPISD::SELECT_FCC; 1603 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 1604 } 1605 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 1606 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 1607} 1608 1609static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1610 const SparcTargetLowering &TLI) { 1611 MachineFunction &MF = DAG.getMachineFunction(); 1612 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 1613 1614 // vastart just stores the address of the VarArgsFrameIndex slot into the 1615 // memory location argument. 1616 DebugLoc DL = Op.getDebugLoc(); 1617 SDValue Offset = 1618 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), 1619 DAG.getRegister(SP::I6, TLI.getPointerTy()), 1620 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset())); 1621 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1622 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), 1623 MachinePointerInfo(SV), false, false, 0); 1624} 1625 1626static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 1627 SDNode *Node = Op.getNode(); 1628 EVT VT = Node->getValueType(0); 1629 SDValue InChain = Node->getOperand(0); 1630 SDValue VAListPtr = Node->getOperand(1); 1631 EVT PtrVT = VAListPtr.getValueType(); 1632 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1633 DebugLoc DL = Node->getDebugLoc(); 1634 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr, 1635 MachinePointerInfo(SV), false, false, false, 0); 1636 // Increment the pointer, VAList, to the next vaarg. 1637 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, 1638 DAG.getIntPtrConstant(VT.getSizeInBits()/8)); 1639 // Store the incremented VAList to the legalized pointer. 1640 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, 1641 VAListPtr, MachinePointerInfo(SV), false, false, 0); 1642 // Load the actual argument out of the pointer VAList. 1643 // We can't count on greater alignment than the word size. 1644 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(), 1645 false, false, false, 1646 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8); 1647} 1648 1649static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1650 SDValue Chain = Op.getOperand(0); // Legalize the chain. 1651 SDValue Size = Op.getOperand(1); // Legalize the size. 1652 DebugLoc dl = Op.getDebugLoc(); 1653 1654 unsigned SPReg = SP::O6; 1655 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 1656 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 1657 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 1658 1659 // The resultant pointer is actually 16 words from the bottom of the stack, 1660 // to provide a register spill area. 1661 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 1662 DAG.getConstant(96, MVT::i32)); 1663 SDValue Ops[2] = { NewVal, Chain }; 1664 return DAG.getMergeValues(Ops, 2, dl); 1665} 1666 1667 1668static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 1669 DebugLoc dl = Op.getDebugLoc(); 1670 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 1671 dl, MVT::Other, DAG.getEntryNode()); 1672 return Chain; 1673} 1674 1675static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1676 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1677 MFI->setFrameAddressIsTaken(true); 1678 1679 EVT VT = Op.getValueType(); 1680 DebugLoc dl = Op.getDebugLoc(); 1681 unsigned FrameReg = SP::I6; 1682 1683 uint64_t depth = Op.getConstantOperandVal(0); 1684 1685 SDValue FrameAddr; 1686 if (depth == 0) 1687 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1688 else { 1689 // flush first to make sure the windowed registers' values are in stack 1690 SDValue Chain = getFLUSHW(Op, DAG); 1691 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 1692 1693 for (uint64_t i = 0; i != depth; ++i) { 1694 SDValue Ptr = DAG.getNode(ISD::ADD, 1695 dl, MVT::i32, 1696 FrameAddr, DAG.getIntPtrConstant(56)); 1697 FrameAddr = DAG.getLoad(MVT::i32, dl, 1698 Chain, 1699 Ptr, 1700 MachinePointerInfo(), false, false, false, 0); 1701 } 1702 } 1703 return FrameAddr; 1704} 1705 1706static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 1707 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1708 MFI->setReturnAddressIsTaken(true); 1709 1710 EVT VT = Op.getValueType(); 1711 DebugLoc dl = Op.getDebugLoc(); 1712 unsigned RetReg = SP::I7; 1713 1714 uint64_t depth = Op.getConstantOperandVal(0); 1715 1716 SDValue RetAddr; 1717 if (depth == 0) 1718 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 1719 else { 1720 // flush first to make sure the windowed registers' values are in stack 1721 SDValue Chain = getFLUSHW(Op, DAG); 1722 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 1723 1724 for (uint64_t i = 0; i != depth; ++i) { 1725 SDValue Ptr = DAG.getNode(ISD::ADD, 1726 dl, MVT::i32, 1727 RetAddr, 1728 DAG.getIntPtrConstant((i == depth-1)?60:56)); 1729 RetAddr = DAG.getLoad(MVT::i32, dl, 1730 Chain, 1731 Ptr, 1732 MachinePointerInfo(), false, false, false, 0); 1733 } 1734 } 1735 return RetAddr; 1736} 1737 1738SDValue SparcTargetLowering:: 1739LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1740 switch (Op.getOpcode()) { 1741 default: llvm_unreachable("Should not custom lower this!"); 1742 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1743 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1744 case ISD::GlobalTLSAddress: 1745 llvm_unreachable("TLS not implemented for Sparc."); 1746 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1747 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1748 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1749 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1750 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1751 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1752 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 1753 case ISD::VAARG: return LowerVAARG(Op, DAG); 1754 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1755 } 1756} 1757 1758MachineBasicBlock * 1759SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1760 MachineBasicBlock *BB) const { 1761 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1762 unsigned BROpcode; 1763 unsigned CC; 1764 DebugLoc dl = MI->getDebugLoc(); 1765 // Figure out the conditional branch opcode to use for this select_cc. 1766 switch (MI->getOpcode()) { 1767 default: llvm_unreachable("Unknown SELECT_CC!"); 1768 case SP::SELECT_CC_Int_ICC: 1769 case SP::SELECT_CC_FP_ICC: 1770 case SP::SELECT_CC_DFP_ICC: 1771 BROpcode = SP::BCOND; 1772 break; 1773 case SP::SELECT_CC_Int_FCC: 1774 case SP::SELECT_CC_FP_FCC: 1775 case SP::SELECT_CC_DFP_FCC: 1776 BROpcode = SP::FBCOND; 1777 break; 1778 } 1779 1780 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 1781 1782 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1783 // control-flow pattern. The incoming instruction knows the destination vreg 1784 // to set, the condition code register to branch on, the true/false values to 1785 // select between, and a branch opcode to use. 1786 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1787 MachineFunction::iterator It = BB; 1788 ++It; 1789 1790 // thisMBB: 1791 // ... 1792 // TrueVal = ... 1793 // [f]bCC copy1MBB 1794 // fallthrough --> copy0MBB 1795 MachineBasicBlock *thisMBB = BB; 1796 MachineFunction *F = BB->getParent(); 1797 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1798 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1799 F->insert(It, copy0MBB); 1800 F->insert(It, sinkMBB); 1801 1802 // Transfer the remainder of BB and its successor edges to sinkMBB. 1803 sinkMBB->splice(sinkMBB->begin(), BB, 1804 llvm::next(MachineBasicBlock::iterator(MI)), 1805 BB->end()); 1806 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1807 1808 // Add the true and fallthrough blocks as its successors. 1809 BB->addSuccessor(copy0MBB); 1810 BB->addSuccessor(sinkMBB); 1811 1812 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1813 1814 // copy0MBB: 1815 // %FalseValue = ... 1816 // # fallthrough to sinkMBB 1817 BB = copy0MBB; 1818 1819 // Update machine-CFG edges 1820 BB->addSuccessor(sinkMBB); 1821 1822 // sinkMBB: 1823 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1824 // ... 1825 BB = sinkMBB; 1826 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1827 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1828 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1829 1830 MI->eraseFromParent(); // The pseudo instruction is gone now. 1831 return BB; 1832} 1833 1834//===----------------------------------------------------------------------===// 1835// Sparc Inline Assembly Support 1836//===----------------------------------------------------------------------===// 1837 1838/// getConstraintType - Given a constraint letter, return the type of 1839/// constraint it is for this target. 1840SparcTargetLowering::ConstraintType 1841SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1842 if (Constraint.size() == 1) { 1843 switch (Constraint[0]) { 1844 default: break; 1845 case 'r': return C_RegisterClass; 1846 } 1847 } 1848 1849 return TargetLowering::getConstraintType(Constraint); 1850} 1851 1852std::pair<unsigned, const TargetRegisterClass*> 1853SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1854 EVT VT) const { 1855 if (Constraint.size() == 1) { 1856 switch (Constraint[0]) { 1857 case 'r': 1858 return std::make_pair(0U, &SP::IntRegsRegClass); 1859 } 1860 } 1861 1862 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1863} 1864 1865bool 1866SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1867 // The Sparc target isn't yet aware of offsets. 1868 return false; 1869} 1870