SparcISelLowering.cpp revision 98949a6d2c42e386f36b5fd94cb97008a51b610f
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcTargetMachine.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/CallingConvLower.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24using namespace llvm; 25 26 27//===----------------------------------------------------------------------===// 28// Calling Convention Implementation 29//===----------------------------------------------------------------------===// 30 31#include "SparcGenCallingConv.inc" 32 33static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 34 // CCValAssign - represent the assignment of the return value to locations. 35 SmallVector<CCValAssign, 16> RVLocs; 36 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 37 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 38 39 // CCState - Info about the registers and stack slot. 40 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs); 41 42 // Analize return values of ISD::RET 43 CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32); 44 45 // If this is the first return lowered for this function, add the regs to the 46 // liveout set for the function. 47 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 48 for (unsigned i = 0; i != RVLocs.size(); ++i) 49 if (RVLocs[i].isRegLoc()) 50 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 51 } 52 53 SDOperand Chain = Op.getOperand(0); 54 SDOperand Flag; 55 56 // Copy the result values into the output registers. 57 for (unsigned i = 0; i != RVLocs.size(); ++i) { 58 CCValAssign &VA = RVLocs[i]; 59 assert(VA.isRegLoc() && "Can only return in registers!"); 60 61 // ISD::RET => ret chain, (regnum1,val1), ... 62 // So i*2+1 index only the regnums. 63 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 64 65 // Guarantee that all emitted copies are stuck together with flags. 66 Flag = Chain.getValue(1); 67 } 68 69 if (Flag.Val) 70 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag); 71 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain); 72} 73 74/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 75/// either one or two GPRs, including FP values. TODO: we should pass FP values 76/// in FP registers for fastcc functions. 77std::vector<SDOperand> 78SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 79 MachineFunction &MF = DAG.getMachineFunction(); 80 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 81 std::vector<SDOperand> ArgValues; 82 83 static const unsigned ArgRegs[] = { 84 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 85 }; 86 87 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 88 unsigned ArgOffset = 68; 89 90 SDOperand Root = DAG.getRoot(); 91 std::vector<SDOperand> OutChains; 92 93 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 94 MVT::ValueType ObjectVT = getValueType(I->getType()); 95 96 switch (ObjectVT) { 97 default: assert(0 && "Unhandled argument type!"); 98 case MVT::i1: 99 case MVT::i8: 100 case MVT::i16: 101 case MVT::i32: 102 if (I->use_empty()) { // Argument is dead. 103 if (CurArgReg < ArgRegEnd) ++CurArgReg; 104 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 105 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 106 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 107 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 108 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 109 if (ObjectVT != MVT::i32) { 110 unsigned AssertOp = ISD::AssertSext; 111 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 112 DAG.getValueType(ObjectVT)); 113 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 114 } 115 ArgValues.push_back(Arg); 116 } else { 117 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 118 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 119 SDOperand Load; 120 if (ObjectVT == MVT::i32) { 121 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 122 } else { 123 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 124 125 // Sparc is big endian, so add an offset based on the ObjectVT. 126 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 127 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 128 DAG.getConstant(Offset, MVT::i32)); 129 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 130 NULL, 0, ObjectVT); 131 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 132 } 133 ArgValues.push_back(Load); 134 } 135 136 ArgOffset += 4; 137 break; 138 case MVT::f32: 139 if (I->use_empty()) { // Argument is dead. 140 if (CurArgReg < ArgRegEnd) ++CurArgReg; 141 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 142 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 143 // FP value is passed in an integer register. 144 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 145 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 146 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 147 148 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 149 ArgValues.push_back(Arg); 150 } else { 151 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 152 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 153 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 154 ArgValues.push_back(Load); 155 } 156 ArgOffset += 4; 157 break; 158 159 case MVT::i64: 160 case MVT::f64: 161 if (I->use_empty()) { // Argument is dead. 162 if (CurArgReg < ArgRegEnd) ++CurArgReg; 163 if (CurArgReg < ArgRegEnd) ++CurArgReg; 164 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 165 } else if (/* FIXME: Apparently this isn't safe?? */ 166 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 167 ((CurArgReg-ArgRegs) & 1) == 0) { 168 // If this is a double argument and the whole thing lives on the stack, 169 // and the argument is aligned, load the double straight from the stack. 170 // We can't do a load in cases like void foo([6ints], int,double), 171 // because the double wouldn't be aligned! 172 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 173 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 174 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 175 } else { 176 SDOperand HiVal; 177 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 178 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 179 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 180 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 181 } else { 182 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 183 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 184 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 185 } 186 187 SDOperand LoVal; 188 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 189 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 190 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 191 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 192 } else { 193 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 194 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 195 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 196 } 197 198 // Compose the two halves together into an i64 unit. 199 SDOperand WholeValue = 200 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 201 202 // If we want a double, do a bit convert. 203 if (ObjectVT == MVT::f64) 204 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 205 206 ArgValues.push_back(WholeValue); 207 } 208 ArgOffset += 8; 209 break; 210 } 211 } 212 213 // Store remaining ArgRegs to the stack if this is a varargs function. 214 if (F.isVarArg()) { 215 // Remember the vararg offset for the va_start implementation. 216 VarArgsFrameOffset = ArgOffset; 217 218 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 219 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 220 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 221 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 222 223 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 224 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 225 226 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 227 ArgOffset += 4; 228 } 229 } 230 231 if (!OutChains.empty()) 232 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 233 &OutChains[0], OutChains.size())); 234 235 return ArgValues; 236} 237 238static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { 239 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 240 SDOperand Chain = Op.getOperand(0); 241 SDOperand Callee = Op.getOperand(4); 242 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 243 244 // Count the size of the outgoing arguments. 245 unsigned ArgsSize = 0; 246 for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { 247 switch (Op.getOperand(i).getValueType()) { 248 default: assert(0 && "Unknown value type!"); 249 case MVT::i1: 250 case MVT::i8: 251 case MVT::i16: 252 case MVT::i32: 253 case MVT::f32: 254 ArgsSize += 4; 255 break; 256 case MVT::i64: 257 case MVT::f64: 258 ArgsSize += 8; 259 break; 260 } 261 } 262 if (ArgsSize > 4*6) 263 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 264 else 265 ArgsSize = 0; 266 267 // Keep stack frames 8-byte aligned. 268 ArgsSize = (ArgsSize+7) & ~7; 269 270 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, MVT::i32)); 271 272 SDOperand StackPtr; 273 std::vector<SDOperand> Stores; 274 std::vector<SDOperand> RegValuesToPass; 275 unsigned ArgOffset = 68; 276 for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { 277 SDOperand Val = Op.getOperand(i); 278 MVT::ValueType ObjectVT = Val.getValueType(); 279 SDOperand ValToStore(0, 0); 280 unsigned ObjSize; 281 switch (ObjectVT) { 282 default: assert(0 && "Unhandled argument type!"); 283 case MVT::i1: 284 case MVT::i8: 285 case MVT::i16: { 286 assert(0 && "unreach"); 287 // Promote the integer to 32-bits. If the input type is signed, use a 288 // sign extend, otherwise use a zero extend. 289 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 290 if (Op.getConstantOperandVal(i+1) & 1) 291 ExtendKind = ISD::SIGN_EXTEND; 292 else 293 ExtendKind = ISD::ZERO_EXTEND; 294 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 295 // FALL THROUGH 296 } 297 case MVT::i32: 298 ObjSize = 4; 299 300 if (RegValuesToPass.size() >= 6) { 301 ValToStore = Val; 302 } else { 303 RegValuesToPass.push_back(Val); 304 } 305 break; 306 case MVT::f32: 307 ObjSize = 4; 308 if (RegValuesToPass.size() >= 6) { 309 ValToStore = Val; 310 } else { 311 // Convert this to a FP value in an int reg. 312 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 313 RegValuesToPass.push_back(Val); 314 } 315 break; 316 case MVT::f64: 317 ObjSize = 8; 318 // If we can store this directly into the outgoing slot, do so. We can 319 // do this when all ArgRegs are used and if the outgoing slot is aligned. 320 // FIXME: McGill/misr fails with this. 321 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 322 ValToStore = Val; 323 break; 324 } 325 326 // Otherwise, convert this to a FP value in int regs. 327 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 328 // FALL THROUGH 329 case MVT::i64: 330 ObjSize = 8; 331 if (RegValuesToPass.size() >= 6) { 332 ValToStore = Val; // Whole thing is passed in memory. 333 break; 334 } 335 336 // Split the value into top and bottom part. Top part goes in a reg. 337 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 338 DAG.getConstant(1, MVT::i32)); 339 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 340 DAG.getConstant(0, MVT::i32)); 341 RegValuesToPass.push_back(Hi); 342 343 if (RegValuesToPass.size() >= 6) { 344 ValToStore = Lo; 345 ArgOffset += 4; 346 ObjSize = 4; 347 } else { 348 RegValuesToPass.push_back(Lo); 349 } 350 break; 351 } 352 353 if (ValToStore.Val) { 354 if (!StackPtr.Val) { 355 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 356 } 357 SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32); 358 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 359 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 360 } 361 ArgOffset += ObjSize; 362 } 363 364 // Emit all stores, make sure the occur before any copies into physregs. 365 if (!Stores.empty()) 366 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 367 368 static const unsigned ArgRegs[] = { 369 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 370 }; 371 372 // Build a sequence of copy-to-reg nodes chained together with token chain 373 // and flag operands which copy the outgoing args into O[0-5]. 374 SDOperand InFlag; 375 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 376 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 377 InFlag = Chain.getValue(1); 378 } 379 380 // If the callee is a GlobalAddress node (quite common, every direct call is) 381 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 382 // Likewise ExternalSymbol -> TargetExternalSymbol. 383 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 384 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 385 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 386 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 387 388 std::vector<MVT::ValueType> NodeTys; 389 NodeTys.push_back(MVT::Other); // Returns a chain 390 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 391 SDOperand Ops[] = { Chain, Callee, InFlag }; 392 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 393 InFlag = Chain.getValue(1); 394 395 Chain = DAG.getCALLSEQ_END(Chain, 396 DAG.getConstant(ArgsSize, MVT::i32), 397 DAG.getConstant(0, MVT::i32), InFlag); 398 InFlag = Chain.getValue(1); 399 400 // Assign locations to each value returned by this call. 401 SmallVector<CCValAssign, 16> RVLocs; 402 CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs); 403 404 CCInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32); 405 SmallVector<SDOperand, 8> ResultVals; 406 407 // Copy all of the result registers out of their specified physreg. 408 for (unsigned i = 0; i != RVLocs.size(); ++i) { 409 unsigned Reg = RVLocs[i].getLocReg(); 410 411 // Remap I0->I7 -> O0->O7. 412 if (Reg >= SP::I0 && Reg <= SP::I7) 413 Reg = Reg-SP::I0+SP::O0; 414 415 Chain = DAG.getCopyFromReg(Chain, Reg, 416 RVLocs[i].getValVT(), InFlag).getValue(1); 417 InFlag = Chain.getValue(2); 418 ResultVals.push_back(Chain.getValue(0)); 419 } 420 421 ResultVals.push_back(Chain); 422 423 // Merge everything together with a MERGE_VALUES node. 424 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 425 &ResultVals[0], ResultVals.size()); 426} 427 428 429 430//===----------------------------------------------------------------------===// 431// TargetLowering Implementation 432//===----------------------------------------------------------------------===// 433 434/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 435/// condition. 436static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 437 switch (CC) { 438 default: assert(0 && "Unknown integer condition code!"); 439 case ISD::SETEQ: return SPCC::ICC_E; 440 case ISD::SETNE: return SPCC::ICC_NE; 441 case ISD::SETLT: return SPCC::ICC_L; 442 case ISD::SETGT: return SPCC::ICC_G; 443 case ISD::SETLE: return SPCC::ICC_LE; 444 case ISD::SETGE: return SPCC::ICC_GE; 445 case ISD::SETULT: return SPCC::ICC_CS; 446 case ISD::SETULE: return SPCC::ICC_LEU; 447 case ISD::SETUGT: return SPCC::ICC_GU; 448 case ISD::SETUGE: return SPCC::ICC_CC; 449 } 450} 451 452/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 453/// FCC condition. 454static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 455 switch (CC) { 456 default: assert(0 && "Unknown fp condition code!"); 457 case ISD::SETEQ: 458 case ISD::SETOEQ: return SPCC::FCC_E; 459 case ISD::SETNE: 460 case ISD::SETUNE: return SPCC::FCC_NE; 461 case ISD::SETLT: 462 case ISD::SETOLT: return SPCC::FCC_L; 463 case ISD::SETGT: 464 case ISD::SETOGT: return SPCC::FCC_G; 465 case ISD::SETLE: 466 case ISD::SETOLE: return SPCC::FCC_LE; 467 case ISD::SETGE: 468 case ISD::SETOGE: return SPCC::FCC_GE; 469 case ISD::SETULT: return SPCC::FCC_UL; 470 case ISD::SETULE: return SPCC::FCC_ULE; 471 case ISD::SETUGT: return SPCC::FCC_UG; 472 case ISD::SETUGE: return SPCC::FCC_UGE; 473 case ISD::SETUO: return SPCC::FCC_U; 474 case ISD::SETO: return SPCC::FCC_O; 475 case ISD::SETONE: return SPCC::FCC_LG; 476 case ISD::SETUEQ: return SPCC::FCC_UE; 477 } 478} 479 480 481SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 482 : TargetLowering(TM) { 483 484 // Set up the register classes. 485 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 486 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 487 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 488 489 // Turn FP extload into load/fextend 490 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 491 // Sparc doesn't have i1 sign extending load 492 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 493 // Turn FP truncstore into trunc + store. 494 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 495 496 // Custom legalize GlobalAddress nodes into LO/HI parts. 497 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 498 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 499 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 500 501 // Sparc doesn't have sext_inreg, replace them with shl/sra 502 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 503 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 504 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 505 506 // Sparc has no REM or DIVREM operations. 507 setOperationAction(ISD::UREM, MVT::i32, Expand); 508 setOperationAction(ISD::SREM, MVT::i32, Expand); 509 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 510 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 511 512 // Custom expand fp<->sint 513 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 514 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 515 516 // Expand fp<->uint 517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 518 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 519 520 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 521 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 522 523 // Sparc has no select or setcc: expand to SELECT_CC. 524 setOperationAction(ISD::SELECT, MVT::i32, Expand); 525 setOperationAction(ISD::SELECT, MVT::f32, Expand); 526 setOperationAction(ISD::SELECT, MVT::f64, Expand); 527 setOperationAction(ISD::SETCC, MVT::i32, Expand); 528 setOperationAction(ISD::SETCC, MVT::f32, Expand); 529 setOperationAction(ISD::SETCC, MVT::f64, Expand); 530 531 // Sparc doesn't have BRCOND either, it has BR_CC. 532 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 533 setOperationAction(ISD::BRIND, MVT::Other, Expand); 534 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 535 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 536 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 537 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 538 539 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 540 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 541 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 542 543 // SPARC has no intrinsics for these particular operations. 544 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 545 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 546 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 547 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 548 549 setOperationAction(ISD::FSIN , MVT::f64, Expand); 550 setOperationAction(ISD::FCOS , MVT::f64, Expand); 551 setOperationAction(ISD::FREM , MVT::f64, Expand); 552 setOperationAction(ISD::FSIN , MVT::f32, Expand); 553 setOperationAction(ISD::FCOS , MVT::f32, Expand); 554 setOperationAction(ISD::FREM , MVT::f32, Expand); 555 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 556 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 557 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 558 setOperationAction(ISD::ROTL , MVT::i32, Expand); 559 setOperationAction(ISD::ROTR , MVT::i32, Expand); 560 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 561 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 562 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 563 setOperationAction(ISD::FPOW , MVT::f64, Expand); 564 setOperationAction(ISD::FPOW , MVT::f32, Expand); 565 566 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 567 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 568 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 569 570 // FIXME: Sparc provides these multiplies, but we don't have them yet. 571 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 572 573 // We don't have line number support yet. 574 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 575 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 576 setOperationAction(ISD::LABEL, MVT::Other, Expand); 577 578 // RET must be custom lowered, to meet ABI requirements 579 setOperationAction(ISD::RET , MVT::Other, Custom); 580 581 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 582 setOperationAction(ISD::VASTART , MVT::Other, Custom); 583 // VAARG needs to be lowered to not do unaligned accesses for doubles. 584 setOperationAction(ISD::VAARG , MVT::Other, Custom); 585 586 // Use the default implementation. 587 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 588 setOperationAction(ISD::VAEND , MVT::Other, Expand); 589 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 590 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 591 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 592 593 // No debug info support yet. 594 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 595 setOperationAction(ISD::LABEL, MVT::Other, Expand); 596 setOperationAction(ISD::DECLARE, MVT::Other, Expand); 597 598 setStackPointerRegisterToSaveRestore(SP::O6); 599 600 if (TM.getSubtarget<SparcSubtarget>().isV9()) 601 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 602 603 computeRegisterProperties(); 604} 605 606const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 607 switch (Opcode) { 608 default: return 0; 609 case SPISD::CMPICC: return "SPISD::CMPICC"; 610 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 611 case SPISD::BRICC: return "SPISD::BRICC"; 612 case SPISD::BRFCC: return "SPISD::BRFCC"; 613 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 614 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 615 case SPISD::Hi: return "SPISD::Hi"; 616 case SPISD::Lo: return "SPISD::Lo"; 617 case SPISD::FTOI: return "SPISD::FTOI"; 618 case SPISD::ITOF: return "SPISD::ITOF"; 619 case SPISD::CALL: return "SPISD::CALL"; 620 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 621 } 622} 623 624/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 625/// be zero. Op is expected to be a target specific node. Used by DAG 626/// combiner. 627void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 628 const APInt &Mask, 629 APInt &KnownZero, 630 APInt &KnownOne, 631 const SelectionDAG &DAG, 632 unsigned Depth) const { 633 APInt KnownZero2, KnownOne2; 634 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 635 636 switch (Op.getOpcode()) { 637 default: break; 638 case SPISD::SELECT_ICC: 639 case SPISD::SELECT_FCC: 640 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 641 Depth+1); 642 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 643 Depth+1); 644 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 645 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 646 647 // Only known if known in both the LHS and RHS. 648 KnownOne &= KnownOne2; 649 KnownZero &= KnownZero2; 650 break; 651 } 652} 653 654// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 655// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 656static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 657 ISD::CondCode CC, unsigned &SPCC) { 658 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 659 CC == ISD::SETNE && 660 ((LHS.getOpcode() == SPISD::SELECT_ICC && 661 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 662 (LHS.getOpcode() == SPISD::SELECT_FCC && 663 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 664 isa<ConstantSDNode>(LHS.getOperand(0)) && 665 isa<ConstantSDNode>(LHS.getOperand(1)) && 666 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 667 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 668 SDOperand CMPCC = LHS.getOperand(3); 669 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 670 LHS = CMPCC.getOperand(0); 671 RHS = CMPCC.getOperand(1); 672 } 673} 674 675static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) { 676 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 677 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 678 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 679 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 680 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 681} 682 683static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) { 684 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 685 Constant *C = N->getConstVal(); 686 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 687 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 688 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 689 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 690} 691 692static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 693 // Convert the fp value to integer in an FP register. 694 assert(Op.getValueType() == MVT::i32); 695 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 696 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 697} 698 699static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 700 assert(Op.getOperand(0).getValueType() == MVT::i32); 701 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 702 // Convert the int value to FP in an FP register. 703 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 704} 705 706static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { 707 SDOperand Chain = Op.getOperand(0); 708 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 709 SDOperand LHS = Op.getOperand(2); 710 SDOperand RHS = Op.getOperand(3); 711 SDOperand Dest = Op.getOperand(4); 712 unsigned Opc, SPCC = ~0U; 713 714 // If this is a br_cc of a "setcc", and if the setcc got lowered into 715 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 716 LookThroughSetCC(LHS, RHS, CC, SPCC); 717 718 // Get the condition flag. 719 SDOperand CompareFlag; 720 if (LHS.getValueType() == MVT::i32) { 721 std::vector<MVT::ValueType> VTs; 722 VTs.push_back(MVT::i32); 723 VTs.push_back(MVT::Flag); 724 SDOperand Ops[2] = { LHS, RHS }; 725 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 726 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 727 Opc = SPISD::BRICC; 728 } else { 729 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 730 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 731 Opc = SPISD::BRFCC; 732 } 733 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 734 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 735} 736 737static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 738 SDOperand LHS = Op.getOperand(0); 739 SDOperand RHS = Op.getOperand(1); 740 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 741 SDOperand TrueVal = Op.getOperand(2); 742 SDOperand FalseVal = Op.getOperand(3); 743 unsigned Opc, SPCC = ~0U; 744 745 // If this is a select_cc of a "setcc", and if the setcc got lowered into 746 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 747 LookThroughSetCC(LHS, RHS, CC, SPCC); 748 749 SDOperand CompareFlag; 750 if (LHS.getValueType() == MVT::i32) { 751 std::vector<MVT::ValueType> VTs; 752 VTs.push_back(LHS.getValueType()); // subcc returns a value 753 VTs.push_back(MVT::Flag); 754 SDOperand Ops[2] = { LHS, RHS }; 755 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 756 Opc = SPISD::SELECT_ICC; 757 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 758 } else { 759 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 760 Opc = SPISD::SELECT_FCC; 761 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 762 } 763 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 764 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 765} 766 767static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 768 SparcTargetLowering &TLI) { 769 // vastart just stores the address of the VarArgsFrameIndex slot into the 770 // memory location argument. 771 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 772 DAG.getRegister(SP::I6, MVT::i32), 773 DAG.getConstant(TLI.getVarArgsFrameOffset(), 774 MVT::i32)); 775 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 776 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); 777} 778 779static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) { 780 SDNode *Node = Op.Val; 781 MVT::ValueType VT = Node->getValueType(0); 782 SDOperand InChain = Node->getOperand(0); 783 SDOperand VAListPtr = Node->getOperand(1); 784 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 785 SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); 786 // Increment the pointer, VAList, to the next vaarg 787 SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, 788 DAG.getConstant(MVT::getSizeInBits(VT)/8, 789 MVT::i32)); 790 // Store the incremented VAList to the legalized pointer 791 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 792 VAListPtr, SV, 0); 793 // Load the actual argument out of the pointer VAList, unless this is an 794 // f64 load. 795 if (VT != MVT::f64) 796 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 797 798 // Otherwise, load it as i64, then do a bitconvert. 799 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 800 801 // Bit-Convert the value to f64. 802 SDOperand Ops[2] = { 803 DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 804 V.getValue(1) 805 }; 806 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::f64, MVT::Other), 807 Ops, 2); 808} 809 810static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) { 811 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 812 SDOperand Size = Op.getOperand(1); // Legalize the size. 813 814 unsigned SPReg = SP::O6; 815 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 816 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 817 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 818 819 // The resultant pointer is actually 16 words from the bottom of the stack, 820 // to provide a register spill area. 821 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 822 DAG.getConstant(96, MVT::i32)); 823 std::vector<MVT::ValueType> Tys; 824 Tys.push_back(MVT::i32); 825 Tys.push_back(MVT::Other); 826 SDOperand Ops[2] = { NewVal, Chain }; 827 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 828} 829 830 831SDOperand SparcTargetLowering:: 832LowerOperation(SDOperand Op, SelectionDAG &DAG) { 833 switch (Op.getOpcode()) { 834 default: assert(0 && "Should not custom lower this!"); 835 // Frame & Return address. Currently unimplemented 836 case ISD::RETURNADDR: return SDOperand(); 837 case ISD::FRAMEADDR: return SDOperand(); 838 case ISD::GlobalTLSAddress: 839 assert(0 && "TLS not implemented for Sparc."); 840 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 841 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG); 842 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 843 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 844 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 845 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 846 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 847 case ISD::VAARG: return LowerVAARG(Op, DAG); 848 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 849 case ISD::CALL: return LowerCALL(Op, DAG); 850 case ISD::RET: return LowerRET(Op, DAG); 851 } 852} 853 854MachineBasicBlock * 855SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 856 MachineBasicBlock *BB) { 857 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 858 unsigned BROpcode; 859 unsigned CC; 860 // Figure out the conditional branch opcode to use for this select_cc. 861 switch (MI->getOpcode()) { 862 default: assert(0 && "Unknown SELECT_CC!"); 863 case SP::SELECT_CC_Int_ICC: 864 case SP::SELECT_CC_FP_ICC: 865 case SP::SELECT_CC_DFP_ICC: 866 BROpcode = SP::BCOND; 867 break; 868 case SP::SELECT_CC_Int_FCC: 869 case SP::SELECT_CC_FP_FCC: 870 case SP::SELECT_CC_DFP_FCC: 871 BROpcode = SP::FBCOND; 872 break; 873 } 874 875 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 876 877 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 878 // control-flow pattern. The incoming instruction knows the destination vreg 879 // to set, the condition code register to branch on, the true/false values to 880 // select between, and a branch opcode to use. 881 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 882 ilist<MachineBasicBlock>::iterator It = BB; 883 ++It; 884 885 // thisMBB: 886 // ... 887 // TrueVal = ... 888 // [f]bCC copy1MBB 889 // fallthrough --> copy0MBB 890 MachineBasicBlock *thisMBB = BB; 891 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 892 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 893 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 894 MachineFunction *F = BB->getParent(); 895 F->getBasicBlockList().insert(It, copy0MBB); 896 F->getBasicBlockList().insert(It, sinkMBB); 897 // Update machine-CFG edges by first adding all successors of the current 898 // block to the new block which will contain the Phi node for the select. 899 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 900 e = BB->succ_end(); i != e; ++i) 901 sinkMBB->addSuccessor(*i); 902 // Next, remove all successors of the current block, and add the true 903 // and fallthrough blocks as its successors. 904 while(!BB->succ_empty()) 905 BB->removeSuccessor(BB->succ_begin()); 906 BB->addSuccessor(copy0MBB); 907 BB->addSuccessor(sinkMBB); 908 909 // copy0MBB: 910 // %FalseValue = ... 911 // # fallthrough to sinkMBB 912 BB = copy0MBB; 913 914 // Update machine-CFG edges 915 BB->addSuccessor(sinkMBB); 916 917 // sinkMBB: 918 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 919 // ... 920 BB = sinkMBB; 921 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 922 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 923 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 924 925 delete MI; // The pseudo instruction is gone now. 926 return BB; 927} 928 929