SparcISelLowering.cpp revision b26bc75213563f594416fae906010ded242eaf3e 
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "SparcTargetMachine.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24using namespace llvm;
25
26
27//===----------------------------------------------------------------------===//
28// Calling Convention Implementation
29//===----------------------------------------------------------------------===//
30
31#include "SparcGenCallingConv.inc"
32
33static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
34  // CCValAssign - represent the assignment of the return value to locations.
35  SmallVector<CCValAssign, 16> RVLocs;
36  unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
37  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
38
39  // CCState - Info about the registers and stack slot.
40  CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
41
42  // Analize return values of ISD::RET
43  CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32);
44
45  // If this is the first return lowered for this function, add the regs to the
46  // liveout set for the function.
47  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
48    for (unsigned i = 0; i != RVLocs.size(); ++i)
49      if (RVLocs[i].isRegLoc())
50        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
51  }
52
53  SDOperand Chain = Op.getOperand(0);
54  SDOperand Flag;
55
56  // Copy the result values into the output registers.
57  for (unsigned i = 0; i != RVLocs.size(); ++i) {
58    CCValAssign &VA = RVLocs[i];
59    assert(VA.isRegLoc() && "Can only return in registers!");
60
61    // ISD::RET => ret chain, (regnum1,val1), ...
62    // So i*2+1 index only the regnums.
63    Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
64
65    // Guarantee that all emitted copies are stuck together with flags.
66    Flag = Chain.getValue(1);
67  }
68
69  if (Flag.Val)
70    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
71  return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
72}
73
74/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
75/// either one or two GPRs, including FP values.  TODO: we should pass FP values
76/// in FP registers for fastcc functions.
77std::vector<SDOperand>
78SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
79  MachineFunction &MF = DAG.getMachineFunction();
80  MachineRegisterInfo &RegInfo = MF.getRegInfo();
81  std::vector<SDOperand> ArgValues;
82
83  static const unsigned ArgRegs[] = {
84    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
85  };
86
87  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
88  unsigned ArgOffset = 68;
89
90  SDOperand Root = DAG.getRoot();
91  std::vector<SDOperand> OutChains;
92
93  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
94    MVT::ValueType ObjectVT = getValueType(I->getType());
95
96    switch (ObjectVT) {
97    default: assert(0 && "Unhandled argument type!");
98    case MVT::i1:
99    case MVT::i8:
100    case MVT::i16:
101    case MVT::i32:
102      if (I->use_empty()) {                // Argument is dead.
103        if (CurArgReg < ArgRegEnd) ++CurArgReg;
104        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
105      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
106        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
107        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
108        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
109        if (ObjectVT != MVT::i32) {
110          unsigned AssertOp = ISD::AssertSext;
111          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
112                            DAG.getValueType(ObjectVT));
113          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
114        }
115        ArgValues.push_back(Arg);
116      } else {
117        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
118        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
119        SDOperand Load;
120        if (ObjectVT == MVT::i32) {
121          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
122        } else {
123          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
124
125          // Sparc is big endian, so add an offset based on the ObjectVT.
126          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
127          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
128                              DAG.getConstant(Offset, MVT::i32));
129          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
130                                NULL, 0, ObjectVT);
131          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
132        }
133        ArgValues.push_back(Load);
134      }
135
136      ArgOffset += 4;
137      break;
138    case MVT::f32:
139      if (I->use_empty()) {                // Argument is dead.
140        if (CurArgReg < ArgRegEnd) ++CurArgReg;
141        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
142      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
143        // FP value is passed in an integer register.
144        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
145        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
146        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
147
148        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
149        ArgValues.push_back(Arg);
150      } else {
151        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
152        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
153        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
154        ArgValues.push_back(Load);
155      }
156      ArgOffset += 4;
157      break;
158
159    case MVT::i64:
160    case MVT::f64:
161      if (I->use_empty()) {                // Argument is dead.
162        if (CurArgReg < ArgRegEnd) ++CurArgReg;
163        if (CurArgReg < ArgRegEnd) ++CurArgReg;
164        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
165      } else {
166        SDOperand HiVal;
167        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
168          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
169          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
170          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
171        } else {
172          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
173          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
174          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
175        }
176
177        SDOperand LoVal;
178        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
179          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
180          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
181          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
182        } else {
183          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
184          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
185          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
186        }
187
188        // Compose the two halves together into an i64 unit.
189        SDOperand WholeValue =
190          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
191
192        // If we want a double, do a bit convert.
193        if (ObjectVT == MVT::f64)
194          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
195
196        ArgValues.push_back(WholeValue);
197      }
198      ArgOffset += 8;
199      break;
200    }
201  }
202
203  // Store remaining ArgRegs to the stack if this is a varargs function.
204  if (F.isVarArg()) {
205    // Remember the vararg offset for the va_start implementation.
206    VarArgsFrameOffset = ArgOffset;
207
208    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
209      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
210      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
211      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
212
213      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
214      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
215
216      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
217      ArgOffset += 4;
218    }
219  }
220
221  if (!OutChains.empty())
222    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
223                            &OutChains[0], OutChains.size()));
224
225  return ArgValues;
226}
227
228static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
229  unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
230  SDOperand Chain = Op.getOperand(0);
231  SDOperand Callee = Op.getOperand(4);
232  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
233
234  // Count the size of the outgoing arguments.
235  unsigned ArgsSize = 0;
236  for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
237    switch (Op.getOperand(i).getValueType()) {
238    default: assert(0 && "Unknown value type!");
239    case MVT::i1:
240    case MVT::i8:
241    case MVT::i16:
242    case MVT::i32:
243    case MVT::f32:
244      ArgsSize += 4;
245      break;
246    case MVT::i64:
247    case MVT::f64:
248      ArgsSize += 8;
249      break;
250    }
251  }
252  if (ArgsSize > 4*6)
253    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
254  else
255    ArgsSize = 0;
256
257  // Keep stack frames 8-byte aligned.
258  ArgsSize = (ArgsSize+7) & ~7;
259
260  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, MVT::i32));
261
262  SDOperand StackPtr;
263  std::vector<SDOperand> Stores;
264  std::vector<SDOperand> RegValuesToPass;
265  unsigned ArgOffset = 68;
266  for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
267    SDOperand Val = Op.getOperand(i);
268    MVT::ValueType ObjectVT = Val.getValueType();
269    SDOperand ValToStore(0, 0);
270    unsigned ObjSize;
271    switch (ObjectVT) {
272    default: assert(0 && "Unhandled argument type!");
273    case MVT::i32:
274      ObjSize = 4;
275
276      if (RegValuesToPass.size() >= 6) {
277        ValToStore = Val;
278      } else {
279        RegValuesToPass.push_back(Val);
280      }
281      break;
282    case MVT::f32:
283      ObjSize = 4;
284      if (RegValuesToPass.size() >= 6) {
285        ValToStore = Val;
286      } else {
287        // Convert this to a FP value in an int reg.
288        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
289        RegValuesToPass.push_back(Val);
290      }
291      break;
292    case MVT::f64:
293      ObjSize = 8;
294      // Otherwise, convert this to a FP value in int regs.
295      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
296      // FALL THROUGH
297    case MVT::i64:
298      ObjSize = 8;
299      if (RegValuesToPass.size() >= 6) {
300        ValToStore = Val;    // Whole thing is passed in memory.
301        break;
302      }
303
304      // Split the value into top and bottom part.  Top part goes in a reg.
305      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
306                                 DAG.getConstant(1, MVT::i32));
307      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
308                                 DAG.getConstant(0, MVT::i32));
309      RegValuesToPass.push_back(Hi);
310
311      if (RegValuesToPass.size() >= 6) {
312        ValToStore = Lo;
313        ArgOffset += 4;
314        ObjSize = 4;
315      } else {
316        RegValuesToPass.push_back(Lo);
317      }
318      break;
319    }
320
321    if (ValToStore.Val) {
322      if (!StackPtr.Val) {
323        StackPtr = DAG.getRegister(SP::O6, MVT::i32);
324      }
325      SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
326      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
327      Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
328    }
329    ArgOffset += ObjSize;
330  }
331
332  // Emit all stores, make sure the occur before any copies into physregs.
333  if (!Stores.empty())
334    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
335
336  static const unsigned ArgRegs[] = {
337    SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
338  };
339
340  // Build a sequence of copy-to-reg nodes chained together with token chain
341  // and flag operands which copy the outgoing args into O[0-5].
342  SDOperand InFlag;
343  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
344    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
345    InFlag = Chain.getValue(1);
346  }
347
348  // If the callee is a GlobalAddress node (quite common, every direct call is)
349  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
350  // Likewise ExternalSymbol -> TargetExternalSymbol.
351  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
352    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
353  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
354    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
355
356  std::vector<MVT::ValueType> NodeTys;
357  NodeTys.push_back(MVT::Other);   // Returns a chain
358  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
359  SDOperand Ops[] = { Chain, Callee, InFlag };
360  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
361  InFlag = Chain.getValue(1);
362
363  Chain = DAG.getCALLSEQ_END(Chain,
364                             DAG.getConstant(ArgsSize, MVT::i32),
365                             DAG.getConstant(0, MVT::i32), InFlag);
366  InFlag = Chain.getValue(1);
367
368  // Assign locations to each value returned by this call.
369  SmallVector<CCValAssign, 16> RVLocs;
370  CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
371
372  CCInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
373  SmallVector<SDOperand, 8> ResultVals;
374
375  // Copy all of the result registers out of their specified physreg.
376  for (unsigned i = 0; i != RVLocs.size(); ++i) {
377    unsigned Reg = RVLocs[i].getLocReg();
378
379    // Remap I0->I7 -> O0->O7.
380    if (Reg >= SP::I0 && Reg <= SP::I7)
381      Reg = Reg-SP::I0+SP::O0;
382
383    Chain = DAG.getCopyFromReg(Chain, Reg,
384                               RVLocs[i].getValVT(), InFlag).getValue(1);
385    InFlag = Chain.getValue(2);
386    ResultVals.push_back(Chain.getValue(0));
387  }
388
389  ResultVals.push_back(Chain);
390
391  // Merge everything together with a MERGE_VALUES node.
392  return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
393                     &ResultVals[0], ResultVals.size());
394}
395
396
397
398//===----------------------------------------------------------------------===//
399// TargetLowering Implementation
400//===----------------------------------------------------------------------===//
401
402/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
403/// condition.
404static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
405  switch (CC) {
406  default: assert(0 && "Unknown integer condition code!");
407  case ISD::SETEQ:  return SPCC::ICC_E;
408  case ISD::SETNE:  return SPCC::ICC_NE;
409  case ISD::SETLT:  return SPCC::ICC_L;
410  case ISD::SETGT:  return SPCC::ICC_G;
411  case ISD::SETLE:  return SPCC::ICC_LE;
412  case ISD::SETGE:  return SPCC::ICC_GE;
413  case ISD::SETULT: return SPCC::ICC_CS;
414  case ISD::SETULE: return SPCC::ICC_LEU;
415  case ISD::SETUGT: return SPCC::ICC_GU;
416  case ISD::SETUGE: return SPCC::ICC_CC;
417  }
418}
419
420/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
421/// FCC condition.
422static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
423  switch (CC) {
424  default: assert(0 && "Unknown fp condition code!");
425  case ISD::SETEQ:
426  case ISD::SETOEQ: return SPCC::FCC_E;
427  case ISD::SETNE:
428  case ISD::SETUNE: return SPCC::FCC_NE;
429  case ISD::SETLT:
430  case ISD::SETOLT: return SPCC::FCC_L;
431  case ISD::SETGT:
432  case ISD::SETOGT: return SPCC::FCC_G;
433  case ISD::SETLE:
434  case ISD::SETOLE: return SPCC::FCC_LE;
435  case ISD::SETGE:
436  case ISD::SETOGE: return SPCC::FCC_GE;
437  case ISD::SETULT: return SPCC::FCC_UL;
438  case ISD::SETULE: return SPCC::FCC_ULE;
439  case ISD::SETUGT: return SPCC::FCC_UG;
440  case ISD::SETUGE: return SPCC::FCC_UGE;
441  case ISD::SETUO:  return SPCC::FCC_U;
442  case ISD::SETO:   return SPCC::FCC_O;
443  case ISD::SETONE: return SPCC::FCC_LG;
444  case ISD::SETUEQ: return SPCC::FCC_UE;
445  }
446}
447
448
449SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
450  : TargetLowering(TM) {
451
452  // Set up the register classes.
453  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
454  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
455  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
456
457  // Turn FP extload into load/fextend
458  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
459  // Sparc doesn't have i1 sign extending load
460  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
461  // Turn FP truncstore into trunc + store.
462  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
463
464  // Custom legalize GlobalAddress nodes into LO/HI parts.
465  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
466  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
467  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
468
469  // Sparc doesn't have sext_inreg, replace them with shl/sra
470  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
471  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
472  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
473
474  // Sparc has no REM or DIVREM operations.
475  setOperationAction(ISD::UREM, MVT::i32, Expand);
476  setOperationAction(ISD::SREM, MVT::i32, Expand);
477  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
478  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
479
480  // Custom expand fp<->sint
481  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
482  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
483
484  // Expand fp<->uint
485  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
486  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
487
488  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
489  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
490
491  // Sparc has no select or setcc: expand to SELECT_CC.
492  setOperationAction(ISD::SELECT, MVT::i32, Expand);
493  setOperationAction(ISD::SELECT, MVT::f32, Expand);
494  setOperationAction(ISD::SELECT, MVT::f64, Expand);
495  setOperationAction(ISD::SETCC, MVT::i32, Expand);
496  setOperationAction(ISD::SETCC, MVT::f32, Expand);
497  setOperationAction(ISD::SETCC, MVT::f64, Expand);
498
499  // Sparc doesn't have BRCOND either, it has BR_CC.
500  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
501  setOperationAction(ISD::BRIND, MVT::Other, Expand);
502  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
503  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
504  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
505  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
506
507  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
508  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
509  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
510
511  // SPARC has no intrinsics for these particular operations.
512  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
513  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
514  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
515  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
516
517  setOperationAction(ISD::FSIN , MVT::f64, Expand);
518  setOperationAction(ISD::FCOS , MVT::f64, Expand);
519  setOperationAction(ISD::FREM , MVT::f64, Expand);
520  setOperationAction(ISD::FSIN , MVT::f32, Expand);
521  setOperationAction(ISD::FCOS , MVT::f32, Expand);
522  setOperationAction(ISD::FREM , MVT::f32, Expand);
523  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
524  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
525  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
526  setOperationAction(ISD::ROTL , MVT::i32, Expand);
527  setOperationAction(ISD::ROTR , MVT::i32, Expand);
528  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
529  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
530  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
531  setOperationAction(ISD::FPOW , MVT::f64, Expand);
532  setOperationAction(ISD::FPOW , MVT::f32, Expand);
533
534  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
535  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
536  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
537
538  // FIXME: Sparc provides these multiplies, but we don't have them yet.
539  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
540
541  // We don't have line number support yet.
542  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
543  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
544  setOperationAction(ISD::LABEL, MVT::Other, Expand);
545
546  // RET must be custom lowered, to meet ABI requirements
547  setOperationAction(ISD::RET               , MVT::Other, Custom);
548
549  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
550  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
551  // VAARG needs to be lowered to not do unaligned accesses for doubles.
552  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
553
554  // Use the default implementation.
555  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
556  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
557  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
558  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
559  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
560
561  // No debug info support yet.
562  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
563  setOperationAction(ISD::LABEL, MVT::Other, Expand);
564  setOperationAction(ISD::DECLARE, MVT::Other, Expand);
565
566  setStackPointerRegisterToSaveRestore(SP::O6);
567
568  if (TM.getSubtarget<SparcSubtarget>().isV9())
569    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
570
571  computeRegisterProperties();
572}
573
574const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
575  switch (Opcode) {
576  default: return 0;
577  case SPISD::CMPICC:     return "SPISD::CMPICC";
578  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
579  case SPISD::BRICC:      return "SPISD::BRICC";
580  case SPISD::BRFCC:      return "SPISD::BRFCC";
581  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
582  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
583  case SPISD::Hi:         return "SPISD::Hi";
584  case SPISD::Lo:         return "SPISD::Lo";
585  case SPISD::FTOI:       return "SPISD::FTOI";
586  case SPISD::ITOF:       return "SPISD::ITOF";
587  case SPISD::CALL:       return "SPISD::CALL";
588  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
589  }
590}
591
592/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
593/// be zero. Op is expected to be a target specific node. Used by DAG
594/// combiner.
595void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
596                                                         const APInt &Mask,
597                                                         APInt &KnownZero,
598                                                         APInt &KnownOne,
599                                                         const SelectionDAG &DAG,
600                                                         unsigned Depth) const {
601  APInt KnownZero2, KnownOne2;
602  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
603
604  switch (Op.getOpcode()) {
605  default: break;
606  case SPISD::SELECT_ICC:
607  case SPISD::SELECT_FCC:
608    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
609                          Depth+1);
610    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
611                          Depth+1);
612    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
613    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
614
615    // Only known if known in both the LHS and RHS.
616    KnownOne &= KnownOne2;
617    KnownZero &= KnownZero2;
618    break;
619  }
620}
621
622// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
623// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
624static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
625                             ISD::CondCode CC, unsigned &SPCC) {
626  if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
627      CC == ISD::SETNE &&
628      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
629        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
630       (LHS.getOpcode() == SPISD::SELECT_FCC &&
631        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
632      isa<ConstantSDNode>(LHS.getOperand(0)) &&
633      isa<ConstantSDNode>(LHS.getOperand(1)) &&
634      cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
635      cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
636    SDOperand CMPCC = LHS.getOperand(3);
637    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
638    LHS = CMPCC.getOperand(0);
639    RHS = CMPCC.getOperand(1);
640  }
641}
642
643static SDOperand LowerGLOBALADDRESS(SDOperand Op, SelectionDAG &DAG) {
644  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
645  SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
646  SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
647  SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
648  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
649}
650
651static SDOperand LowerCONSTANTPOOL(SDOperand Op, SelectionDAG &DAG) {
652  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
653  Constant *C = N->getConstVal();
654  SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
655  SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
656  SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
657  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
658}
659
660static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
661  // Convert the fp value to integer in an FP register.
662  assert(Op.getValueType() == MVT::i32);
663  Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
664  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
665}
666
667static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
668  assert(Op.getOperand(0).getValueType() == MVT::i32);
669  SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
670  // Convert the int value to FP in an FP register.
671  return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
672}
673
674static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
675  SDOperand Chain = Op.getOperand(0);
676  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
677  SDOperand LHS = Op.getOperand(2);
678  SDOperand RHS = Op.getOperand(3);
679  SDOperand Dest = Op.getOperand(4);
680  unsigned Opc, SPCC = ~0U;
681
682  // If this is a br_cc of a "setcc", and if the setcc got lowered into
683  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
684  LookThroughSetCC(LHS, RHS, CC, SPCC);
685
686  // Get the condition flag.
687  SDOperand CompareFlag;
688  if (LHS.getValueType() == MVT::i32) {
689    std::vector<MVT::ValueType> VTs;
690    VTs.push_back(MVT::i32);
691    VTs.push_back(MVT::Flag);
692    SDOperand Ops[2] = { LHS, RHS };
693    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
694    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
695    Opc = SPISD::BRICC;
696  } else {
697    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
698    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
699    Opc = SPISD::BRFCC;
700  }
701  return DAG.getNode(Opc, MVT::Other, Chain, Dest,
702                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
703}
704
705static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
706  SDOperand LHS = Op.getOperand(0);
707  SDOperand RHS = Op.getOperand(1);
708  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
709  SDOperand TrueVal = Op.getOperand(2);
710  SDOperand FalseVal = Op.getOperand(3);
711  unsigned Opc, SPCC = ~0U;
712
713  // If this is a select_cc of a "setcc", and if the setcc got lowered into
714  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
715  LookThroughSetCC(LHS, RHS, CC, SPCC);
716
717  SDOperand CompareFlag;
718  if (LHS.getValueType() == MVT::i32) {
719    std::vector<MVT::ValueType> VTs;
720    VTs.push_back(LHS.getValueType());   // subcc returns a value
721    VTs.push_back(MVT::Flag);
722    SDOperand Ops[2] = { LHS, RHS };
723    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
724    Opc = SPISD::SELECT_ICC;
725    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
726  } else {
727    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
728    Opc = SPISD::SELECT_FCC;
729    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
730  }
731  return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
732                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
733}
734
735static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
736                              SparcTargetLowering &TLI) {
737  // vastart just stores the address of the VarArgsFrameIndex slot into the
738  // memory location argument.
739  SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
740                                 DAG.getRegister(SP::I6, MVT::i32),
741                                 DAG.getConstant(TLI.getVarArgsFrameOffset(),
742                                                 MVT::i32));
743  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
744  return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
745}
746
747static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
748  SDNode *Node = Op.Val;
749  MVT::ValueType VT = Node->getValueType(0);
750  SDOperand InChain = Node->getOperand(0);
751  SDOperand VAListPtr = Node->getOperand(1);
752  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
753  SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
754  // Increment the pointer, VAList, to the next vaarg
755  SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
756                                  DAG.getConstant(MVT::getSizeInBits(VT)/8,
757                                                  MVT::i32));
758  // Store the incremented VAList to the legalized pointer
759  InChain = DAG.getStore(VAList.getValue(1), NextPtr,
760                         VAListPtr, SV, 0);
761  // Load the actual argument out of the pointer VAList, unless this is an
762  // f64 load.
763  if (VT != MVT::f64)
764    return DAG.getLoad(VT, InChain, VAList, NULL, 0);
765
766  // Otherwise, load it as i64, then do a bitconvert.
767  SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
768
769  // Bit-Convert the value to f64.
770  SDOperand Ops[2] = {
771    DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
772    V.getValue(1)
773  };
774  return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::f64, MVT::Other),
775                     Ops, 2);
776}
777
778static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) {
779  SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
780  SDOperand Size  = Op.getOperand(1);  // Legalize the size.
781
782  unsigned SPReg = SP::O6;
783  SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
784  SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
785  Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
786
787  // The resultant pointer is actually 16 words from the bottom of the stack,
788  // to provide a register spill area.
789  SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
790                                 DAG.getConstant(96, MVT::i32));
791  std::vector<MVT::ValueType> Tys;
792  Tys.push_back(MVT::i32);
793  Tys.push_back(MVT::Other);
794  SDOperand Ops[2] = { NewVal, Chain };
795  return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
796}
797
798
799SDOperand SparcTargetLowering::
800LowerOperation(SDOperand Op, SelectionDAG &DAG) {
801  switch (Op.getOpcode()) {
802  default: assert(0 && "Should not custom lower this!");
803  // Frame & Return address.  Currently unimplemented
804  case ISD::RETURNADDR: return SDOperand();
805  case ISD::FRAMEADDR:  return SDOperand();
806  case ISD::GlobalTLSAddress:
807    assert(0 && "TLS not implemented for Sparc.");
808  case ISD::GlobalAddress:      return LowerGLOBALADDRESS(Op, DAG);
809  case ISD::ConstantPool:       return LowerCONSTANTPOOL(Op, DAG);
810  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
811  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
812  case ISD::BR_CC:              return LowerBR_CC(Op, DAG);
813  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
814  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
815  case ISD::VAARG:              return LowerVAARG(Op, DAG);
816  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
817  case ISD::CALL:               return LowerCALL(Op, DAG);
818  case ISD::RET:                return LowerRET(Op, DAG);
819  }
820}
821
822MachineBasicBlock *
823SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
824                                                 MachineBasicBlock *BB) {
825  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
826  unsigned BROpcode;
827  unsigned CC;
828  // Figure out the conditional branch opcode to use for this select_cc.
829  switch (MI->getOpcode()) {
830  default: assert(0 && "Unknown SELECT_CC!");
831  case SP::SELECT_CC_Int_ICC:
832  case SP::SELECT_CC_FP_ICC:
833  case SP::SELECT_CC_DFP_ICC:
834    BROpcode = SP::BCOND;
835    break;
836  case SP::SELECT_CC_Int_FCC:
837  case SP::SELECT_CC_FP_FCC:
838  case SP::SELECT_CC_DFP_FCC:
839    BROpcode = SP::FBCOND;
840    break;
841  }
842
843  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
844
845  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
846  // control-flow pattern.  The incoming instruction knows the destination vreg
847  // to set, the condition code register to branch on, the true/false values to
848  // select between, and a branch opcode to use.
849  const BasicBlock *LLVM_BB = BB->getBasicBlock();
850  ilist<MachineBasicBlock>::iterator It = BB;
851  ++It;
852
853  //  thisMBB:
854  //  ...
855  //   TrueVal = ...
856  //   [f]bCC copy1MBB
857  //   fallthrough --> copy0MBB
858  MachineBasicBlock *thisMBB = BB;
859  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
860  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
861  BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
862  MachineFunction *F = BB->getParent();
863  F->getBasicBlockList().insert(It, copy0MBB);
864  F->getBasicBlockList().insert(It, sinkMBB);
865  // Update machine-CFG edges by first adding all successors of the current
866  // block to the new block which will contain the Phi node for the select.
867  for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
868      e = BB->succ_end(); i != e; ++i)
869    sinkMBB->addSuccessor(*i);
870  // Next, remove all successors of the current block, and add the true
871  // and fallthrough blocks as its successors.
872  while(!BB->succ_empty())
873    BB->removeSuccessor(BB->succ_begin());
874  BB->addSuccessor(copy0MBB);
875  BB->addSuccessor(sinkMBB);
876
877  //  copy0MBB:
878  //   %FalseValue = ...
879  //   # fallthrough to sinkMBB
880  BB = copy0MBB;
881
882  // Update machine-CFG edges
883  BB->addSuccessor(sinkMBB);
884
885  //  sinkMBB:
886  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
887  //  ...
888  BB = sinkMBB;
889  BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
890    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
891    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
892
893  delete MI;   // The pseudo instruction is gone now.
894  return BB;
895}
896
897