SparcISelLowering.cpp revision bcc8017c738e92d9c1af221b11c4916cb524184e
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcTargetMachine.h" 17#include "SparcMachineFunctionInfo.h" 18#include "llvm/Function.h" 19#include "llvm/CodeGen/CallingConvLower.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26#include "llvm/ADT/VectorExtras.h" 27#include "llvm/Support/ErrorHandling.h" 28using namespace llvm; 29 30 31//===----------------------------------------------------------------------===// 32// Calling Convention Implementation 33//===----------------------------------------------------------------------===// 34 35#include "SparcGenCallingConv.inc" 36 37SDValue 38SparcTargetLowering::LowerReturn(SDValue Chain, 39 CallingConv::ID CallConv, bool isVarArg, 40 const SmallVectorImpl<ISD::OutputArg> &Outs, 41 const SmallVectorImpl<SDValue> &OutVals, 42 DebugLoc dl, SelectionDAG &DAG) const { 43 44 // CCValAssign - represent the assignment of the return value to locations. 45 SmallVector<CCValAssign, 16> RVLocs; 46 47 // CCState - Info about the registers and stack slot. 48 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), 49 RVLocs, *DAG.getContext()); 50 51 // Analize return values. 52 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 53 54 // If this is the first return lowered for this function, add the regs to the 55 // liveout set for the function. 56 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 57 for (unsigned i = 0; i != RVLocs.size(); ++i) 58 if (RVLocs[i].isRegLoc()) 59 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 60 } 61 62 SDValue Flag; 63 64 // Copy the result values into the output registers. 65 for (unsigned i = 0; i != RVLocs.size(); ++i) { 66 CCValAssign &VA = RVLocs[i]; 67 assert(VA.isRegLoc() && "Can only return in registers!"); 68 69 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 70 OutVals[i], Flag); 71 72 // Guarantee that all emitted copies are stuck together with flags. 73 Flag = Chain.getValue(1); 74 } 75 76 if (Flag.getNode()) 77 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 78 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain); 79} 80 81/// LowerFormalArguments - V8 uses a very simple ABI, where all values are 82/// passed in either one or two GPRs, including FP values. TODO: we should 83/// pass FP values in FP registers for fastcc functions. 84SDValue 85SparcTargetLowering::LowerFormalArguments(SDValue Chain, 86 CallingConv::ID CallConv, bool isVarArg, 87 const SmallVectorImpl<ISD::InputArg> 88 &Ins, 89 DebugLoc dl, SelectionDAG &DAG, 90 SmallVectorImpl<SDValue> &InVals) 91 const { 92 93 MachineFunction &MF = DAG.getMachineFunction(); 94 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 95 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 96 97 // Assign locations to all of the incoming arguments. 98 SmallVector<CCValAssign, 16> ArgLocs; 99 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 100 ArgLocs, *DAG.getContext()); 101 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 102 103 static const unsigned ArgRegs[] = { 104 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 105 }; 106 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 107 unsigned ArgOffset = 68; 108 109 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 110 SDValue ArgValue; 111 CCValAssign &VA = ArgLocs[i]; 112 // FIXME: We ignore the register assignments of AnalyzeFormalArguments 113 // because it doesn't know how to split a double into two i32 registers. 114 EVT ObjectVT = VA.getValVT(); 115 switch (ObjectVT.getSimpleVT().SimpleTy) { 116 default: llvm_unreachable("Unhandled argument type!"); 117 case MVT::i1: 118 case MVT::i8: 119 case MVT::i16: 120 case MVT::i32: 121 if (!Ins[i].Used) { // Argument is dead. 122 if (CurArgReg < ArgRegEnd) ++CurArgReg; 123 InVals.push_back(DAG.getUNDEF(ObjectVT)); 124 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 125 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 126 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 127 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 128 if (ObjectVT != MVT::i32) { 129 unsigned AssertOp = ISD::AssertSext; 130 Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg, 131 DAG.getValueType(ObjectVT)); 132 Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg); 133 } 134 InVals.push_back(Arg); 135 } else { 136 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 137 true); 138 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 139 SDValue Load; 140 if (ObjectVT == MVT::i32) { 141 Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0, 142 false, false, 0); 143 } else { 144 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 145 146 // Sparc is big endian, so add an offset based on the ObjectVT. 147 unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8); 148 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 149 DAG.getConstant(Offset, MVT::i32)); 150 Load = DAG.getExtLoad(LoadOp, MVT::i32, dl, Chain, FIPtr, 151 NULL, 0, ObjectVT, false, false, 0); 152 Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load); 153 } 154 InVals.push_back(Load); 155 } 156 157 ArgOffset += 4; 158 break; 159 case MVT::f32: 160 if (!Ins[i].Used) { // Argument is dead. 161 if (CurArgReg < ArgRegEnd) ++CurArgReg; 162 InVals.push_back(DAG.getUNDEF(ObjectVT)); 163 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 164 // FP value is passed in an integer register. 165 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 166 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 167 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 168 169 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg); 170 InVals.push_back(Arg); 171 } else { 172 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 173 true); 174 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 175 SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0, 176 false, false, 0); 177 InVals.push_back(Load); 178 } 179 ArgOffset += 4; 180 break; 181 182 case MVT::i64: 183 case MVT::f64: 184 if (!Ins[i].Used) { // Argument is dead. 185 if (CurArgReg < ArgRegEnd) ++CurArgReg; 186 if (CurArgReg < ArgRegEnd) ++CurArgReg; 187 InVals.push_back(DAG.getUNDEF(ObjectVT)); 188 } else { 189 SDValue HiVal; 190 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 191 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 192 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 193 HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 194 } else { 195 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 196 true); 197 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 198 HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0, 199 false, false, 0); 200 } 201 202 SDValue LoVal; 203 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 204 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 205 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 206 LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32); 207 } else { 208 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4, 209 true); 210 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 211 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0, 212 false, false, 0); 213 } 214 215 // Compose the two halves together into an i64 unit. 216 SDValue WholeValue = 217 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 218 219 // If we want a double, do a bit convert. 220 if (ObjectVT == MVT::f64) 221 WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue); 222 223 InVals.push_back(WholeValue); 224 } 225 ArgOffset += 8; 226 break; 227 } 228 } 229 230 // Store remaining ArgRegs to the stack if this is a varargs function. 231 if (isVarArg) { 232 // Remember the vararg offset for the va_start implementation. 233 FuncInfo->setVarArgsFrameOffset(ArgOffset); 234 235 std::vector<SDValue> OutChains; 236 237 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 238 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 239 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 240 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 241 242 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 243 true); 244 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 245 246 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0, 247 false, false, 0)); 248 ArgOffset += 4; 249 } 250 251 if (!OutChains.empty()) { 252 OutChains.push_back(Chain); 253 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 254 &OutChains[0], OutChains.size()); 255 } 256 } 257 258 return Chain; 259} 260 261SDValue 262SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 263 CallingConv::ID CallConv, bool isVarArg, 264 bool &isTailCall, 265 const SmallVectorImpl<ISD::OutputArg> &Outs, 266 const SmallVectorImpl<SDValue> &OutVals, 267 const SmallVectorImpl<ISD::InputArg> &Ins, 268 DebugLoc dl, SelectionDAG &DAG, 269 SmallVectorImpl<SDValue> &InVals) const { 270 // Sparc target does not yet support tail call optimization. 271 isTailCall = false; 272 273#if 0 274 // Analyze operands of the call, assigning locations to each operand. 275 SmallVector<CCValAssign, 16> ArgLocs; 276 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs); 277 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 278 279 // Get the size of the outgoing arguments stack space requirement. 280 unsigned ArgsSize = CCInfo.getNextStackOffset(); 281 // FIXME: We can't use this until f64 is known to take two GPRs. 282#else 283 (void)CC_Sparc32; 284 285 // Count the size of the outgoing arguments. 286 unsigned ArgsSize = 0; 287 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 288 switch (Outs[i].VT.getSimpleVT().SimpleTy) { 289 default: llvm_unreachable("Unknown value type!"); 290 case MVT::i1: 291 case MVT::i8: 292 case MVT::i16: 293 case MVT::i32: 294 case MVT::f32: 295 ArgsSize += 4; 296 break; 297 case MVT::i64: 298 case MVT::f64: 299 ArgsSize += 8; 300 break; 301 } 302 } 303 if (ArgsSize > 4*6) 304 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 305 else 306 ArgsSize = 0; 307#endif 308 309 // Keep stack frames 8-byte aligned. 310 ArgsSize = (ArgsSize+7) & ~7; 311 312 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 313 314 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 315 SmallVector<SDValue, 8> MemOpChains; 316 317#if 0 318 // Walk the register/memloc assignments, inserting copies/loads. 319 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 320 CCValAssign &VA = ArgLocs[i]; 321 SDValue Arg = OutVals[i]; 322 323 // Promote the value if needed. 324 switch (VA.getLocInfo()) { 325 default: llvm_unreachable("Unknown loc info!"); 326 case CCValAssign::Full: break; 327 case CCValAssign::SExt: 328 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 329 break; 330 case CCValAssign::ZExt: 331 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 332 break; 333 case CCValAssign::AExt: 334 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 335 break; 336 } 337 338 // Arguments that can be passed on register must be kept at 339 // RegsToPass vector 340 if (VA.isRegLoc()) { 341 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 342 continue; 343 } 344 345 assert(VA.isMemLoc()); 346 347 // Create a store off the stack pointer for this argument. 348 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 349 // FIXME: VERIFY THAT 68 IS RIGHT. 350 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68); 351 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 352 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0, 353 false, false, 0)); 354 } 355 356#else 357 static const unsigned ArgRegs[] = { 358 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 359 }; 360 unsigned ArgOffset = 68; 361 362 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 363 SDValue Val = OutVals[i]; 364 EVT ObjectVT = Outs[i].VT; 365 SDValue ValToStore(0, 0); 366 unsigned ObjSize; 367 switch (ObjectVT.getSimpleVT().SimpleTy) { 368 default: llvm_unreachable("Unhandled argument type!"); 369 case MVT::i32: 370 ObjSize = 4; 371 372 if (RegsToPass.size() >= 6) { 373 ValToStore = Val; 374 } else { 375 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); 376 } 377 break; 378 case MVT::f32: 379 ObjSize = 4; 380 if (RegsToPass.size() >= 6) { 381 ValToStore = Val; 382 } else { 383 // Convert this to a FP value in an int reg. 384 Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val); 385 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); 386 } 387 break; 388 case MVT::f64: { 389 ObjSize = 8; 390 if (RegsToPass.size() >= 6) { 391 ValToStore = Val; // Whole thing is passed in memory. 392 break; 393 } 394 395 // Break into top and bottom parts by storing to the stack and loading 396 // out the parts as integers. Top part goes in a reg. 397 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 398 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 399 Val, StackPtr, NULL, 0, 400 false, false, 0); 401 // Sparc is big-endian, so the high part comes first. 402 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 403 false, false, 0); 404 // Increment the pointer to the other half. 405 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 406 DAG.getIntPtrConstant(4)); 407 // Load the low part. 408 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 409 false, false, 0); 410 411 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); 412 413 if (RegsToPass.size() >= 6) { 414 ValToStore = Lo; 415 ArgOffset += 4; 416 ObjSize = 4; 417 } else { 418 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo)); 419 } 420 break; 421 } 422 case MVT::i64: { 423 ObjSize = 8; 424 if (RegsToPass.size() >= 6) { 425 ValToStore = Val; // Whole thing is passed in memory. 426 break; 427 } 428 429 // Split the value into top and bottom part. Top part goes in a reg. 430 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, 431 DAG.getConstant(1, MVT::i32)); 432 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, 433 DAG.getConstant(0, MVT::i32)); 434 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); 435 436 if (RegsToPass.size() >= 6) { 437 ValToStore = Lo; 438 ArgOffset += 4; 439 ObjSize = 4; 440 } else { 441 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo)); 442 } 443 break; 444 } 445 } 446 447 if (ValToStore.getNode()) { 448 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 449 SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32); 450 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 451 MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore, 452 PtrOff, NULL, 0, 453 false, false, 0)); 454 } 455 ArgOffset += ObjSize; 456 } 457#endif 458 459 // Emit all stores, make sure the occur before any copies into physregs. 460 if (!MemOpChains.empty()) 461 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 462 &MemOpChains[0], MemOpChains.size()); 463 464 // Build a sequence of copy-to-reg nodes chained together with token 465 // chain and flag operands which copy the outgoing args into registers. 466 // The InFlag in necessary since all emited instructions must be 467 // stuck together. 468 SDValue InFlag; 469 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 470 unsigned Reg = RegsToPass[i].first; 471 // Remap I0->I7 -> O0->O7. 472 if (Reg >= SP::I0 && Reg <= SP::I7) 473 Reg = Reg-SP::I0+SP::O0; 474 475 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 476 InFlag = Chain.getValue(1); 477 } 478 479 // If the callee is a GlobalAddress node (quite common, every direct call is) 480 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 481 // Likewise ExternalSymbol -> TargetExternalSymbol. 482 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 483 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 484 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 485 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 486 487 std::vector<EVT> NodeTys; 488 NodeTys.push_back(MVT::Other); // Returns a chain 489 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 490 SDValue Ops[] = { Chain, Callee, InFlag }; 491 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2); 492 InFlag = Chain.getValue(1); 493 494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 495 DAG.getIntPtrConstant(0, true), InFlag); 496 InFlag = Chain.getValue(1); 497 498 // Assign locations to each value returned by this call. 499 SmallVector<CCValAssign, 16> RVLocs; 500 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), 501 RVLocs, *DAG.getContext()); 502 503 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 504 505 // Copy all of the result registers out of their specified physreg. 506 for (unsigned i = 0; i != RVLocs.size(); ++i) { 507 unsigned Reg = RVLocs[i].getLocReg(); 508 509 // Remap I0->I7 -> O0->O7. 510 if (Reg >= SP::I0 && Reg <= SP::I7) 511 Reg = Reg-SP::I0+SP::O0; 512 513 Chain = DAG.getCopyFromReg(Chain, dl, Reg, 514 RVLocs[i].getValVT(), InFlag).getValue(1); 515 InFlag = Chain.getValue(2); 516 InVals.push_back(Chain.getValue(0)); 517 } 518 519 return Chain; 520} 521 522 523 524//===----------------------------------------------------------------------===// 525// TargetLowering Implementation 526//===----------------------------------------------------------------------===// 527 528/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 529/// condition. 530static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 531 switch (CC) { 532 default: llvm_unreachable("Unknown integer condition code!"); 533 case ISD::SETEQ: return SPCC::ICC_E; 534 case ISD::SETNE: return SPCC::ICC_NE; 535 case ISD::SETLT: return SPCC::ICC_L; 536 case ISD::SETGT: return SPCC::ICC_G; 537 case ISD::SETLE: return SPCC::ICC_LE; 538 case ISD::SETGE: return SPCC::ICC_GE; 539 case ISD::SETULT: return SPCC::ICC_CS; 540 case ISD::SETULE: return SPCC::ICC_LEU; 541 case ISD::SETUGT: return SPCC::ICC_GU; 542 case ISD::SETUGE: return SPCC::ICC_CC; 543 } 544} 545 546/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 547/// FCC condition. 548static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 549 switch (CC) { 550 default: llvm_unreachable("Unknown fp condition code!"); 551 case ISD::SETEQ: 552 case ISD::SETOEQ: return SPCC::FCC_E; 553 case ISD::SETNE: 554 case ISD::SETUNE: return SPCC::FCC_NE; 555 case ISD::SETLT: 556 case ISD::SETOLT: return SPCC::FCC_L; 557 case ISD::SETGT: 558 case ISD::SETOGT: return SPCC::FCC_G; 559 case ISD::SETLE: 560 case ISD::SETOLE: return SPCC::FCC_LE; 561 case ISD::SETGE: 562 case ISD::SETOGE: return SPCC::FCC_GE; 563 case ISD::SETULT: return SPCC::FCC_UL; 564 case ISD::SETULE: return SPCC::FCC_ULE; 565 case ISD::SETUGT: return SPCC::FCC_UG; 566 case ISD::SETUGE: return SPCC::FCC_UGE; 567 case ISD::SETUO: return SPCC::FCC_U; 568 case ISD::SETO: return SPCC::FCC_O; 569 case ISD::SETONE: return SPCC::FCC_LG; 570 case ISD::SETUEQ: return SPCC::FCC_UE; 571 } 572} 573 574SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 575 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 576 577 // Set up the register classes. 578 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 579 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 580 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 581 582 // Turn FP extload into load/fextend 583 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 584 // Sparc doesn't have i1 sign extending load 585 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 586 // Turn FP truncstore into trunc + store. 587 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 588 589 // Custom legalize GlobalAddress nodes into LO/HI parts. 590 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 591 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 592 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 593 594 // Sparc doesn't have sext_inreg, replace them with shl/sra 595 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 596 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 597 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 598 599 // Sparc has no REM or DIVREM operations. 600 setOperationAction(ISD::UREM, MVT::i32, Expand); 601 setOperationAction(ISD::SREM, MVT::i32, Expand); 602 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 603 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 604 605 // Custom expand fp<->sint 606 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 607 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 608 609 // Expand fp<->uint 610 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 611 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 612 613 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 614 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 615 616 // Sparc has no select or setcc: expand to SELECT_CC. 617 setOperationAction(ISD::SELECT, MVT::i32, Expand); 618 setOperationAction(ISD::SELECT, MVT::f32, Expand); 619 setOperationAction(ISD::SELECT, MVT::f64, Expand); 620 setOperationAction(ISD::SETCC, MVT::i32, Expand); 621 setOperationAction(ISD::SETCC, MVT::f32, Expand); 622 setOperationAction(ISD::SETCC, MVT::f64, Expand); 623 624 // Sparc doesn't have BRCOND either, it has BR_CC. 625 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 626 setOperationAction(ISD::BRIND, MVT::Other, Expand); 627 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 628 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 629 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 630 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 631 632 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 633 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 634 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 635 636 // SPARC has no intrinsics for these particular operations. 637 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 638 639 setOperationAction(ISD::FSIN , MVT::f64, Expand); 640 setOperationAction(ISD::FCOS , MVT::f64, Expand); 641 setOperationAction(ISD::FREM , MVT::f64, Expand); 642 setOperationAction(ISD::FSIN , MVT::f32, Expand); 643 setOperationAction(ISD::FCOS , MVT::f32, Expand); 644 setOperationAction(ISD::FREM , MVT::f32, Expand); 645 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 646 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 647 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 648 setOperationAction(ISD::ROTL , MVT::i32, Expand); 649 setOperationAction(ISD::ROTR , MVT::i32, Expand); 650 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 651 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 652 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 653 setOperationAction(ISD::FPOW , MVT::f64, Expand); 654 setOperationAction(ISD::FPOW , MVT::f32, Expand); 655 656 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 657 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 658 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 659 660 // FIXME: Sparc provides these multiplies, but we don't have them yet. 661 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 662 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 663 664 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 665 666 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 667 setOperationAction(ISD::VASTART , MVT::Other, Custom); 668 // VAARG needs to be lowered to not do unaligned accesses for doubles. 669 setOperationAction(ISD::VAARG , MVT::Other, Custom); 670 671 // Use the default implementation. 672 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 673 setOperationAction(ISD::VAEND , MVT::Other, Expand); 674 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 675 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 676 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 677 678 // No debug info support yet. 679 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 680 681 setStackPointerRegisterToSaveRestore(SP::O6); 682 683 if (TM.getSubtarget<SparcSubtarget>().isV9()) 684 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 685 686 computeRegisterProperties(); 687} 688 689const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 690 switch (Opcode) { 691 default: return 0; 692 case SPISD::CMPICC: return "SPISD::CMPICC"; 693 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 694 case SPISD::BRICC: return "SPISD::BRICC"; 695 case SPISD::BRFCC: return "SPISD::BRFCC"; 696 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 697 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 698 case SPISD::Hi: return "SPISD::Hi"; 699 case SPISD::Lo: return "SPISD::Lo"; 700 case SPISD::FTOI: return "SPISD::FTOI"; 701 case SPISD::ITOF: return "SPISD::ITOF"; 702 case SPISD::CALL: return "SPISD::CALL"; 703 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 704 } 705} 706 707/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 708/// be zero. Op is expected to be a target specific node. Used by DAG 709/// combiner. 710void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 711 const APInt &Mask, 712 APInt &KnownZero, 713 APInt &KnownOne, 714 const SelectionDAG &DAG, 715 unsigned Depth) const { 716 APInt KnownZero2, KnownOne2; 717 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 718 719 switch (Op.getOpcode()) { 720 default: break; 721 case SPISD::SELECT_ICC: 722 case SPISD::SELECT_FCC: 723 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 724 Depth+1); 725 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 726 Depth+1); 727 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 728 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 729 730 // Only known if known in both the LHS and RHS. 731 KnownOne &= KnownOne2; 732 KnownZero &= KnownZero2; 733 break; 734 } 735} 736 737// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 738// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 739static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 740 ISD::CondCode CC, unsigned &SPCC) { 741 if (isa<ConstantSDNode>(RHS) && 742 cast<ConstantSDNode>(RHS)->isNullValue() && 743 CC == ISD::SETNE && 744 ((LHS.getOpcode() == SPISD::SELECT_ICC && 745 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 746 (LHS.getOpcode() == SPISD::SELECT_FCC && 747 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 748 isa<ConstantSDNode>(LHS.getOperand(0)) && 749 isa<ConstantSDNode>(LHS.getOperand(1)) && 750 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 751 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 752 SDValue CMPCC = LHS.getOperand(3); 753 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 754 LHS = CMPCC.getOperand(0); 755 RHS = CMPCC.getOperand(1); 756 } 757} 758 759SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 760 SelectionDAG &DAG) const { 761 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 762 // FIXME there isn't really any debug info here 763 DebugLoc dl = Op.getDebugLoc(); 764 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 765 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); 766 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); 767 768 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 769 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 770 771 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 772 getPointerTy()); 773 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 774 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 775 GlobalBase, RelAddr); 776 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 777 AbsAddr, NULL, 0, false, false, 0); 778} 779 780SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 781 SelectionDAG &DAG) const { 782 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 783 // FIXME there isn't really any debug info here 784 DebugLoc dl = Op.getDebugLoc(); 785 const Constant *C = N->getConstVal(); 786 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 787 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); 788 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); 789 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 790 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 791 792 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 793 getPointerTy()); 794 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 795 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 796 GlobalBase, RelAddr); 797 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 798 AbsAddr, NULL, 0, false, false, 0); 799} 800 801static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 802 DebugLoc dl = Op.getDebugLoc(); 803 // Convert the fp value to integer in an FP register. 804 assert(Op.getValueType() == MVT::i32); 805 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 806 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 807} 808 809static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 810 DebugLoc dl = Op.getDebugLoc(); 811 assert(Op.getOperand(0).getValueType() == MVT::i32); 812 SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); 813 // Convert the int value to FP in an FP register. 814 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 815} 816 817static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 818 SDValue Chain = Op.getOperand(0); 819 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 820 SDValue LHS = Op.getOperand(2); 821 SDValue RHS = Op.getOperand(3); 822 SDValue Dest = Op.getOperand(4); 823 DebugLoc dl = Op.getDebugLoc(); 824 unsigned Opc, SPCC = ~0U; 825 826 // If this is a br_cc of a "setcc", and if the setcc got lowered into 827 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 828 LookThroughSetCC(LHS, RHS, CC, SPCC); 829 830 // Get the condition flag. 831 SDValue CompareFlag; 832 if (LHS.getValueType() == MVT::i32) { 833 std::vector<EVT> VTs; 834 VTs.push_back(MVT::i32); 835 VTs.push_back(MVT::Flag); 836 SDValue Ops[2] = { LHS, RHS }; 837 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 838 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 839 Opc = SPISD::BRICC; 840 } else { 841 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); 842 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 843 Opc = SPISD::BRFCC; 844 } 845 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 846 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 847} 848 849static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 850 SDValue LHS = Op.getOperand(0); 851 SDValue RHS = Op.getOperand(1); 852 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 853 SDValue TrueVal = Op.getOperand(2); 854 SDValue FalseVal = Op.getOperand(3); 855 DebugLoc dl = Op.getDebugLoc(); 856 unsigned Opc, SPCC = ~0U; 857 858 // If this is a select_cc of a "setcc", and if the setcc got lowered into 859 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 860 LookThroughSetCC(LHS, RHS, CC, SPCC); 861 862 SDValue CompareFlag; 863 if (LHS.getValueType() == MVT::i32) { 864 std::vector<EVT> VTs; 865 VTs.push_back(LHS.getValueType()); // subcc returns a value 866 VTs.push_back(MVT::Flag); 867 SDValue Ops[2] = { LHS, RHS }; 868 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 869 Opc = SPISD::SELECT_ICC; 870 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 871 } else { 872 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); 873 Opc = SPISD::SELECT_FCC; 874 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 875 } 876 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 877 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 878} 879 880static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 881 const SparcTargetLowering &TLI) { 882 MachineFunction &MF = DAG.getMachineFunction(); 883 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 884 885 // vastart just stores the address of the VarArgsFrameIndex slot into the 886 // memory location argument. 887 DebugLoc dl = Op.getDebugLoc(); 888 SDValue Offset = 889 DAG.getNode(ISD::ADD, dl, MVT::i32, 890 DAG.getRegister(SP::I6, MVT::i32), 891 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(), 892 MVT::i32)); 893 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 894 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0, 895 false, false, 0); 896} 897 898static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 899 SDNode *Node = Op.getNode(); 900 EVT VT = Node->getValueType(0); 901 SDValue InChain = Node->getOperand(0); 902 SDValue VAListPtr = Node->getOperand(1); 903 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 904 DebugLoc dl = Node->getDebugLoc(); 905 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0, 906 false, false, 0); 907 // Increment the pointer, VAList, to the next vaarg 908 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 909 DAG.getConstant(VT.getSizeInBits()/8, 910 MVT::i32)); 911 // Store the incremented VAList to the legalized pointer 912 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 913 VAListPtr, SV, 0, false, false, 0); 914 // Load the actual argument out of the pointer VAList, unless this is an 915 // f64 load. 916 if (VT != MVT::f64) 917 return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0, false, false, 0); 918 919 // Otherwise, load it as i64, then do a bitconvert. 920 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0, 921 false, false, 0); 922 923 // Bit-Convert the value to f64. 924 SDValue Ops[2] = { 925 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V), 926 V.getValue(1) 927 }; 928 return DAG.getMergeValues(Ops, 2, dl); 929} 930 931static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 932 SDValue Chain = Op.getOperand(0); // Legalize the chain. 933 SDValue Size = Op.getOperand(1); // Legalize the size. 934 DebugLoc dl = Op.getDebugLoc(); 935 936 unsigned SPReg = SP::O6; 937 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 938 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 939 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 940 941 // The resultant pointer is actually 16 words from the bottom of the stack, 942 // to provide a register spill area. 943 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 944 DAG.getConstant(96, MVT::i32)); 945 SDValue Ops[2] = { NewVal, Chain }; 946 return DAG.getMergeValues(Ops, 2, dl); 947} 948 949 950SDValue SparcTargetLowering:: 951LowerOperation(SDValue Op, SelectionDAG &DAG) const { 952 switch (Op.getOpcode()) { 953 default: llvm_unreachable("Should not custom lower this!"); 954 // Frame & Return address. Currently unimplemented 955 case ISD::RETURNADDR: return SDValue(); 956 case ISD::FRAMEADDR: return SDValue(); 957 case ISD::GlobalTLSAddress: 958 llvm_unreachable("TLS not implemented for Sparc."); 959 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 960 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 961 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 962 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 963 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 964 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 965 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 966 case ISD::VAARG: return LowerVAARG(Op, DAG); 967 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 968 } 969} 970 971MachineBasicBlock * 972SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 973 MachineBasicBlock *BB) const { 974 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 975 unsigned BROpcode; 976 unsigned CC; 977 DebugLoc dl = MI->getDebugLoc(); 978 // Figure out the conditional branch opcode to use for this select_cc. 979 switch (MI->getOpcode()) { 980 default: llvm_unreachable("Unknown SELECT_CC!"); 981 case SP::SELECT_CC_Int_ICC: 982 case SP::SELECT_CC_FP_ICC: 983 case SP::SELECT_CC_DFP_ICC: 984 BROpcode = SP::BCOND; 985 break; 986 case SP::SELECT_CC_Int_FCC: 987 case SP::SELECT_CC_FP_FCC: 988 case SP::SELECT_CC_DFP_FCC: 989 BROpcode = SP::FBCOND; 990 break; 991 } 992 993 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 994 995 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 996 // control-flow pattern. The incoming instruction knows the destination vreg 997 // to set, the condition code register to branch on, the true/false values to 998 // select between, and a branch opcode to use. 999 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1000 MachineFunction::iterator It = BB; 1001 ++It; 1002 1003 // thisMBB: 1004 // ... 1005 // TrueVal = ... 1006 // [f]bCC copy1MBB 1007 // fallthrough --> copy0MBB 1008 MachineBasicBlock *thisMBB = BB; 1009 MachineFunction *F = BB->getParent(); 1010 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1011 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1012 1013 // Transfer the remainder of BB and its successor edges to sinkMBB. 1014 sinkMBB->splice(sinkMBB->begin(), BB, 1015 llvm::next(MachineBasicBlock::iterator(MI)), 1016 BB->end()); 1017 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1018 1019 // Add the true and fallthrough blocks as its successors. 1020 BB->addSuccessor(copy0MBB); 1021 BB->addSuccessor(sinkMBB); 1022 1023 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1024 F->insert(It, copy0MBB); 1025 F->insert(It, sinkMBB); 1026 1027 // copy0MBB: 1028 // %FalseValue = ... 1029 // # fallthrough to sinkMBB 1030 BB = copy0MBB; 1031 1032 // Update machine-CFG edges 1033 BB->addSuccessor(sinkMBB); 1034 1035 // sinkMBB: 1036 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1037 // ... 1038 BB = sinkMBB; 1039 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1040 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1041 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1042 1043 MI->eraseFromParent(); // The pseudo instruction is gone now. 1044 return BB; 1045} 1046 1047//===----------------------------------------------------------------------===// 1048// Sparc Inline Assembly Support 1049//===----------------------------------------------------------------------===// 1050 1051/// getConstraintType - Given a constraint letter, return the type of 1052/// constraint it is for this target. 1053SparcTargetLowering::ConstraintType 1054SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1055 if (Constraint.size() == 1) { 1056 switch (Constraint[0]) { 1057 default: break; 1058 case 'r': return C_RegisterClass; 1059 } 1060 } 1061 1062 return TargetLowering::getConstraintType(Constraint); 1063} 1064 1065std::pair<unsigned, const TargetRegisterClass*> 1066SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1067 EVT VT) const { 1068 if (Constraint.size() == 1) { 1069 switch (Constraint[0]) { 1070 case 'r': 1071 return std::make_pair(0U, SP::IntRegsRegisterClass); 1072 } 1073 } 1074 1075 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1076} 1077 1078std::vector<unsigned> SparcTargetLowering:: 1079getRegClassForInlineAsmConstraint(const std::string &Constraint, 1080 EVT VT) const { 1081 if (Constraint.size() != 1) 1082 return std::vector<unsigned>(); 1083 1084 switch (Constraint[0]) { 1085 default: break; 1086 case 'r': 1087 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3, 1088 SP::L4, SP::L5, SP::L6, SP::L7, 1089 SP::I0, SP::I1, SP::I2, SP::I3, 1090 SP::I4, SP::I5, 1091 SP::O0, SP::O1, SP::O2, SP::O3, 1092 SP::O4, SP::O5, SP::O7, 0); 1093 } 1094 1095 return std::vector<unsigned>(); 1096} 1097 1098bool 1099SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1100 // The Sparc target isn't yet aware of offsets. 1101 return false; 1102} 1103 1104/// getFunctionAlignment - Return the Log2 alignment of this function. 1105unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const { 1106 return 2; 1107} 1108