SparcISelLowering.cpp revision f0144127b98425d214e59e4a1a4b342b78e3642b
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcTargetMachine.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/CallingConvLower.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/Target/TargetLoweringObjectFile.h" 25#include "llvm/ADT/VectorExtras.h" 26#include "llvm/Support/ErrorHandling.h" 27using namespace llvm; 28 29 30//===----------------------------------------------------------------------===// 31// Calling Convention Implementation 32//===----------------------------------------------------------------------===// 33 34#include "SparcGenCallingConv.inc" 35 36static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { 37 // CCValAssign - represent the assignment of the return value to locations. 38 SmallVector<CCValAssign, 16> RVLocs; 39 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 40 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 41 DebugLoc dl = Op.getDebugLoc(); 42 43 // CCState - Info about the registers and stack slot. 44 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext()); 45 46 // Analize return values of ISD::RET 47 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32); 48 49 // If this is the first return lowered for this function, add the regs to the 50 // liveout set for the function. 51 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 52 for (unsigned i = 0; i != RVLocs.size(); ++i) 53 if (RVLocs[i].isRegLoc()) 54 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 55 } 56 57 SDValue Chain = Op.getOperand(0); 58 SDValue Flag; 59 60 // Copy the result values into the output registers. 61 for (unsigned i = 0; i != RVLocs.size(); ++i) { 62 CCValAssign &VA = RVLocs[i]; 63 assert(VA.isRegLoc() && "Can only return in registers!"); 64 65 // ISD::RET => ret chain, (regnum1,val1), ... 66 // So i*2+1 index only the regnums. 67 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 68 Op.getOperand(i*2+1), Flag); 69 70 // Guarantee that all emitted copies are stuck together with flags. 71 Flag = Chain.getValue(1); 72 } 73 74 if (Flag.getNode()) 75 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 76 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain); 77} 78 79/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 80/// either one or two GPRs, including FP values. TODO: we should pass FP values 81/// in FP registers for fastcc functions. 82SDValue 83SparcTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, 84 SelectionDAG &DAG) { 85 MachineFunction &MF = DAG.getMachineFunction(); 86 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 87 SDValue Root = Op.getOperand(0); 88 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 89 unsigned CC = MF.getFunction()->getCallingConv(); 90 DebugLoc dl = Op.getDebugLoc(); 91 92 // Assign locations to all of the incoming arguments. 93 SmallVector<CCValAssign, 16> ArgLocs; 94 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); 95 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Sparc32); 96 97 static const unsigned ArgRegs[] = { 98 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 99 }; 100 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 101 unsigned ArgOffset = 68; 102 103 SmallVector<SDValue, 16> ArgValues; 104 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 105 SDValue ArgValue; 106 CCValAssign &VA = ArgLocs[i]; 107 // FIXME: We ignore the register assignments of AnalyzeFormalArguments 108 // because it doesn't know how to split a double into two i32 registers. 109 MVT ObjectVT = VA.getValVT(); 110 switch (ObjectVT.getSimpleVT()) { 111 default: llvm_unreachable("Unhandled argument type!"); 112 case MVT::i1: 113 case MVT::i8: 114 case MVT::i16: 115 case MVT::i32: 116 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 117 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 118 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 119 SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); 120 if (ObjectVT != MVT::i32) { 121 unsigned AssertOp = ISD::AssertSext; 122 Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg, 123 DAG.getValueType(ObjectVT)); 124 Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg); 125 } 126 ArgValues.push_back(Arg); 127 } else { 128 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 129 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 130 SDValue Load; 131 if (ObjectVT == MVT::i32) { 132 Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0); 133 } else { 134 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 135 136 // Sparc is big endian, so add an offset based on the ObjectVT. 137 unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8); 138 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 139 DAG.getConstant(Offset, MVT::i32)); 140 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr, 141 NULL, 0, ObjectVT); 142 Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load); 143 } 144 ArgValues.push_back(Load); 145 } 146 147 ArgOffset += 4; 148 break; 149 case MVT::f32: 150 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 151 // FP value is passed in an integer register. 152 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 153 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 154 SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); 155 156 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg); 157 ArgValues.push_back(Arg); 158 } else { 159 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 160 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 161 SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0); 162 ArgValues.push_back(Load); 163 } 164 ArgOffset += 4; 165 break; 166 167 case MVT::i64: 168 case MVT::f64: 169 { 170 SDValue HiVal; 171 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 172 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 173 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 174 HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32); 175 } else { 176 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 177 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 178 HiVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0); 179 } 180 181 SDValue LoVal; 182 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 183 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 184 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 185 LoVal = DAG.getCopyFromReg(Root, dl, VRegLo, MVT::i32); 186 } else { 187 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 188 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 189 LoVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0); 190 } 191 192 // Compose the two halves together into an i64 unit. 193 SDValue WholeValue = 194 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 195 196 // If we want a double, do a bit convert. 197 if (ObjectVT == MVT::f64) 198 WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue); 199 200 ArgValues.push_back(WholeValue); 201 } 202 ArgOffset += 8; 203 break; 204 } 205 } 206 207 // Store remaining ArgRegs to the stack if this is a varargs function. 208 if (isVarArg) { 209 // Remember the vararg offset for the va_start implementation. 210 VarArgsFrameOffset = ArgOffset; 211 212 std::vector<SDValue> OutChains; 213 214 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 215 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 216 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 217 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 218 219 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 220 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 221 222 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0)); 223 ArgOffset += 4; 224 } 225 226 if (!OutChains.empty()) { 227 OutChains.push_back(Root); 228 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 229 &OutChains[0], OutChains.size()); 230 } 231 } 232 233 ArgValues.push_back(Root); 234 235 // Return the new list of results. 236 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 237 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 238} 239 240static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { 241 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 242 unsigned CallingConv = TheCall->getCallingConv(); 243 SDValue Chain = TheCall->getChain(); 244 SDValue Callee = TheCall->getCallee(); 245 bool isVarArg = TheCall->isVarArg(); 246 DebugLoc dl = TheCall->getDebugLoc(); 247 248#if 0 249 // Analyze operands of the call, assigning locations to each operand. 250 SmallVector<CCValAssign, 16> ArgLocs; 251 CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs); 252 CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32); 253 254 // Get the size of the outgoing arguments stack space requirement. 255 unsigned ArgsSize = CCInfo.getNextStackOffset(); 256 // FIXME: We can't use this until f64 is known to take two GPRs. 257#else 258 (void)CC_Sparc32; 259 260 // Count the size of the outgoing arguments. 261 unsigned ArgsSize = 0; 262 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { 263 switch (TheCall->getArg(i).getValueType().getSimpleVT()) { 264 default: llvm_unreachable("Unknown value type!"); 265 case MVT::i1: 266 case MVT::i8: 267 case MVT::i16: 268 case MVT::i32: 269 case MVT::f32: 270 ArgsSize += 4; 271 break; 272 case MVT::i64: 273 case MVT::f64: 274 ArgsSize += 8; 275 break; 276 } 277 } 278 if (ArgsSize > 4*6) 279 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 280 else 281 ArgsSize = 0; 282#endif 283 284 // Keep stack frames 8-byte aligned. 285 ArgsSize = (ArgsSize+7) & ~7; 286 287 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 288 289 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 290 SmallVector<SDValue, 8> MemOpChains; 291 292#if 0 293 // Walk the register/memloc assignments, inserting copies/loads. 294 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 295 CCValAssign &VA = ArgLocs[i]; 296 297 // Arguments start after the 5 first operands of ISD::CALL 298 SDValue Arg = TheCall->getArg(i); 299 300 // Promote the value if needed. 301 switch (VA.getLocInfo()) { 302 default: llvm_unreachable("Unknown loc info!"); 303 case CCValAssign::Full: break; 304 case CCValAssign::SExt: 305 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 306 break; 307 case CCValAssign::ZExt: 308 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 309 break; 310 case CCValAssign::AExt: 311 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 312 break; 313 } 314 315 // Arguments that can be passed on register must be kept at 316 // RegsToPass vector 317 if (VA.isRegLoc()) { 318 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 319 continue; 320 } 321 322 assert(VA.isMemLoc()); 323 324 // Create a store off the stack pointer for this argument. 325 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 326 // FIXME: VERIFY THAT 68 IS RIGHT. 327 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68); 328 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 329 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 330 } 331 332#else 333 static const unsigned ArgRegs[] = { 334 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 335 }; 336 unsigned ArgOffset = 68; 337 338 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) { 339 SDValue Val = TheCall->getArg(i); 340 MVT ObjectVT = Val.getValueType(); 341 SDValue ValToStore(0, 0); 342 unsigned ObjSize; 343 switch (ObjectVT.getSimpleVT()) { 344 default: llvm_unreachable("Unhandled argument type!"); 345 case MVT::i32: 346 ObjSize = 4; 347 348 if (RegsToPass.size() >= 6) { 349 ValToStore = Val; 350 } else { 351 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); 352 } 353 break; 354 case MVT::f32: 355 ObjSize = 4; 356 if (RegsToPass.size() >= 6) { 357 ValToStore = Val; 358 } else { 359 // Convert this to a FP value in an int reg. 360 Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val); 361 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); 362 } 363 break; 364 case MVT::f64: { 365 ObjSize = 8; 366 if (RegsToPass.size() >= 6) { 367 ValToStore = Val; // Whole thing is passed in memory. 368 break; 369 } 370 371 // Break into top and bottom parts by storing to the stack and loading 372 // out the parts as integers. Top part goes in a reg. 373 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 374 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 375 Val, StackPtr, NULL, 0); 376 // Sparc is big-endian, so the high part comes first. 377 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); 378 // Increment the pointer to the other half. 379 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 380 DAG.getIntPtrConstant(4)); 381 // Load the low part. 382 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); 383 384 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); 385 386 if (RegsToPass.size() >= 6) { 387 ValToStore = Lo; 388 ArgOffset += 4; 389 ObjSize = 4; 390 } else { 391 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo)); 392 } 393 break; 394 } 395 case MVT::i64: { 396 ObjSize = 8; 397 if (RegsToPass.size() >= 6) { 398 ValToStore = Val; // Whole thing is passed in memory. 399 break; 400 } 401 402 // Split the value into top and bottom part. Top part goes in a reg. 403 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, 404 DAG.getConstant(1, MVT::i32)); 405 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, 406 DAG.getConstant(0, MVT::i32)); 407 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); 408 409 if (RegsToPass.size() >= 6) { 410 ValToStore = Lo; 411 ArgOffset += 4; 412 ObjSize = 4; 413 } else { 414 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo)); 415 } 416 break; 417 } 418 } 419 420 if (ValToStore.getNode()) { 421 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 422 SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32); 423 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 424 MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore, 425 PtrOff, NULL, 0)); 426 } 427 ArgOffset += ObjSize; 428 } 429#endif 430 431 // Emit all stores, make sure the occur before any copies into physregs. 432 if (!MemOpChains.empty()) 433 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 434 &MemOpChains[0], MemOpChains.size()); 435 436 // Build a sequence of copy-to-reg nodes chained together with token 437 // chain and flag operands which copy the outgoing args into registers. 438 // The InFlag in necessary since all emited instructions must be 439 // stuck together. 440 SDValue InFlag; 441 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 442 unsigned Reg = RegsToPass[i].first; 443 // Remap I0->I7 -> O0->O7. 444 if (Reg >= SP::I0 && Reg <= SP::I7) 445 Reg = Reg-SP::I0+SP::O0; 446 447 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 448 InFlag = Chain.getValue(1); 449 } 450 451 // If the callee is a GlobalAddress node (quite common, every direct call is) 452 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 453 // Likewise ExternalSymbol -> TargetExternalSymbol. 454 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 455 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 456 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 457 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 458 459 std::vector<MVT> NodeTys; 460 NodeTys.push_back(MVT::Other); // Returns a chain 461 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 462 SDValue Ops[] = { Chain, Callee, InFlag }; 463 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2); 464 InFlag = Chain.getValue(1); 465 466 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 467 DAG.getIntPtrConstant(0, true), InFlag); 468 InFlag = Chain.getValue(1); 469 470 // Assign locations to each value returned by this call. 471 SmallVector<CCValAssign, 16> RVLocs; 472 CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), 473 RVLocs, *DAG.getContext()); 474 475 RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32); 476 SmallVector<SDValue, 8> ResultVals; 477 478 // Copy all of the result registers out of their specified physreg. 479 for (unsigned i = 0; i != RVLocs.size(); ++i) { 480 unsigned Reg = RVLocs[i].getLocReg(); 481 482 // Remap I0->I7 -> O0->O7. 483 if (Reg >= SP::I0 && Reg <= SP::I7) 484 Reg = Reg-SP::I0+SP::O0; 485 486 Chain = DAG.getCopyFromReg(Chain, dl, Reg, 487 RVLocs[i].getValVT(), InFlag).getValue(1); 488 InFlag = Chain.getValue(2); 489 ResultVals.push_back(Chain.getValue(0)); 490 } 491 492 ResultVals.push_back(Chain); 493 494 // Merge everything together with a MERGE_VALUES node. 495 return DAG.getNode(ISD::MERGE_VALUES, dl, 496 TheCall->getVTList(), &ResultVals[0], 497 ResultVals.size()); 498} 499 500 501 502//===----------------------------------------------------------------------===// 503// TargetLowering Implementation 504//===----------------------------------------------------------------------===// 505 506/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 507/// condition. 508static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 509 switch (CC) { 510 default: llvm_unreachable("Unknown integer condition code!"); 511 case ISD::SETEQ: return SPCC::ICC_E; 512 case ISD::SETNE: return SPCC::ICC_NE; 513 case ISD::SETLT: return SPCC::ICC_L; 514 case ISD::SETGT: return SPCC::ICC_G; 515 case ISD::SETLE: return SPCC::ICC_LE; 516 case ISD::SETGE: return SPCC::ICC_GE; 517 case ISD::SETULT: return SPCC::ICC_CS; 518 case ISD::SETULE: return SPCC::ICC_LEU; 519 case ISD::SETUGT: return SPCC::ICC_GU; 520 case ISD::SETUGE: return SPCC::ICC_CC; 521 } 522} 523 524/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 525/// FCC condition. 526static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 527 switch (CC) { 528 default: llvm_unreachable("Unknown fp condition code!"); 529 case ISD::SETEQ: 530 case ISD::SETOEQ: return SPCC::FCC_E; 531 case ISD::SETNE: 532 case ISD::SETUNE: return SPCC::FCC_NE; 533 case ISD::SETLT: 534 case ISD::SETOLT: return SPCC::FCC_L; 535 case ISD::SETGT: 536 case ISD::SETOGT: return SPCC::FCC_G; 537 case ISD::SETLE: 538 case ISD::SETOLE: return SPCC::FCC_LE; 539 case ISD::SETGE: 540 case ISD::SETOGE: return SPCC::FCC_GE; 541 case ISD::SETULT: return SPCC::FCC_UL; 542 case ISD::SETULE: return SPCC::FCC_ULE; 543 case ISD::SETUGT: return SPCC::FCC_UG; 544 case ISD::SETUGE: return SPCC::FCC_UGE; 545 case ISD::SETUO: return SPCC::FCC_U; 546 case ISD::SETO: return SPCC::FCC_O; 547 case ISD::SETONE: return SPCC::FCC_LG; 548 case ISD::SETUEQ: return SPCC::FCC_UE; 549 } 550} 551 552class TargetLoweringObjectFileSparc : public TargetLoweringObjectFileELF { 553public: 554 void getSectionFlagsAsString(SectionKind Kind, 555 SmallVectorImpl<char> &Str) const { 556 if (Kind.isMergeableConst() || Kind.isMergeableCString()) 557 return TargetLoweringObjectFileELF::getSectionFlagsAsString(Kind, Str); 558 559 // FIXME: Inefficient. 560 std::string Res; 561 if (!Kind.isMetadata()) 562 Res += ",#alloc"; 563 if (Kind.isText()) 564 Res += ",#execinstr"; 565 if (Kind.isWriteable()) 566 Res += ",#write"; 567 if (Kind.isThreadLocal()) 568 Res += ",#tls"; 569 570 Str.append(Res.begin(), Res.end()); 571 } 572}; 573 574 575SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 576 : TargetLowering(TM, new TargetLoweringObjectFileSparc()) { 577 578 // Set up the register classes. 579 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 580 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 581 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 582 583 // Turn FP extload into load/fextend 584 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 585 // Sparc doesn't have i1 sign extending load 586 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 587 // Turn FP truncstore into trunc + store. 588 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 589 590 // Custom legalize GlobalAddress nodes into LO/HI parts. 591 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 592 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 593 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 594 595 // Sparc doesn't have sext_inreg, replace them with shl/sra 596 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 597 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 598 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 599 600 // Sparc has no REM or DIVREM operations. 601 setOperationAction(ISD::UREM, MVT::i32, Expand); 602 setOperationAction(ISD::SREM, MVT::i32, Expand); 603 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 604 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 605 606 // Custom expand fp<->sint 607 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 608 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 609 610 // Expand fp<->uint 611 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 612 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 613 614 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 615 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 616 617 // Sparc has no select or setcc: expand to SELECT_CC. 618 setOperationAction(ISD::SELECT, MVT::i32, Expand); 619 setOperationAction(ISD::SELECT, MVT::f32, Expand); 620 setOperationAction(ISD::SELECT, MVT::f64, Expand); 621 setOperationAction(ISD::SETCC, MVT::i32, Expand); 622 setOperationAction(ISD::SETCC, MVT::f32, Expand); 623 setOperationAction(ISD::SETCC, MVT::f64, Expand); 624 625 // Sparc doesn't have BRCOND either, it has BR_CC. 626 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 627 setOperationAction(ISD::BRIND, MVT::Other, Expand); 628 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 629 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 630 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 631 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 632 633 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 634 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 635 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 636 637 // SPARC has no intrinsics for these particular operations. 638 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 639 640 setOperationAction(ISD::FSIN , MVT::f64, Expand); 641 setOperationAction(ISD::FCOS , MVT::f64, Expand); 642 setOperationAction(ISD::FREM , MVT::f64, Expand); 643 setOperationAction(ISD::FSIN , MVT::f32, Expand); 644 setOperationAction(ISD::FCOS , MVT::f32, Expand); 645 setOperationAction(ISD::FREM , MVT::f32, Expand); 646 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 647 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 648 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 649 setOperationAction(ISD::ROTL , MVT::i32, Expand); 650 setOperationAction(ISD::ROTR , MVT::i32, Expand); 651 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 652 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 653 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 654 setOperationAction(ISD::FPOW , MVT::f64, Expand); 655 setOperationAction(ISD::FPOW , MVT::f32, Expand); 656 657 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 658 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 659 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 660 661 // FIXME: Sparc provides these multiplies, but we don't have them yet. 662 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 663 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 664 665 // We don't have line number support yet. 666 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 667 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 668 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 669 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 670 671 // RET must be custom lowered, to meet ABI requirements 672 setOperationAction(ISD::RET , MVT::Other, Custom); 673 674 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 675 setOperationAction(ISD::VASTART , MVT::Other, Custom); 676 // VAARG needs to be lowered to not do unaligned accesses for doubles. 677 setOperationAction(ISD::VAARG , MVT::Other, Custom); 678 679 // Use the default implementation. 680 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 681 setOperationAction(ISD::VAEND , MVT::Other, Expand); 682 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 683 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 684 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 685 686 // No debug info support yet. 687 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 688 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 689 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 690 setOperationAction(ISD::DECLARE, MVT::Other, Expand); 691 692 setStackPointerRegisterToSaveRestore(SP::O6); 693 694 if (TM.getSubtarget<SparcSubtarget>().isV9()) 695 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 696 697 computeRegisterProperties(); 698} 699 700const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 701 switch (Opcode) { 702 default: return 0; 703 case SPISD::CMPICC: return "SPISD::CMPICC"; 704 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 705 case SPISD::BRICC: return "SPISD::BRICC"; 706 case SPISD::BRFCC: return "SPISD::BRFCC"; 707 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 708 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 709 case SPISD::Hi: return "SPISD::Hi"; 710 case SPISD::Lo: return "SPISD::Lo"; 711 case SPISD::FTOI: return "SPISD::FTOI"; 712 case SPISD::ITOF: return "SPISD::ITOF"; 713 case SPISD::CALL: return "SPISD::CALL"; 714 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 715 } 716} 717 718/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 719/// be zero. Op is expected to be a target specific node. Used by DAG 720/// combiner. 721void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 722 const APInt &Mask, 723 APInt &KnownZero, 724 APInt &KnownOne, 725 const SelectionDAG &DAG, 726 unsigned Depth) const { 727 APInt KnownZero2, KnownOne2; 728 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 729 730 switch (Op.getOpcode()) { 731 default: break; 732 case SPISD::SELECT_ICC: 733 case SPISD::SELECT_FCC: 734 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 735 Depth+1); 736 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 737 Depth+1); 738 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 739 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 740 741 // Only known if known in both the LHS and RHS. 742 KnownOne &= KnownOne2; 743 KnownZero &= KnownZero2; 744 break; 745 } 746} 747 748// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 749// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 750static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 751 ISD::CondCode CC, unsigned &SPCC) { 752 if (isa<ConstantSDNode>(RHS) && 753 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 && 754 CC == ISD::SETNE && 755 ((LHS.getOpcode() == SPISD::SELECT_ICC && 756 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 757 (LHS.getOpcode() == SPISD::SELECT_FCC && 758 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 759 isa<ConstantSDNode>(LHS.getOperand(0)) && 760 isa<ConstantSDNode>(LHS.getOperand(1)) && 761 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 && 762 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) { 763 SDValue CMPCC = LHS.getOperand(3); 764 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 765 LHS = CMPCC.getOperand(0); 766 RHS = CMPCC.getOperand(1); 767 } 768} 769 770static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) { 771 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 772 // FIXME there isn't really any debug info here 773 DebugLoc dl = Op.getDebugLoc(); 774 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 775 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); 776 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); 777 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 778} 779 780static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) { 781 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 782 // FIXME there isn't really any debug info here 783 DebugLoc dl = Op.getDebugLoc(); 784 Constant *C = N->getConstVal(); 785 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 786 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); 787 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); 788 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 789} 790 791static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 792 DebugLoc dl = Op.getDebugLoc(); 793 // Convert the fp value to integer in an FP register. 794 assert(Op.getValueType() == MVT::i32); 795 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 796 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 797} 798 799static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 800 DebugLoc dl = Op.getDebugLoc(); 801 assert(Op.getOperand(0).getValueType() == MVT::i32); 802 SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); 803 // Convert the int value to FP in an FP register. 804 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 805} 806 807static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 808 SDValue Chain = Op.getOperand(0); 809 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 810 SDValue LHS = Op.getOperand(2); 811 SDValue RHS = Op.getOperand(3); 812 SDValue Dest = Op.getOperand(4); 813 DebugLoc dl = Op.getDebugLoc(); 814 unsigned Opc, SPCC = ~0U; 815 816 // If this is a br_cc of a "setcc", and if the setcc got lowered into 817 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 818 LookThroughSetCC(LHS, RHS, CC, SPCC); 819 820 // Get the condition flag. 821 SDValue CompareFlag; 822 if (LHS.getValueType() == MVT::i32) { 823 std::vector<MVT> VTs; 824 VTs.push_back(MVT::i32); 825 VTs.push_back(MVT::Flag); 826 SDValue Ops[2] = { LHS, RHS }; 827 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 828 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 829 Opc = SPISD::BRICC; 830 } else { 831 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); 832 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 833 Opc = SPISD::BRFCC; 834 } 835 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 836 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 837} 838 839static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 840 SDValue LHS = Op.getOperand(0); 841 SDValue RHS = Op.getOperand(1); 842 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 843 SDValue TrueVal = Op.getOperand(2); 844 SDValue FalseVal = Op.getOperand(3); 845 DebugLoc dl = Op.getDebugLoc(); 846 unsigned Opc, SPCC = ~0U; 847 848 // If this is a select_cc of a "setcc", and if the setcc got lowered into 849 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 850 LookThroughSetCC(LHS, RHS, CC, SPCC); 851 852 SDValue CompareFlag; 853 if (LHS.getValueType() == MVT::i32) { 854 std::vector<MVT> VTs; 855 VTs.push_back(LHS.getValueType()); // subcc returns a value 856 VTs.push_back(MVT::Flag); 857 SDValue Ops[2] = { LHS, RHS }; 858 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 859 Opc = SPISD::SELECT_ICC; 860 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 861 } else { 862 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); 863 Opc = SPISD::SELECT_FCC; 864 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 865 } 866 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 867 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 868} 869 870static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 871 SparcTargetLowering &TLI) { 872 // vastart just stores the address of the VarArgsFrameIndex slot into the 873 // memory location argument. 874 DebugLoc dl = Op.getDebugLoc(); 875 SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, 876 DAG.getRegister(SP::I6, MVT::i32), 877 DAG.getConstant(TLI.getVarArgsFrameOffset(), 878 MVT::i32)); 879 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 880 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0); 881} 882 883static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 884 SDNode *Node = Op.getNode(); 885 MVT VT = Node->getValueType(0); 886 SDValue InChain = Node->getOperand(0); 887 SDValue VAListPtr = Node->getOperand(1); 888 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 889 DebugLoc dl = Node->getDebugLoc(); 890 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0); 891 // Increment the pointer, VAList, to the next vaarg 892 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 893 DAG.getConstant(VT.getSizeInBits()/8, 894 MVT::i32)); 895 // Store the incremented VAList to the legalized pointer 896 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 897 VAListPtr, SV, 0); 898 // Load the actual argument out of the pointer VAList, unless this is an 899 // f64 load. 900 if (VT != MVT::f64) 901 return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0); 902 903 // Otherwise, load it as i64, then do a bitconvert. 904 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0); 905 906 // Bit-Convert the value to f64. 907 SDValue Ops[2] = { 908 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V), 909 V.getValue(1) 910 }; 911 return DAG.getMergeValues(Ops, 2, dl); 912} 913 914static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 915 SDValue Chain = Op.getOperand(0); // Legalize the chain. 916 SDValue Size = Op.getOperand(1); // Legalize the size. 917 DebugLoc dl = Op.getDebugLoc(); 918 919 unsigned SPReg = SP::O6; 920 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 921 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 922 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 923 924 // The resultant pointer is actually 16 words from the bottom of the stack, 925 // to provide a register spill area. 926 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 927 DAG.getConstant(96, MVT::i32)); 928 SDValue Ops[2] = { NewVal, Chain }; 929 return DAG.getMergeValues(Ops, 2, dl); 930} 931 932 933SDValue SparcTargetLowering:: 934LowerOperation(SDValue Op, SelectionDAG &DAG) { 935 switch (Op.getOpcode()) { 936 default: llvm_unreachable("Should not custom lower this!"); 937 // Frame & Return address. Currently unimplemented 938 case ISD::RETURNADDR: return SDValue(); 939 case ISD::FRAMEADDR: return SDValue(); 940 case ISD::GlobalTLSAddress: 941 llvm_unreachable("TLS not implemented for Sparc."); 942 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 943 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG); 944 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 945 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 946 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 947 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 948 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 949 case ISD::VAARG: return LowerVAARG(Op, DAG); 950 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 951 case ISD::CALL: return LowerCALL(Op, DAG); 952 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 953 case ISD::RET: return LowerRET(Op, DAG); 954 } 955} 956 957MachineBasicBlock * 958SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 959 MachineBasicBlock *BB) const { 960 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 961 unsigned BROpcode; 962 unsigned CC; 963 DebugLoc dl = MI->getDebugLoc(); 964 // Figure out the conditional branch opcode to use for this select_cc. 965 switch (MI->getOpcode()) { 966 default: llvm_unreachable("Unknown SELECT_CC!"); 967 case SP::SELECT_CC_Int_ICC: 968 case SP::SELECT_CC_FP_ICC: 969 case SP::SELECT_CC_DFP_ICC: 970 BROpcode = SP::BCOND; 971 break; 972 case SP::SELECT_CC_Int_FCC: 973 case SP::SELECT_CC_FP_FCC: 974 case SP::SELECT_CC_DFP_FCC: 975 BROpcode = SP::FBCOND; 976 break; 977 } 978 979 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 980 981 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 982 // control-flow pattern. The incoming instruction knows the destination vreg 983 // to set, the condition code register to branch on, the true/false values to 984 // select between, and a branch opcode to use. 985 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 986 MachineFunction::iterator It = BB; 987 ++It; 988 989 // thisMBB: 990 // ... 991 // TrueVal = ... 992 // [f]bCC copy1MBB 993 // fallthrough --> copy0MBB 994 MachineBasicBlock *thisMBB = BB; 995 MachineFunction *F = BB->getParent(); 996 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 997 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 998 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 999 F->insert(It, copy0MBB); 1000 F->insert(It, sinkMBB); 1001 // Update machine-CFG edges by transferring all successors of the current 1002 // block to the new block which will contain the Phi node for the select. 1003 sinkMBB->transferSuccessors(BB); 1004 // Next, add the true and fallthrough blocks as its successors. 1005 BB->addSuccessor(copy0MBB); 1006 BB->addSuccessor(sinkMBB); 1007 1008 // copy0MBB: 1009 // %FalseValue = ... 1010 // # fallthrough to sinkMBB 1011 BB = copy0MBB; 1012 1013 // Update machine-CFG edges 1014 BB->addSuccessor(sinkMBB); 1015 1016 // sinkMBB: 1017 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1018 // ... 1019 BB = sinkMBB; 1020 BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1021 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1022 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1023 1024 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1025 return BB; 1026} 1027 1028//===----------------------------------------------------------------------===// 1029// Sparc Inline Assembly Support 1030//===----------------------------------------------------------------------===// 1031 1032/// getConstraintType - Given a constraint letter, return the type of 1033/// constraint it is for this target. 1034SparcTargetLowering::ConstraintType 1035SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1036 if (Constraint.size() == 1) { 1037 switch (Constraint[0]) { 1038 default: break; 1039 case 'r': return C_RegisterClass; 1040 } 1041 } 1042 1043 return TargetLowering::getConstraintType(Constraint); 1044} 1045 1046std::pair<unsigned, const TargetRegisterClass*> 1047SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1048 MVT VT) const { 1049 if (Constraint.size() == 1) { 1050 switch (Constraint[0]) { 1051 case 'r': 1052 return std::make_pair(0U, SP::IntRegsRegisterClass); 1053 } 1054 } 1055 1056 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1057} 1058 1059std::vector<unsigned> SparcTargetLowering:: 1060getRegClassForInlineAsmConstraint(const std::string &Constraint, 1061 MVT VT) const { 1062 if (Constraint.size() != 1) 1063 return std::vector<unsigned>(); 1064 1065 switch (Constraint[0]) { 1066 default: break; 1067 case 'r': 1068 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3, 1069 SP::L4, SP::L5, SP::L6, SP::L7, 1070 SP::I0, SP::I1, SP::I2, SP::I3, 1071 SP::I4, SP::I5, 1072 SP::O0, SP::O1, SP::O2, SP::O3, 1073 SP::O4, SP::O5, SP::O7, 0); 1074 } 1075 1076 return std::vector<unsigned>(); 1077} 1078 1079bool 1080SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1081 // The Sparc target isn't yet aware of offsets. 1082 return false; 1083} 1084 1085/// getFunctionAlignment - Return the Log2 alignment of this function. 1086unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const { 1087 return 4; 1088} 1089