SparcISelLowering.cpp revision fc5d305597ea6336d75bd7f3b741e8d57d6a5105
1 2//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 3// 4// The LLVM Compiler Infrastructure 5// 6// This file is distributed under the University of Illinois Open Source 7// License. See LICENSE.TXT for details. 8// 9//===----------------------------------------------------------------------===// 10// 11// This file implements the interfaces that Sparc uses to lower LLVM code into a 12// selection DAG. 13// 14//===----------------------------------------------------------------------===// 15 16#include "SparcISelLowering.h" 17#include "SparcTargetMachine.h" 18#include "SparcMachineFunctionInfo.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Function.h" 21#include "llvm/Module.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29#include "llvm/ADT/VectorExtras.h" 30#include "llvm/Support/ErrorHandling.h" 31using namespace llvm; 32 33 34//===----------------------------------------------------------------------===// 35// Calling Convention Implementation 36//===----------------------------------------------------------------------===// 37 38static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 39 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 40 ISD::ArgFlagsTy &ArgFlags, CCState &State) 41{ 42 assert (ArgFlags.isSRet()); 43 44 //Assign SRet argument 45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 46 0, 47 LocVT, LocInfo)); 48 return true; 49} 50 51static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 52 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, CCState &State) 54{ 55 static const unsigned RegList[] = { 56 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 57 }; 58 //Try to get first reg 59 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 60 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 61 } else { 62 //Assign whole thing in stack 63 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 64 State.AllocateStack(8,4), 65 LocVT, LocInfo)); 66 return true; 67 } 68 69 //Try to get second reg 70 if (unsigned Reg = State.AllocateReg(RegList, 6)) 71 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 72 else 73 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 74 State.AllocateStack(4,4), 75 LocVT, LocInfo)); 76 return true; 77} 78 79#include "SparcGenCallingConv.inc" 80 81SDValue 82SparcTargetLowering::LowerReturn(SDValue Chain, 83 CallingConv::ID CallConv, bool isVarArg, 84 const SmallVectorImpl<ISD::OutputArg> &Outs, 85 const SmallVectorImpl<SDValue> &OutVals, 86 DebugLoc dl, SelectionDAG &DAG) const { 87 88 MachineFunction &MF = DAG.getMachineFunction(); 89 90 // CCValAssign - represent the assignment of the return value to locations. 91 SmallVector<CCValAssign, 16> RVLocs; 92 93 // CCState - Info about the registers and stack slot. 94 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), 95 RVLocs, *DAG.getContext()); 96 97 // Analize return values. 98 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 99 100 // If this is the first return lowered for this function, add the regs to the 101 // liveout set for the function. 102 if (MF.getRegInfo().liveout_empty()) { 103 for (unsigned i = 0; i != RVLocs.size(); ++i) 104 if (RVLocs[i].isRegLoc()) 105 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 106 } 107 108 SDValue Flag; 109 110 // Copy the result values into the output registers. 111 for (unsigned i = 0; i != RVLocs.size(); ++i) { 112 CCValAssign &VA = RVLocs[i]; 113 assert(VA.isRegLoc() && "Can only return in registers!"); 114 115 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 116 OutVals[i], Flag); 117 118 // Guarantee that all emitted copies are stuck together with flags. 119 Flag = Chain.getValue(1); 120 } 121 122 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot 123 // If the function returns a struct, copy the SRetReturnReg to I0 124 if (MF.getFunction()->hasStructRetAttr()) { 125 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 126 unsigned Reg = SFI->getSRetReturnReg(); 127 if (!Reg) 128 llvm_unreachable("sret virtual register not created in the entry block"); 129 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 130 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); 131 Flag = Chain.getValue(1); 132 if (MF.getRegInfo().liveout_empty()) 133 MF.getRegInfo().addLiveOut(SP::I0); 134 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 135 } 136 137 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32); 138 139 if (Flag.getNode()) 140 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 141 RetAddrOffsetNode, Flag); 142 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 143 RetAddrOffsetNode); 144} 145 146/// LowerFormalArguments - V8 uses a very simple ABI, where all values are 147/// passed in either one or two GPRs, including FP values. TODO: we should 148/// pass FP values in FP registers for fastcc functions. 149SDValue 150SparcTargetLowering::LowerFormalArguments(SDValue Chain, 151 CallingConv::ID CallConv, bool isVarArg, 152 const SmallVectorImpl<ISD::InputArg> 153 &Ins, 154 DebugLoc dl, SelectionDAG &DAG, 155 SmallVectorImpl<SDValue> &InVals) 156 const { 157 158 MachineFunction &MF = DAG.getMachineFunction(); 159 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 160 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 161 162 // Assign locations to all of the incoming arguments. 163 SmallVector<CCValAssign, 16> ArgLocs; 164 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 165 ArgLocs, *DAG.getContext()); 166 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 167 168 const unsigned StackOffset = 92; 169 170 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 171 CCValAssign &VA = ArgLocs[i]; 172 173 if (i == 0 && Ins[i].Flags.isSRet()) { 174 //Get SRet from [%fp+64] 175 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 176 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 177 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 178 MachinePointerInfo(), 179 false, false, 0); 180 InVals.push_back(Arg); 181 continue; 182 } 183 184 if (VA.isRegLoc()) { 185 if (VA.needsCustom()) { 186 assert(VA.getLocVT() == MVT::f64); 187 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 188 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 189 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 190 191 assert(i+1 < e); 192 CCValAssign &NextVA = ArgLocs[++i]; 193 194 SDValue LoVal; 195 if (NextVA.isMemLoc()) { 196 int FrameIdx = MF.getFrameInfo()-> 197 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 198 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 199 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 200 MachinePointerInfo(), 201 false, false, 0); 202 } else { 203 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 204 &SP::IntRegsRegClass); 205 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 206 } 207 SDValue WholeValue = 208 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 209 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 210 InVals.push_back(WholeValue); 211 continue; 212 } 213 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 214 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 215 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 216 if (VA.getLocVT() == MVT::f32) 217 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 218 else if (VA.getLocVT() != MVT::i32) { 219 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 220 DAG.getValueType(VA.getLocVT())); 221 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 222 } 223 InVals.push_back(Arg); 224 continue; 225 } 226 227 assert(VA.isMemLoc()); 228 229 unsigned Offset = VA.getLocMemOffset()+StackOffset; 230 231 if (VA.needsCustom()) { 232 assert(VA.getValVT() == MVT::f64); 233 //If it is double-word aligned, just load. 234 if (Offset % 8 == 0) { 235 int FI = MF.getFrameInfo()->CreateFixedObject(8, 236 Offset, 237 true); 238 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 239 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 240 MachinePointerInfo(), 241 false,false, 0); 242 InVals.push_back(Load); 243 continue; 244 } 245 246 int FI = MF.getFrameInfo()->CreateFixedObject(4, 247 Offset, 248 true); 249 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 250 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 251 MachinePointerInfo(), 252 false, false, 0); 253 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 254 Offset+4, 255 true); 256 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 257 258 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 259 MachinePointerInfo(), 260 false, false, 0); 261 262 SDValue WholeValue = 263 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 264 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 265 InVals.push_back(WholeValue); 266 continue; 267 } 268 269 int FI = MF.getFrameInfo()->CreateFixedObject(4, 270 Offset, 271 true); 272 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 273 SDValue Load ; 274 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 275 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 276 MachinePointerInfo(), 277 false, false, 0); 278 } else { 279 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 280 // Sparc is big endian, so add an offset based on the ObjectVT. 281 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 282 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 283 DAG.getConstant(Offset, MVT::i32)); 284 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 285 MachinePointerInfo(), 286 VA.getValVT(), false, false,0); 287 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 288 } 289 InVals.push_back(Load); 290 } 291 292 if (MF.getFunction()->hasStructRetAttr()) { 293 //Copy the SRet Argument to SRetReturnReg 294 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 295 unsigned Reg = SFI->getSRetReturnReg(); 296 if (!Reg) { 297 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 298 SFI->setSRetReturnReg(Reg); 299 } 300 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 301 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 302 } 303 304 // Store remaining ArgRegs to the stack if this is a varargs function. 305 if (isVarArg) { 306 static const unsigned ArgRegs[] = { 307 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 308 }; 309 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 310 const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 311 unsigned ArgOffset = CCInfo.getNextStackOffset(); 312 if (NumAllocated == 6) 313 ArgOffset += StackOffset; 314 else { 315 assert(!ArgOffset); 316 ArgOffset = 68+4*NumAllocated; 317 } 318 319 // Remember the vararg offset for the va_start implementation. 320 FuncInfo->setVarArgsFrameOffset(ArgOffset); 321 322 std::vector<SDValue> OutChains; 323 324 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 325 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 326 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 327 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 328 329 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 330 true); 331 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 332 333 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 334 MachinePointerInfo(), 335 false, false, 0)); 336 ArgOffset += 4; 337 } 338 339 if (!OutChains.empty()) { 340 OutChains.push_back(Chain); 341 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 342 &OutChains[0], OutChains.size()); 343 } 344 } 345 346 return Chain; 347} 348 349SDValue 350SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 351 CallingConv::ID CallConv, bool isVarArg, 352 bool &isTailCall, 353 const SmallVectorImpl<ISD::OutputArg> &Outs, 354 const SmallVectorImpl<SDValue> &OutVals, 355 const SmallVectorImpl<ISD::InputArg> &Ins, 356 DebugLoc dl, SelectionDAG &DAG, 357 SmallVectorImpl<SDValue> &InVals) const { 358 // Sparc target does not yet support tail call optimization. 359 isTailCall = false; 360 361 // Analyze operands of the call, assigning locations to each operand. 362 SmallVector<CCValAssign, 16> ArgLocs; 363 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, 364 *DAG.getContext()); 365 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 366 367 // Get the size of the outgoing arguments stack space requirement. 368 unsigned ArgsSize = CCInfo.getNextStackOffset(); 369 370 // Keep stack frames 8-byte aligned. 371 ArgsSize = (ArgsSize+7) & ~7; 372 373 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 374 375 //Create local copies for byval args. 376 SmallVector<SDValue, 8> ByValArgs; 377 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 378 ISD::ArgFlagsTy Flags = Outs[i].Flags; 379 if (!Flags.isByVal()) 380 continue; 381 382 SDValue Arg = OutVals[i]; 383 unsigned Size = Flags.getByValSize(); 384 unsigned Align = Flags.getByValAlign(); 385 386 int FI = MFI->CreateStackObject(Size, Align, false); 387 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 388 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 389 390 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 391 false, //isVolatile, 392 (Size <= 32), //AlwaysInline if size <= 32 393 MachinePointerInfo(), MachinePointerInfo()); 394 ByValArgs.push_back(FIPtr); 395 } 396 397 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 398 399 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 400 SmallVector<SDValue, 8> MemOpChains; 401 402 const unsigned StackOffset = 92; 403 bool hasStructRetAttr = false; 404 // Walk the register/memloc assignments, inserting copies/loads. 405 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 406 i != e; 407 ++i, ++realArgIdx) { 408 CCValAssign &VA = ArgLocs[i]; 409 SDValue Arg = OutVals[realArgIdx]; 410 411 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 412 413 //Use local copy if it is a byval arg. 414 if (Flags.isByVal()) 415 Arg = ByValArgs[byvalArgIdx++]; 416 417 // Promote the value if needed. 418 switch (VA.getLocInfo()) { 419 default: llvm_unreachable("Unknown loc info!"); 420 case CCValAssign::Full: break; 421 case CCValAssign::SExt: 422 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 423 break; 424 case CCValAssign::ZExt: 425 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 426 break; 427 case CCValAssign::AExt: 428 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 429 break; 430 case CCValAssign::BCvt: 431 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 432 break; 433 } 434 435 if (Flags.isSRet()) { 436 assert(VA.needsCustom()); 437 // store SRet argument in %sp+64 438 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 439 SDValue PtrOff = DAG.getIntPtrConstant(64); 440 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 441 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 442 MachinePointerInfo(), 443 false, false, 0)); 444 hasStructRetAttr = true; 445 continue; 446 } 447 448 if (VA.needsCustom()) { 449 assert(VA.getLocVT() == MVT::f64); 450 451 if (VA.isMemLoc()) { 452 unsigned Offset = VA.getLocMemOffset() + StackOffset; 453 //if it is double-word aligned, just store. 454 if (Offset % 8 == 0) { 455 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 456 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 457 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 458 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 459 MachinePointerInfo(), 460 false, false, 0)); 461 continue; 462 } 463 } 464 465 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 466 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 467 Arg, StackPtr, MachinePointerInfo(), 468 false, false, 0); 469 // Sparc is big-endian, so the high part comes first. 470 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 471 MachinePointerInfo(), false, false, 0); 472 // Increment the pointer to the other half. 473 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 474 DAG.getIntPtrConstant(4)); 475 // Load the low part. 476 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 477 MachinePointerInfo(), false, false, 0); 478 479 if (VA.isRegLoc()) { 480 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 481 assert(i+1 != e); 482 CCValAssign &NextVA = ArgLocs[++i]; 483 if (NextVA.isRegLoc()) { 484 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 485 } else { 486 //Store the low part in stack. 487 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 488 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 489 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 490 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 491 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 492 MachinePointerInfo(), 493 false, false, 0)); 494 } 495 } else { 496 unsigned Offset = VA.getLocMemOffset() + StackOffset; 497 // Store the high part. 498 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 499 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 500 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 501 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 502 MachinePointerInfo(), 503 false, false, 0)); 504 // Store the low part. 505 PtrOff = DAG.getIntPtrConstant(Offset+4); 506 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 507 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 508 MachinePointerInfo(), 509 false, false, 0)); 510 } 511 continue; 512 } 513 514 // Arguments that can be passed on register must be kept at 515 // RegsToPass vector 516 if (VA.isRegLoc()) { 517 if (VA.getLocVT() != MVT::f32) { 518 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 519 continue; 520 } 521 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 522 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 523 continue; 524 } 525 526 assert(VA.isMemLoc()); 527 528 // Create a store off the stack pointer for this argument. 529 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 530 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 531 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 532 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 533 MachinePointerInfo(), 534 false, false, 0)); 535 } 536 537 538 // Emit all stores, make sure the occur before any copies into physregs. 539 if (!MemOpChains.empty()) 540 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 541 &MemOpChains[0], MemOpChains.size()); 542 543 // Build a sequence of copy-to-reg nodes chained together with token 544 // chain and flag operands which copy the outgoing args into registers. 545 // The InFlag in necessary since all emitted instructions must be 546 // stuck together. 547 SDValue InFlag; 548 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 549 unsigned Reg = RegsToPass[i].first; 550 // Remap I0->I7 -> O0->O7. 551 if (Reg >= SP::I0 && Reg <= SP::I7) 552 Reg = Reg-SP::I0+SP::O0; 553 554 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 555 InFlag = Chain.getValue(1); 556 } 557 558 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 559 560 // If the callee is a GlobalAddress node (quite common, every direct call is) 561 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 562 // Likewise ExternalSymbol -> TargetExternalSymbol. 563 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 564 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 565 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 566 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 567 568 // Returns a chain & a flag for retval copy to use 569 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 570 SmallVector<SDValue, 8> Ops; 571 Ops.push_back(Chain); 572 Ops.push_back(Callee); 573 if (hasStructRetAttr) 574 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 575 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 576 unsigned Reg = RegsToPass[i].first; 577 if (Reg >= SP::I0 && Reg <= SP::I7) 578 Reg = Reg-SP::I0+SP::O0; 579 580 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType())); 581 } 582 if (InFlag.getNode()) 583 Ops.push_back(InFlag); 584 585 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 586 InFlag = Chain.getValue(1); 587 588 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 589 DAG.getIntPtrConstant(0, true), InFlag); 590 InFlag = Chain.getValue(1); 591 592 // Assign locations to each value returned by this call. 593 SmallVector<CCValAssign, 16> RVLocs; 594 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), 595 RVLocs, *DAG.getContext()); 596 597 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 598 599 // Copy all of the result registers out of their specified physreg. 600 for (unsigned i = 0; i != RVLocs.size(); ++i) { 601 unsigned Reg = RVLocs[i].getLocReg(); 602 603 // Remap I0->I7 -> O0->O7. 604 if (Reg >= SP::I0 && Reg <= SP::I7) 605 Reg = Reg-SP::I0+SP::O0; 606 607 Chain = DAG.getCopyFromReg(Chain, dl, Reg, 608 RVLocs[i].getValVT(), InFlag).getValue(1); 609 InFlag = Chain.getValue(2); 610 InVals.push_back(Chain.getValue(0)); 611 } 612 613 return Chain; 614} 615 616unsigned 617SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 618{ 619 const Function *CalleeFn = 0; 620 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 621 CalleeFn = dyn_cast<Function>(G->getGlobal()); 622 } else if (ExternalSymbolSDNode *E = 623 dyn_cast<ExternalSymbolSDNode>(Callee)) { 624 const Function *Fn = DAG.getMachineFunction().getFunction(); 625 const Module *M = Fn->getParent(); 626 CalleeFn = M->getFunction(E->getSymbol()); 627 } 628 629 if (!CalleeFn) 630 return 0; 631 632 assert(CalleeFn->hasStructRetAttr() && 633 "Callee does not have the StructRet attribute."); 634 635 const PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 636 const Type *ElementTy = Ty->getElementType(); 637 return getTargetData()->getTypeAllocSize(ElementTy); 638} 639 640//===----------------------------------------------------------------------===// 641// TargetLowering Implementation 642//===----------------------------------------------------------------------===// 643 644/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 645/// condition. 646static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 647 switch (CC) { 648 default: llvm_unreachable("Unknown integer condition code!"); 649 case ISD::SETEQ: return SPCC::ICC_E; 650 case ISD::SETNE: return SPCC::ICC_NE; 651 case ISD::SETLT: return SPCC::ICC_L; 652 case ISD::SETGT: return SPCC::ICC_G; 653 case ISD::SETLE: return SPCC::ICC_LE; 654 case ISD::SETGE: return SPCC::ICC_GE; 655 case ISD::SETULT: return SPCC::ICC_CS; 656 case ISD::SETULE: return SPCC::ICC_LEU; 657 case ISD::SETUGT: return SPCC::ICC_GU; 658 case ISD::SETUGE: return SPCC::ICC_CC; 659 } 660} 661 662/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 663/// FCC condition. 664static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 665 switch (CC) { 666 default: llvm_unreachable("Unknown fp condition code!"); 667 case ISD::SETEQ: 668 case ISD::SETOEQ: return SPCC::FCC_E; 669 case ISD::SETNE: 670 case ISD::SETUNE: return SPCC::FCC_NE; 671 case ISD::SETLT: 672 case ISD::SETOLT: return SPCC::FCC_L; 673 case ISD::SETGT: 674 case ISD::SETOGT: return SPCC::FCC_G; 675 case ISD::SETLE: 676 case ISD::SETOLE: return SPCC::FCC_LE; 677 case ISD::SETGE: 678 case ISD::SETOGE: return SPCC::FCC_GE; 679 case ISD::SETULT: return SPCC::FCC_UL; 680 case ISD::SETULE: return SPCC::FCC_ULE; 681 case ISD::SETUGT: return SPCC::FCC_UG; 682 case ISD::SETUGE: return SPCC::FCC_UGE; 683 case ISD::SETUO: return SPCC::FCC_U; 684 case ISD::SETO: return SPCC::FCC_O; 685 case ISD::SETONE: return SPCC::FCC_LG; 686 case ISD::SETUEQ: return SPCC::FCC_UE; 687 } 688} 689 690SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 691 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 692 693 // Set up the register classes. 694 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 695 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 696 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 697 698 // Turn FP extload into load/fextend 699 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 700 // Sparc doesn't have i1 sign extending load 701 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 702 // Turn FP truncstore into trunc + store. 703 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 704 705 // Custom legalize GlobalAddress nodes into LO/HI parts. 706 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 707 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 708 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 709 710 // Sparc doesn't have sext_inreg, replace them with shl/sra 711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 713 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 714 715 // Sparc has no REM or DIVREM operations. 716 setOperationAction(ISD::UREM, MVT::i32, Expand); 717 setOperationAction(ISD::SREM, MVT::i32, Expand); 718 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 719 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 720 721 // Custom expand fp<->sint 722 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 723 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 724 725 // Expand fp<->uint 726 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 727 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 728 729 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 730 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 731 732 // Sparc has no select or setcc: expand to SELECT_CC. 733 setOperationAction(ISD::SELECT, MVT::i32, Expand); 734 setOperationAction(ISD::SELECT, MVT::f32, Expand); 735 setOperationAction(ISD::SELECT, MVT::f64, Expand); 736 setOperationAction(ISD::SETCC, MVT::i32, Expand); 737 setOperationAction(ISD::SETCC, MVT::f32, Expand); 738 setOperationAction(ISD::SETCC, MVT::f64, Expand); 739 740 // Sparc doesn't have BRCOND either, it has BR_CC. 741 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 742 setOperationAction(ISD::BRIND, MVT::Other, Expand); 743 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 744 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 745 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 746 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 747 748 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 749 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 750 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 751 752 // SPARC has no intrinsics for these particular operations. 753 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 754 755 setOperationAction(ISD::FSIN , MVT::f64, Expand); 756 setOperationAction(ISD::FCOS , MVT::f64, Expand); 757 setOperationAction(ISD::FREM , MVT::f64, Expand); 758 setOperationAction(ISD::FSIN , MVT::f32, Expand); 759 setOperationAction(ISD::FCOS , MVT::f32, Expand); 760 setOperationAction(ISD::FREM , MVT::f32, Expand); 761 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 762 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 763 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 764 setOperationAction(ISD::ROTL , MVT::i32, Expand); 765 setOperationAction(ISD::ROTR , MVT::i32, Expand); 766 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 767 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 768 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 769 setOperationAction(ISD::FPOW , MVT::f64, Expand); 770 setOperationAction(ISD::FPOW , MVT::f32, Expand); 771 772 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 773 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 774 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 775 776 // FIXME: Sparc provides these multiplies, but we don't have them yet. 777 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 778 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 779 780 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 781 782 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 783 setOperationAction(ISD::VASTART , MVT::Other, Custom); 784 // VAARG needs to be lowered to not do unaligned accesses for doubles. 785 setOperationAction(ISD::VAARG , MVT::Other, Custom); 786 787 // Use the default implementation. 788 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 789 setOperationAction(ISD::VAEND , MVT::Other, Expand); 790 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 791 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 792 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 793 794 // No debug info support yet. 795 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 796 797 setStackPointerRegisterToSaveRestore(SP::O6); 798 799 if (TM.getSubtarget<SparcSubtarget>().isV9()) 800 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 801 802 setMinFunctionAlignment(2); 803 804 computeRegisterProperties(); 805} 806 807const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 808 switch (Opcode) { 809 default: return 0; 810 case SPISD::CMPICC: return "SPISD::CMPICC"; 811 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 812 case SPISD::BRICC: return "SPISD::BRICC"; 813 case SPISD::BRFCC: return "SPISD::BRFCC"; 814 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 815 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 816 case SPISD::Hi: return "SPISD::Hi"; 817 case SPISD::Lo: return "SPISD::Lo"; 818 case SPISD::FTOI: return "SPISD::FTOI"; 819 case SPISD::ITOF: return "SPISD::ITOF"; 820 case SPISD::CALL: return "SPISD::CALL"; 821 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 822 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 823 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 824 } 825} 826 827/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 828/// be zero. Op is expected to be a target specific node. Used by DAG 829/// combiner. 830void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 831 const APInt &Mask, 832 APInt &KnownZero, 833 APInt &KnownOne, 834 const SelectionDAG &DAG, 835 unsigned Depth) const { 836 APInt KnownZero2, KnownOne2; 837 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 838 839 switch (Op.getOpcode()) { 840 default: break; 841 case SPISD::SELECT_ICC: 842 case SPISD::SELECT_FCC: 843 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 844 Depth+1); 845 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 846 Depth+1); 847 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 848 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 849 850 // Only known if known in both the LHS and RHS. 851 KnownOne &= KnownOne2; 852 KnownZero &= KnownZero2; 853 break; 854 } 855} 856 857// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 858// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 859static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 860 ISD::CondCode CC, unsigned &SPCC) { 861 if (isa<ConstantSDNode>(RHS) && 862 cast<ConstantSDNode>(RHS)->isNullValue() && 863 CC == ISD::SETNE && 864 ((LHS.getOpcode() == SPISD::SELECT_ICC && 865 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 866 (LHS.getOpcode() == SPISD::SELECT_FCC && 867 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 868 isa<ConstantSDNode>(LHS.getOperand(0)) && 869 isa<ConstantSDNode>(LHS.getOperand(1)) && 870 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 871 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 872 SDValue CMPCC = LHS.getOperand(3); 873 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 874 LHS = CMPCC.getOperand(0); 875 RHS = CMPCC.getOperand(1); 876 } 877} 878 879SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 880 SelectionDAG &DAG) const { 881 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 882 // FIXME there isn't really any debug info here 883 DebugLoc dl = Op.getDebugLoc(); 884 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 885 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); 886 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); 887 888 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 889 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 890 891 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 892 getPointerTy()); 893 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 894 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 895 GlobalBase, RelAddr); 896 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 897 AbsAddr, MachinePointerInfo(), false, false, 0); 898} 899 900SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 901 SelectionDAG &DAG) const { 902 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 903 // FIXME there isn't really any debug info here 904 DebugLoc dl = Op.getDebugLoc(); 905 const Constant *C = N->getConstVal(); 906 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 907 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); 908 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); 909 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 910 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 911 912 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 913 getPointerTy()); 914 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 915 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 916 GlobalBase, RelAddr); 917 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 918 AbsAddr, MachinePointerInfo(), false, false, 0); 919} 920 921static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 922 DebugLoc dl = Op.getDebugLoc(); 923 // Convert the fp value to integer in an FP register. 924 assert(Op.getValueType() == MVT::i32); 925 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 926 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 927} 928 929static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 930 DebugLoc dl = Op.getDebugLoc(); 931 assert(Op.getOperand(0).getValueType() == MVT::i32); 932 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 933 // Convert the int value to FP in an FP register. 934 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 935} 936 937static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 938 SDValue Chain = Op.getOperand(0); 939 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 940 SDValue LHS = Op.getOperand(2); 941 SDValue RHS = Op.getOperand(3); 942 SDValue Dest = Op.getOperand(4); 943 DebugLoc dl = Op.getDebugLoc(); 944 unsigned Opc, SPCC = ~0U; 945 946 // If this is a br_cc of a "setcc", and if the setcc got lowered into 947 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 948 LookThroughSetCC(LHS, RHS, CC, SPCC); 949 950 // Get the condition flag. 951 SDValue CompareFlag; 952 if (LHS.getValueType() == MVT::i32) { 953 std::vector<EVT> VTs; 954 VTs.push_back(MVT::i32); 955 VTs.push_back(MVT::Glue); 956 SDValue Ops[2] = { LHS, RHS }; 957 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 958 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 959 Opc = SPISD::BRICC; 960 } else { 961 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 962 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 963 Opc = SPISD::BRFCC; 964 } 965 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 966 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 967} 968 969static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 970 SDValue LHS = Op.getOperand(0); 971 SDValue RHS = Op.getOperand(1); 972 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 973 SDValue TrueVal = Op.getOperand(2); 974 SDValue FalseVal = Op.getOperand(3); 975 DebugLoc dl = Op.getDebugLoc(); 976 unsigned Opc, SPCC = ~0U; 977 978 // If this is a select_cc of a "setcc", and if the setcc got lowered into 979 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 980 LookThroughSetCC(LHS, RHS, CC, SPCC); 981 982 SDValue CompareFlag; 983 if (LHS.getValueType() == MVT::i32) { 984 std::vector<EVT> VTs; 985 VTs.push_back(LHS.getValueType()); // subcc returns a value 986 VTs.push_back(MVT::Glue); 987 SDValue Ops[2] = { LHS, RHS }; 988 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 989 Opc = SPISD::SELECT_ICC; 990 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 991 } else { 992 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 993 Opc = SPISD::SELECT_FCC; 994 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 995 } 996 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 997 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 998} 999 1000static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1001 const SparcTargetLowering &TLI) { 1002 MachineFunction &MF = DAG.getMachineFunction(); 1003 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 1004 1005 // vastart just stores the address of the VarArgsFrameIndex slot into the 1006 // memory location argument. 1007 DebugLoc dl = Op.getDebugLoc(); 1008 SDValue Offset = 1009 DAG.getNode(ISD::ADD, dl, MVT::i32, 1010 DAG.getRegister(SP::I6, MVT::i32), 1011 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(), 1012 MVT::i32)); 1013 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1014 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), 1015 MachinePointerInfo(SV), false, false, 0); 1016} 1017 1018static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 1019 SDNode *Node = Op.getNode(); 1020 EVT VT = Node->getValueType(0); 1021 SDValue InChain = Node->getOperand(0); 1022 SDValue VAListPtr = Node->getOperand(1); 1023 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1024 DebugLoc dl = Node->getDebugLoc(); 1025 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, 1026 MachinePointerInfo(SV), false, false, 0); 1027 // Increment the pointer, VAList, to the next vaarg 1028 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 1029 DAG.getConstant(VT.getSizeInBits()/8, 1030 MVT::i32)); 1031 // Store the incremented VAList to the legalized pointer 1032 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 1033 VAListPtr, MachinePointerInfo(SV), false, false, 0); 1034 // Load the actual argument out of the pointer VAList, unless this is an 1035 // f64 load. 1036 if (VT != MVT::f64) 1037 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 1038 false, false, 0); 1039 1040 // Otherwise, load it as i64, then do a bitconvert. 1041 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(), 1042 false, false, 0); 1043 1044 // Bit-Convert the value to f64. 1045 SDValue Ops[2] = { 1046 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V), 1047 V.getValue(1) 1048 }; 1049 return DAG.getMergeValues(Ops, 2, dl); 1050} 1051 1052static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1053 SDValue Chain = Op.getOperand(0); // Legalize the chain. 1054 SDValue Size = Op.getOperand(1); // Legalize the size. 1055 DebugLoc dl = Op.getDebugLoc(); 1056 1057 unsigned SPReg = SP::O6; 1058 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 1059 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 1060 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 1061 1062 // The resultant pointer is actually 16 words from the bottom of the stack, 1063 // to provide a register spill area. 1064 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 1065 DAG.getConstant(96, MVT::i32)); 1066 SDValue Ops[2] = { NewVal, Chain }; 1067 return DAG.getMergeValues(Ops, 2, dl); 1068} 1069 1070 1071static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 1072 DebugLoc dl = Op.getDebugLoc(); 1073 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 1074 dl, MVT::Other, DAG.getEntryNode()); 1075 return Chain; 1076} 1077 1078static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1079 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1080 MFI->setFrameAddressIsTaken(true); 1081 1082 EVT VT = Op.getValueType(); 1083 DebugLoc dl = Op.getDebugLoc(); 1084 unsigned FrameReg = SP::I6; 1085 1086 uint64_t depth = Op.getConstantOperandVal(0); 1087 1088 SDValue FrameAddr; 1089 if (depth == 0) 1090 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1091 else { 1092 // flush first to make sure the windowed registers' values are in stack 1093 SDValue Chain = getFLUSHW(Op, DAG); 1094 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 1095 1096 for (uint64_t i = 0; i != depth; ++i) { 1097 SDValue Ptr = DAG.getNode(ISD::ADD, 1098 dl, MVT::i32, 1099 FrameAddr, DAG.getIntPtrConstant(56)); 1100 FrameAddr = DAG.getLoad(MVT::i32, dl, 1101 Chain, 1102 Ptr, 1103 MachinePointerInfo(), false, false, 0); 1104 } 1105 } 1106 return FrameAddr; 1107} 1108 1109static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 1110 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1111 MFI->setReturnAddressIsTaken(true); 1112 1113 EVT VT = Op.getValueType(); 1114 DebugLoc dl = Op.getDebugLoc(); 1115 unsigned RetReg = SP::I7; 1116 1117 uint64_t depth = Op.getConstantOperandVal(0); 1118 1119 SDValue RetAddr; 1120 if (depth == 0) 1121 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 1122 else { 1123 // flush first to make sure the windowed registers' values are in stack 1124 SDValue Chain = getFLUSHW(Op, DAG); 1125 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 1126 1127 for (uint64_t i = 0; i != depth; ++i) { 1128 SDValue Ptr = DAG.getNode(ISD::ADD, 1129 dl, MVT::i32, 1130 RetAddr, 1131 DAG.getIntPtrConstant((i == depth-1)?60:56)); 1132 RetAddr = DAG.getLoad(MVT::i32, dl, 1133 Chain, 1134 Ptr, 1135 MachinePointerInfo(), false, false, 0); 1136 } 1137 } 1138 return RetAddr; 1139} 1140 1141SDValue SparcTargetLowering:: 1142LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1143 switch (Op.getOpcode()) { 1144 default: llvm_unreachable("Should not custom lower this!"); 1145 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1146 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1147 case ISD::GlobalTLSAddress: 1148 llvm_unreachable("TLS not implemented for Sparc."); 1149 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1150 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1151 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1152 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1153 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1154 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1155 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 1156 case ISD::VAARG: return LowerVAARG(Op, DAG); 1157 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1158 } 1159} 1160 1161MachineBasicBlock * 1162SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1163 MachineBasicBlock *BB) const { 1164 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1165 unsigned BROpcode; 1166 unsigned CC; 1167 DebugLoc dl = MI->getDebugLoc(); 1168 // Figure out the conditional branch opcode to use for this select_cc. 1169 switch (MI->getOpcode()) { 1170 default: llvm_unreachable("Unknown SELECT_CC!"); 1171 case SP::SELECT_CC_Int_ICC: 1172 case SP::SELECT_CC_FP_ICC: 1173 case SP::SELECT_CC_DFP_ICC: 1174 BROpcode = SP::BCOND; 1175 break; 1176 case SP::SELECT_CC_Int_FCC: 1177 case SP::SELECT_CC_FP_FCC: 1178 case SP::SELECT_CC_DFP_FCC: 1179 BROpcode = SP::FBCOND; 1180 break; 1181 } 1182 1183 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 1184 1185 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1186 // control-flow pattern. The incoming instruction knows the destination vreg 1187 // to set, the condition code register to branch on, the true/false values to 1188 // select between, and a branch opcode to use. 1189 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1190 MachineFunction::iterator It = BB; 1191 ++It; 1192 1193 // thisMBB: 1194 // ... 1195 // TrueVal = ... 1196 // [f]bCC copy1MBB 1197 // fallthrough --> copy0MBB 1198 MachineBasicBlock *thisMBB = BB; 1199 MachineFunction *F = BB->getParent(); 1200 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1201 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1202 F->insert(It, copy0MBB); 1203 F->insert(It, sinkMBB); 1204 1205 // Transfer the remainder of BB and its successor edges to sinkMBB. 1206 sinkMBB->splice(sinkMBB->begin(), BB, 1207 llvm::next(MachineBasicBlock::iterator(MI)), 1208 BB->end()); 1209 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1210 1211 // Add the true and fallthrough blocks as its successors. 1212 BB->addSuccessor(copy0MBB); 1213 BB->addSuccessor(sinkMBB); 1214 1215 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1216 1217 // copy0MBB: 1218 // %FalseValue = ... 1219 // # fallthrough to sinkMBB 1220 BB = copy0MBB; 1221 1222 // Update machine-CFG edges 1223 BB->addSuccessor(sinkMBB); 1224 1225 // sinkMBB: 1226 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1227 // ... 1228 BB = sinkMBB; 1229 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1230 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1231 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1232 1233 MI->eraseFromParent(); // The pseudo instruction is gone now. 1234 return BB; 1235} 1236 1237//===----------------------------------------------------------------------===// 1238// Sparc Inline Assembly Support 1239//===----------------------------------------------------------------------===// 1240 1241/// getConstraintType - Given a constraint letter, return the type of 1242/// constraint it is for this target. 1243SparcTargetLowering::ConstraintType 1244SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1245 if (Constraint.size() == 1) { 1246 switch (Constraint[0]) { 1247 default: break; 1248 case 'r': return C_RegisterClass; 1249 } 1250 } 1251 1252 return TargetLowering::getConstraintType(Constraint); 1253} 1254 1255std::pair<unsigned, const TargetRegisterClass*> 1256SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1257 EVT VT) const { 1258 if (Constraint.size() == 1) { 1259 switch (Constraint[0]) { 1260 case 'r': 1261 return std::make_pair(0U, SP::IntRegsRegisterClass); 1262 } 1263 } 1264 1265 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1266} 1267 1268std::vector<unsigned> SparcTargetLowering:: 1269getRegClassForInlineAsmConstraint(const std::string &Constraint, 1270 EVT VT) const { 1271 if (Constraint.size() != 1) 1272 return std::vector<unsigned>(); 1273 1274 switch (Constraint[0]) { 1275 default: break; 1276 case 'r': 1277 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3, 1278 SP::L4, SP::L5, SP::L6, SP::L7, 1279 SP::I0, SP::I1, SP::I2, SP::I3, 1280 SP::I4, SP::I5, 1281 SP::O0, SP::O1, SP::O2, SP::O3, 1282 SP::O4, SP::O5, SP::O7, 0); 1283 } 1284 1285 return std::vector<unsigned>(); 1286} 1287 1288bool 1289SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1290 // The Sparc target isn't yet aware of offsets. 1291 return false; 1292} 1293