SparcISelLowering.h revision 26932106562adbe3f186b8f32fd5057d9f373875 
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPARC_ISELLOWERING_H
16#define SPARC_ISELLOWERING_H
17
18#include "Sparc.h"
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22  class SparcSubtarget;
23
24  namespace SPISD {
25    enum {
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27      CMPICC,      // Compare two GPR operands, set icc+xcc.
28      CMPFCC,      // Compare two FP operands, set fcc.
29      BRICC,       // Branch to dest on icc condition
30      BRXCC,       // Branch to dest on xcc condition (64-bit only).
31      BRFCC,       // Branch to dest on fcc condition
32      SELECT_ICC,  // Select between two values using the current ICC flags.
33      SELECT_XCC,  // Select between two values using the current XCC flags.
34      SELECT_FCC,  // Select between two values using the current FCC flags.
35
36      Hi, Lo,      // Hi/Lo operations, typically on a global address.
37
38      FTOI,        // FP to Int within a FP register.
39      ITOF,        // Int to FP within a FP register.
40
41      CALL,        // A call instruction.
42      RET_FLAG,    // Return with a flag operand.
43      GLOBAL_BASE_REG, // Global base reg for PIC
44      FLUSHW       // FLUSH register windows to stack
45    };
46  }
47
48  class SparcTargetLowering : public TargetLowering {
49    const SparcSubtarget *Subtarget;
50  public:
51    SparcTargetLowering(TargetMachine &TM);
52    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
53
54    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
55    /// in Mask are known to be either zero or one and return them in the
56    /// KnownZero/KnownOne bitsets.
57    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
58                                                APInt &KnownZero,
59                                                APInt &KnownOne,
60                                                const SelectionDAG &DAG,
61                                                unsigned Depth = 0) const;
62
63    virtual MachineBasicBlock *
64      EmitInstrWithCustomInserter(MachineInstr *MI,
65                                  MachineBasicBlock *MBB) const;
66
67    virtual const char *getTargetNodeName(unsigned Opcode) const;
68
69    ConstraintType getConstraintType(const std::string &Constraint) const;
70    std::pair<unsigned, const TargetRegisterClass*>
71    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
72
73    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
74
75    virtual SDValue
76      LowerFormalArguments(SDValue Chain,
77                           CallingConv::ID CallConv,
78                           bool isVarArg,
79                           const SmallVectorImpl<ISD::InputArg> &Ins,
80                           DebugLoc dl, SelectionDAG &DAG,
81                           SmallVectorImpl<SDValue> &InVals) const;
82    SDValue LowerFormalArguments_32(SDValue Chain,
83                                    CallingConv::ID CallConv,
84                                    bool isVarArg,
85                                    const SmallVectorImpl<ISD::InputArg> &Ins,
86                                    DebugLoc dl, SelectionDAG &DAG,
87                                    SmallVectorImpl<SDValue> &InVals) const;
88    SDValue LowerFormalArguments_64(SDValue Chain,
89                                    CallingConv::ID CallConv,
90                                    bool isVarArg,
91                                    const SmallVectorImpl<ISD::InputArg> &Ins,
92                                    DebugLoc dl, SelectionDAG &DAG,
93                                    SmallVectorImpl<SDValue> &InVals) const;
94
95    virtual SDValue
96      LowerCall(TargetLowering::CallLoweringInfo &CLI,
97                SmallVectorImpl<SDValue> &InVals) const;
98    SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
99                         SmallVectorImpl<SDValue> &InVals) const;
100    SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
101                         SmallVectorImpl<SDValue> &InVals) const;
102
103    virtual SDValue
104      LowerReturn(SDValue Chain,
105                  CallingConv::ID CallConv, bool isVarArg,
106                  const SmallVectorImpl<ISD::OutputArg> &Outs,
107                  const SmallVectorImpl<SDValue> &OutVals,
108                  DebugLoc dl, SelectionDAG &DAG) const;
109    SDValue LowerReturn_32(SDValue Chain,
110                           CallingConv::ID CallConv, bool IsVarArg,
111                           const SmallVectorImpl<ISD::OutputArg> &Outs,
112                           const SmallVectorImpl<SDValue> &OutVals,
113                           DebugLoc DL, SelectionDAG &DAG) const;
114    SDValue LowerReturn_64(SDValue Chain,
115                           CallingConv::ID CallConv, bool IsVarArg,
116                           const SmallVectorImpl<ISD::OutputArg> &Outs,
117                           const SmallVectorImpl<SDValue> &OutVals,
118                           DebugLoc DL, SelectionDAG &DAG) const;
119
120    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
121    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
122
123    unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
124    SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
125    SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
126                         SelectionDAG &DAG) const;
127    SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
128  };
129} // end namespace llvm
130
131#endif    // SPARC_ISELLOWERING_H
132