SparcISelLowering.h revision 7d2ad624fa749a6d3edac0d94e9c107989c16304
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef SPARC_ISELLOWERING_H 16#define SPARC_ISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "Sparc.h" 20 21namespace llvm { 22 namespace SPISD { 23 enum { 24 FIRST_NUMBER = ISD::BUILTIN_OP_END, 25 CMPICC, // Compare two GPR operands, set icc. 26 CMPFCC, // Compare two FP operands, set fcc. 27 BRICC, // Branch to dest on icc condition 28 BRFCC, // Branch to dest on fcc condition 29 SELECT_ICC, // Select between two values using the current ICC flags. 30 SELECT_FCC, // Select between two values using the current FCC flags. 31 32 Hi, Lo, // Hi/Lo operations, typically on a global address. 33 34 FTOI, // FP to Int within a FP register. 35 ITOF, // Int to FP within a FP register. 36 37 CALL, // A call instruction. 38 RET_FLAG // Return with a flag operand. 39 }; 40 } 41 42 class SparcTargetLowering : public TargetLowering { 43 int VarArgsFrameOffset; // Frame offset to start of varargs area. 44 public: 45 SparcTargetLowering(TargetMachine &TM); 46 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 47 48 int getVarArgsFrameOffset() const { return VarArgsFrameOffset; } 49 50 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 51 /// in Mask are known to be either zero or one and return them in the 52 /// KnownZero/KnownOne bitsets. 53 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 54 const APInt &Mask, 55 APInt &KnownZero, 56 APInt &KnownOne, 57 const SelectionDAG &DAG, 58 unsigned Depth = 0) const; 59 60 virtual void LowerArguments(Function &F, SelectionDAG &DAG, 61 SmallVectorImpl<SDValue> &ArgValues, 62 DebugLoc dl); 63 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 64 MachineBasicBlock *MBB); 65 66 virtual const char *getTargetNodeName(unsigned Opcode) const; 67 68 ConstraintType getConstraintType(const std::string &Constraint) const; 69 std::pair<unsigned, const TargetRegisterClass*> 70 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; 71 std::vector<unsigned> 72 getRegClassForInlineAsmConstraint(const std::string &Constraint, 73 MVT VT) const; 74 75 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 76 }; 77} // end namespace llvm 78 79#endif // SPARC_ISELLOWERING_H 80