SparcISelLowering.h revision 860b64cb1efba110bf81bcc243a6fbaae4c655a4 
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPARC_ISELLOWERING_H
16#define SPARC_ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "Sparc.h"
20
21namespace llvm {
22  namespace SPISD {
23    enum {
24      FIRST_NUMBER = ISD::BUILTIN_OP_END,
25      CMPICC,      // Compare two GPR operands, set icc.
26      CMPFCC,      // Compare two FP operands, set fcc.
27      BRICC,       // Branch to dest on icc condition
28      BRFCC,       // Branch to dest on fcc condition
29      SELECT_ICC,  // Select between two values using the current ICC flags.
30      SELECT_FCC,  // Select between two values using the current FCC flags.
31
32      Hi, Lo,      // Hi/Lo operations, typically on a global address.
33
34      FTOI,        // FP to Int within a FP register.
35      ITOF,        // Int to FP within a FP register.
36
37      CALL,        // A call instruction.
38      RET_FLAG,    // Return with a flag operand.
39      GLOBAL_BASE_REG, // Global base reg for PIC
40      FLUSH        // FLUSH registers to stack
41    };
42  }
43
44  class SparcTargetLowering : public TargetLowering {
45  public:
46    SparcTargetLowering(TargetMachine &TM);
47    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
48
49    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
50    /// in Mask are known to be either zero or one and return them in the
51    /// KnownZero/KnownOne bitsets.
52    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
53                                                const APInt &Mask,
54                                                APInt &KnownZero,
55                                                APInt &KnownOne,
56                                                const SelectionDAG &DAG,
57                                                unsigned Depth = 0) const;
58
59    virtual MachineBasicBlock *
60      EmitInstrWithCustomInserter(MachineInstr *MI,
61                                  MachineBasicBlock *MBB) const;
62
63    virtual const char *getTargetNodeName(unsigned Opcode) const;
64
65    ConstraintType getConstraintType(const std::string &Constraint) const;
66    std::pair<unsigned, const TargetRegisterClass*>
67    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
68    std::vector<unsigned>
69    getRegClassForInlineAsmConstraint(const std::string &Constraint,
70                                      EVT VT) const;
71
72    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
73
74    /// getFunctionAlignment - Return the Log2 alignment of this function.
75    virtual unsigned getFunctionAlignment(const Function *F) const;
76
77    virtual SDValue
78      LowerFormalArguments(SDValue Chain,
79                           CallingConv::ID CallConv,
80                           bool isVarArg,
81                           const SmallVectorImpl<ISD::InputArg> &Ins,
82                           DebugLoc dl, SelectionDAG &DAG,
83                           SmallVectorImpl<SDValue> &InVals) const;
84
85    virtual SDValue
86      LowerCall(SDValue Chain, SDValue Callee,
87                CallingConv::ID CallConv, bool isVarArg,
88                bool &isTailCall,
89                const SmallVectorImpl<ISD::OutputArg> &Outs,
90                const SmallVectorImpl<SDValue> &OutVals,
91                const SmallVectorImpl<ISD::InputArg> &Ins,
92                DebugLoc dl, SelectionDAG &DAG,
93                SmallVectorImpl<SDValue> &InVals) const;
94
95    virtual SDValue
96      LowerReturn(SDValue Chain,
97                  CallingConv::ID CallConv, bool isVarArg,
98                  const SmallVectorImpl<ISD::OutputArg> &Outs,
99                  const SmallVectorImpl<SDValue> &OutVals,
100                  DebugLoc dl, SelectionDAG &DAG) const;
101
102    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
103    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
104  };
105} // end namespace llvm
106
107#endif    // SPARC_ISELLOWERING_H
108