SparcISelLowering.h revision 942619695f4bd77934c09a1cae0fb39ae59edac3 
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPARC_ISELLOWERING_H
16#define SPARC_ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "Sparc.h"
20
21namespace llvm {
22  namespace SPISD {
23    enum {
24      FIRST_NUMBER = ISD::BUILTIN_OP_END,
25      CMPICC,      // Compare two GPR operands, set icc.
26      CMPFCC,      // Compare two FP operands, set fcc.
27      BRICC,       // Branch to dest on icc condition
28      BRFCC,       // Branch to dest on fcc condition
29      SELECT_ICC,  // Select between two values using the current ICC flags.
30      SELECT_FCC,  // Select between two values using the current FCC flags.
31
32      Hi, Lo,      // Hi/Lo operations, typically on a global address.
33
34      FTOI,        // FP to Int within a FP register.
35      ITOF,        // Int to FP within a FP register.
36
37      CALL,        // A call instruction.
38      RET_FLAG,    // Return with a flag operand.
39      GLOBAL_BASE_REG // Global base reg for PIC
40    };
41  }
42
43  class SparcTargetLowering : public TargetLowering {
44    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
45  public:
46    SparcTargetLowering(TargetMachine &TM);
47    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
48
49    int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
50
51    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
52    /// in Mask are known to be either zero or one and return them in the
53    /// KnownZero/KnownOne bitsets.
54    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
55                                                const APInt &Mask,
56                                                APInt &KnownZero,
57                                                APInt &KnownOne,
58                                                const SelectionDAG &DAG,
59                                                unsigned Depth = 0) const;
60
61    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
62                                                         MachineBasicBlock *MBB,
63                    DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
64
65    virtual const char *getTargetNodeName(unsigned Opcode) const;
66
67    ConstraintType getConstraintType(const std::string &Constraint) const;
68    std::pair<unsigned, const TargetRegisterClass*>
69    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
70    std::vector<unsigned>
71    getRegClassForInlineAsmConstraint(const std::string &Constraint,
72                                      EVT VT) const;
73
74    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
75
76    /// getFunctionAlignment - Return the Log2 alignment of this function.
77    virtual unsigned getFunctionAlignment(const Function *F) const;
78
79    virtual SDValue
80      LowerFormalArguments(SDValue Chain,
81                           CallingConv::ID CallConv,
82                           bool isVarArg,
83                           const SmallVectorImpl<ISD::InputArg> &Ins,
84                           DebugLoc dl, SelectionDAG &DAG,
85                           SmallVectorImpl<SDValue> &InVals);
86
87    virtual SDValue
88      LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy,
89                CallingConv::ID CallConv, bool isVarArg,
90                bool &isTailCall,
91                const SmallVectorImpl<ISD::OutputArg> &Outs,
92                const SmallVectorImpl<ISD::InputArg> &Ins,
93                DebugLoc dl, SelectionDAG &DAG,
94                SmallVectorImpl<SDValue> &InVals);
95
96    virtual SDValue
97      LowerReturn(SDValue Chain,
98                  CallingConv::ID CallConv, bool isVarArg,
99                  const SmallVectorImpl<ISD::OutputArg> &Outs,
100                  DebugLoc dl, SelectionDAG &DAG);
101
102    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
103    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
104  };
105} // end namespace llvm
106
107#endif    // SPARC_ISELLOWERING_H
108