SparcISelLowering.h revision fcd5e86396e121fef7ad11d41cc8bc0a541631b2
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef SPARC_ISELLOWERING_H 16#define SPARC_ISELLOWERING_H 17 18#include "Sparc.h" 19#include "llvm/Target/TargetLowering.h" 20 21namespace llvm { 22 class SparcSubtarget; 23 24 namespace SPISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 CMPICC, // Compare two GPR operands, set icc+xcc. 28 CMPFCC, // Compare two FP operands, set fcc. 29 BRICC, // Branch to dest on icc condition 30 BRXCC, // Branch to dest on xcc condition (64-bit only). 31 BRFCC, // Branch to dest on fcc condition 32 SELECT_ICC, // Select between two values using the current ICC flags. 33 SELECT_XCC, // Select between two values using the current XCC flags. 34 SELECT_FCC, // Select between two values using the current FCC flags. 35 36 Hi, Lo, // Hi/Lo operations, typically on a global address. 37 38 FTOI, // FP to Int within a FP register. 39 ITOF, // Int to FP within a FP register. 40 FTOX, // FP to Int64 within a FP register. 41 XTOF, // Int64 to FP within a FP register. 42 43 CALL, // A call instruction. 44 RET_FLAG, // Return with a flag operand. 45 GLOBAL_BASE_REG, // Global base reg for PIC. 46 FLUSHW, // FLUSH register windows to stack. 47 48 TLS_ADD, // For Thread Local Storage (TLS). 49 TLS_LD, 50 TLS_CALL 51 }; 52 } 53 54 class SparcTargetLowering : public TargetLowering { 55 const SparcSubtarget *Subtarget; 56 public: 57 SparcTargetLowering(TargetMachine &TM); 58 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 59 60 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 61 /// in Mask are known to be either zero or one and return them in the 62 /// KnownZero/KnownOne bitsets. 63 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 64 APInt &KnownZero, 65 APInt &KnownOne, 66 const SelectionDAG &DAG, 67 unsigned Depth = 0) const; 68 69 virtual MachineBasicBlock * 70 EmitInstrWithCustomInserter(MachineInstr *MI, 71 MachineBasicBlock *MBB) const; 72 73 virtual const char *getTargetNodeName(unsigned Opcode) const; 74 75 ConstraintType getConstraintType(const std::string &Constraint) const; 76 std::pair<unsigned, const TargetRegisterClass*> 77 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; 78 79 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 80 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 81 82 virtual SDValue 83 LowerFormalArguments(SDValue Chain, 84 CallingConv::ID CallConv, 85 bool isVarArg, 86 const SmallVectorImpl<ISD::InputArg> &Ins, 87 SDLoc dl, SelectionDAG &DAG, 88 SmallVectorImpl<SDValue> &InVals) const; 89 SDValue LowerFormalArguments_32(SDValue Chain, 90 CallingConv::ID CallConv, 91 bool isVarArg, 92 const SmallVectorImpl<ISD::InputArg> &Ins, 93 SDLoc dl, SelectionDAG &DAG, 94 SmallVectorImpl<SDValue> &InVals) const; 95 SDValue LowerFormalArguments_64(SDValue Chain, 96 CallingConv::ID CallConv, 97 bool isVarArg, 98 const SmallVectorImpl<ISD::InputArg> &Ins, 99 SDLoc dl, SelectionDAG &DAG, 100 SmallVectorImpl<SDValue> &InVals) const; 101 102 virtual SDValue 103 LowerCall(TargetLowering::CallLoweringInfo &CLI, 104 SmallVectorImpl<SDValue> &InVals) const; 105 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 106 SmallVectorImpl<SDValue> &InVals) const; 107 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 108 SmallVectorImpl<SDValue> &InVals) const; 109 110 virtual SDValue 111 LowerReturn(SDValue Chain, 112 CallingConv::ID CallConv, bool isVarArg, 113 const SmallVectorImpl<ISD::OutputArg> &Outs, 114 const SmallVectorImpl<SDValue> &OutVals, 115 SDLoc dl, SelectionDAG &DAG) const; 116 SDValue LowerReturn_32(SDValue Chain, 117 CallingConv::ID CallConv, bool IsVarArg, 118 const SmallVectorImpl<ISD::OutputArg> &Outs, 119 const SmallVectorImpl<SDValue> &OutVals, 120 SDLoc DL, SelectionDAG &DAG) const; 121 SDValue LowerReturn_64(SDValue Chain, 122 CallingConv::ID CallConv, bool IsVarArg, 123 const SmallVectorImpl<ISD::OutputArg> &Outs, 124 const SmallVectorImpl<SDValue> &OutVals, 125 SDLoc DL, SelectionDAG &DAG) const; 126 127 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 128 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 129 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 130 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 131 132 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; 133 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 134 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 135 SelectionDAG &DAG) const; 136 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 137 138 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, 139 SDValue Arg, SDLoc DL, 140 SelectionDAG &DAG) const; 141 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, 142 const char *LibFuncName, 143 unsigned numArgs) const; 144 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, 145 unsigned &SPCC, 146 SDLoc DL, 147 SelectionDAG &DAG) const; 148 149 bool ShouldShrinkFPConstant(EVT VT) const { 150 // Do not shrink FP constpool if VT == MVT::f128. 151 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 152 return VT != MVT::f128; 153 } 154 155 virtual void ReplaceNodeResults(SDNode *N, 156 SmallVectorImpl<SDValue>& Results, 157 SelectionDAG &DAG) const; 158 }; 159} // end namespace llvm 160 161#endif // SPARC_ISELLOWERING_H 162