SparcInstr64Bit.td revision 1cefde83ffcfe869e86ef1976667f47856087dd3 
1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains instruction definitions and patterns needed for 64-bit
11// code generation on SPARC v9.
12//
13// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
14// also be used in 32-bit code running on a SPARC v9 CPU.
15//
16//===----------------------------------------------------------------------===//
17
18let Predicates = [Is64Bit] in {
19// The same integer registers are used for i32 and i64 values.
20// When registers hold i32 values, the high bits are don't care.
21// This give us free trunc and anyext.
22def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
24
25} // Predicates = [Is64Bit]
26
27
28//===----------------------------------------------------------------------===//
29// 64-bit Shift Instructions.
30//===----------------------------------------------------------------------===//
31//
32// The 32-bit shift instructions are still available. The left shift srl
33// instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
34//
35// The srl instructions only shift the low 32 bits and clear the high 32 bits.
36// Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
37
38let Predicates = [Is64Bit] in {
39
40def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
42
43def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
45
46defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
47defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
48defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
49
50} // Predicates = [Is64Bit]
51
52
53//===----------------------------------------------------------------------===//
54// 64-bit Immediates.
55//===----------------------------------------------------------------------===//
56//
57// All 32-bit immediates can be materialized with sethi+or, but 64-bit
58// immediates may require more code. There may be a point where it is
59// preferable to use a constant pool load instead, depending on the
60// microarchitecture.
61
62// Single-instruction patterns.
63
64// The ALU instructions want their simm13 operands as i32 immediates.
65def as_i32imm : SDNodeXForm<imm, [{
66  return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
67}]>;
68def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
69def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
70
71// Double-instruction patterns.
72
73// All unsigned i32 immediates can be handled by sethi+or.
74def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
75def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
76      Requires<[Is64Bit]>;
77
78// All negative i33 immediates can be handled by sethi+xor.
79def nimm33 : PatLeaf<(imm), [{
80  int64_t Imm = N->getSExtValue();
81  return Imm < 0 && isInt<33>(Imm);
82}]>;
83// Bits 10-31 inverted. Same as assembler's %hix.
84def HIX22 : SDNodeXForm<imm, [{
85  uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
86  return CurDAG->getTargetConstant(Val, MVT::i32);
87}]>;
88// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
89def LOX10 : SDNodeXForm<imm, [{
90  return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
91}]>;
92def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
93      Requires<[Is64Bit]>;
94
95// More possible patterns:
96//
97//   (sllx sethi, n)
98//   (sllx simm13, n)
99//
100// 3 instrs:
101//
102//   (xor (sllx sethi), simm13)
103//   (sllx (xor sethi, simm13))
104//
105// 4 instrs:
106//
107//   (or sethi, (sllx sethi))
108//   (xnor sethi, (sllx sethi))
109//
110// 5 instrs:
111//
112//   (or (sllx sethi), (or sethi, simm13))
113//   (xnor (sllx sethi), (or sethi, simm13))
114//   (or (sllx sethi), (sllx sethi))
115//   (xnor (sllx sethi), (sllx sethi))
116//
117// Worst case is 6 instrs:
118//
119//   (or (sllx (or sethi, simmm13)), (or sethi, simm13))
120
121// Bits 42-63, same as assembler's %hh.
122def HH22 : SDNodeXForm<imm, [{
123  uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
124  return CurDAG->getTargetConstant(Val, MVT::i32);
125}]>;
126// Bits 32-41, same as assembler's %hm.
127def HM10 : SDNodeXForm<imm, [{
128  uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
129  return CurDAG->getTargetConstant(Val, MVT::i32);
130}]>;
131def : Pat<(i64 imm:$val),
132          (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),
133                (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
134      Requires<[Is64Bit]>;
135
136
137//===----------------------------------------------------------------------===//
138// 64-bit Integer Arithmetic and Logic.
139//===----------------------------------------------------------------------===//
140
141let Predicates = [Is64Bit] in {
142
143// Register-register instructions.
144
145def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
146def : Pat<(or  i64:$a, i64:$b), (ORrr  $a, $b)>;
147def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
148
149def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>;
150def : Pat<(or  i64:$a, (not i64:$b)), (ORNrr  $a, $b)>;
151def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>;
152
153def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
154def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>;
155
156def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
157
158def : Pat<(tlsadd i64:$a, i64:$b, tglobaltlsaddr:$sym),
159          (TLS_ADDrr $a, $b, $sym)>;
160
161// Register-immediate instructions.
162
163def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
164def : Pat<(or  i64:$a, (i64 simm13:$b)), (ORri  $a, (as_i32imm $b))>;
165def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
166
167def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
168def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
169
170def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
171
172def : Pat<(ctpop i64:$src), (POPCrr $src)>;
173
174// "LEA" form of add
175def LEAX_ADDri : F3_2<2, 0b000000,
176                     (outs I64Regs:$dst), (ins MEMri:$addr),
177                     "add ${addr:arith}, $dst",
178                     [(set iPTR:$dst, ADDRri:$addr)]>;
179
180} // Predicates = [Is64Bit]
181
182
183//===----------------------------------------------------------------------===//
184// 64-bit Integer Multiply and Divide.
185//===----------------------------------------------------------------------===//
186
187let Predicates = [Is64Bit] in {
188
189def MULXrr : F3_1<2, 0b001001,
190                  (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
191                  "mulx $rs1, $rs2, $rd",
192                  [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
193def MULXri : F3_2<2, 0b001001,
194                  (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
195                  "mulx $rs1, $i, $rd",
196                  [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
197
198// Division can trap.
199let hasSideEffects = 1 in {
200def SDIVXrr : F3_1<2, 0b101101,
201                   (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
202                   "sdivx $rs1, $rs2, $rd",
203                   [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
204def SDIVXri : F3_2<2, 0b101101,
205                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
206                   "sdivx $rs1, $i, $rd",
207                   [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>;
208
209def UDIVXrr : F3_1<2, 0b001101,
210                   (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
211                   "udivx $rs1, $rs2, $rd",
212                   [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
213def UDIVXri : F3_2<2, 0b001101,
214                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
215                   "udivx $rs1, $i, $rd",
216                   [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>;
217} // hasSideEffects = 1
218
219} // Predicates = [Is64Bit]
220
221
222//===----------------------------------------------------------------------===//
223// 64-bit Loads and Stores.
224//===----------------------------------------------------------------------===//
225//
226// All the 32-bit loads and stores are available. The extending loads are sign
227// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
228// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
229// Word).
230//
231// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
232
233let Predicates = [Is64Bit] in {
234
235// 64-bit loads.
236def LDXrr  : F3_1<3, 0b001011,
237                  (outs I64Regs:$dst), (ins MEMrr:$addr),
238                  "ldx [$addr], $dst",
239                  [(set i64:$dst, (load ADDRrr:$addr))]>;
240def LDXri  : F3_2<3, 0b001011,
241                  (outs I64Regs:$dst), (ins MEMri:$addr),
242                  "ldx [$addr], $dst",
243                  [(set i64:$dst, (load ADDRri:$addr))]>;
244let mayLoad = 1 in
245  def TLS_LDXrr : F3_1<3, 0b001011,
246                       (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
247                       "ldx [$addr], $dst, $sym",
248                       [(set i64:$dst,
249                           (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
250
251// Extending loads to i64.
252def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
253def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
254def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
255def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
256
257def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
258def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
259def : Pat<(i64 (extloadi8 ADDRrr:$addr)),  (LDUBrr ADDRrr:$addr)>;
260def : Pat<(i64 (extloadi8 ADDRri:$addr)),  (LDUBri ADDRri:$addr)>;
261def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
262def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
263
264def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
265def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
266def : Pat<(i64 (extloadi16 ADDRrr:$addr)),  (LDUHrr ADDRrr:$addr)>;
267def : Pat<(i64 (extloadi16 ADDRri:$addr)),  (LDUHri ADDRri:$addr)>;
268def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
269def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
270
271def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
272def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
273def : Pat<(i64 (extloadi32 ADDRrr:$addr)),  (LDrr ADDRrr:$addr)>;
274def : Pat<(i64 (extloadi32 ADDRri:$addr)),  (LDri ADDRri:$addr)>;
275
276// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
277def LDSWrr : F3_1<3, 0b001011,
278                 (outs I64Regs:$dst), (ins MEMrr:$addr),
279                 "ldsw [$addr], $dst",
280                 [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
281def LDSWri : F3_2<3, 0b001011,
282                 (outs I64Regs:$dst), (ins MEMri:$addr),
283                 "ldsw [$addr], $dst",
284                 [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
285
286// 64-bit stores.
287def STXrr  : F3_1<3, 0b001110,
288                 (outs), (ins MEMrr:$addr, I64Regs:$src),
289                 "stx $src, [$addr]",
290                 [(store i64:$src, ADDRrr:$addr)]>;
291def STXri  : F3_2<3, 0b001110,
292                 (outs), (ins MEMri:$addr, I64Regs:$src),
293                 "stx $src, [$addr]",
294                 [(store i64:$src, ADDRri:$addr)]>;
295
296// Truncating stores from i64 are identical to the i32 stores.
297def : Pat<(truncstorei8  i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
298def : Pat<(truncstorei8  i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
299def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
300def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
301def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr  ADDRrr:$addr, $src)>;
302def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri  ADDRri:$addr, $src)>;
303
304// store 0, addr -> store %g0, addr
305def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>;
306def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
307
308} // Predicates = [Is64Bit]
309
310
311//===----------------------------------------------------------------------===//
312// 64-bit Conditionals.
313//===----------------------------------------------------------------------===//
314//
315// Flag-setting instructions like subcc and addcc set both icc and xcc flags.
316// The icc flags correspond to the 32-bit result, and the xcc are for the
317// full 64-bit result.
318//
319// We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
320// 64-bit compares. See LowerBR_CC.
321
322let Predicates = [Is64Bit] in {
323
324let Uses = [ICC] in
325def BPXCC : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
326                     "b$cond %xcc, $imm22",
327                     [(SPbrxcc bb:$imm22, imm:$cond)]>;
328
329// Conditional moves on %xcc.
330let Uses = [ICC], Constraints = "$f = $rd" in {
331def MOVXCCrr : Pseudo<(outs IntRegs:$rd),
332                      (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
333                      "mov$cond %xcc, $rs2, $rd",
334                      [(set i32:$rd,
335                       (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
336def MOVXCCri : Pseudo<(outs IntRegs:$rd),
337                      (ins i32imm:$i, IntRegs:$f, CCOp:$cond),
338                      "mov$cond %xcc, $i, $rd",
339                      [(set i32:$rd,
340                       (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>;
341def FMOVS_XCC : Pseudo<(outs FPRegs:$rd),
342                      (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
343                      "fmovs$cond %xcc, $rs2, $rd",
344                      [(set f32:$rd,
345                       (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
346def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd),
347                      (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
348                      "fmovd$cond %xcc, $rs2, $rd",
349                      [(set f64:$rd,
350                       (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
351} // Uses, Constraints
352
353//===----------------------------------------------------------------------===//
354// 64-bit Floating Point Conversions.
355//===----------------------------------------------------------------------===//
356
357let Predicates = [Is64Bit] in {
358
359def FXTOS : F3_3u<2, 0b110100, 0b010000100,
360                 (outs FPRegs:$dst), (ins DFPRegs:$src),
361                 "fxtos $src, $dst",
362                 [(set FPRegs:$dst, (SPxtof DFPRegs:$src))]>;
363def FXTOD : F3_3u<2, 0b110100, 0b010001000,
364                 (outs DFPRegs:$dst), (ins DFPRegs:$src),
365                 "fxtod $src, $dst",
366                 [(set DFPRegs:$dst, (SPxtof DFPRegs:$src))]>;
367def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
368                 (outs QFPRegs:$dst), (ins DFPRegs:$src),
369                 "fxtoq $src, $dst",
370                 [(set QFPRegs:$dst, (SPxtof DFPRegs:$src))]>,
371                 Requires<[HasHardQuad]>;
372
373def FSTOX : F3_3u<2, 0b110100, 0b010000001,
374                 (outs DFPRegs:$dst), (ins FPRegs:$src),
375                 "fstox $src, $dst",
376                 [(set DFPRegs:$dst, (SPftox FPRegs:$src))]>;
377def FDTOX : F3_3u<2, 0b110100, 0b010000010,
378                 (outs DFPRegs:$dst), (ins DFPRegs:$src),
379                 "fdtox $src, $dst",
380                 [(set DFPRegs:$dst, (SPftox DFPRegs:$src))]>;
381def FQTOX : F3_3u<2, 0b110100, 0b010000011,
382                 (outs DFPRegs:$dst), (ins QFPRegs:$src),
383                 "fqtox $src, $dst",
384                 [(set DFPRegs:$dst, (SPftox QFPRegs:$src))]>,
385                 Requires<[HasHardQuad]>;
386
387} // Predicates = [Is64Bit]
388
389def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
390          (MOVXCCrr $t, $f, imm:$cond)>;
391def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
392          (MOVXCCri (as_i32imm $t), $f, imm:$cond)>;
393
394def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond),
395          (MOVICCrr $t, $f, imm:$cond)>;
396def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond),
397          (MOVICCri (as_i32imm $t), $f, imm:$cond)>;
398
399def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond),
400          (MOVFCCrr $t, $f, imm:$cond)>;
401def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
402          (MOVFCCri (as_i32imm $t), $f, imm:$cond)>;
403
404} // Predicates = [Is64Bit]
405