SparcInstr64Bit.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains instruction definitions and patterns needed for 64-bit 11// code generation on SPARC v9. 12// 13// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can 14// also be used in 32-bit code running on a SPARC v9 CPU. 15// 16//===----------------------------------------------------------------------===// 17 18let Predicates = [Is64Bit] in { 19// The same integer registers are used for i32 and i64 values. 20// When registers hold i32 values, the high bits are don't care. 21// This give us free trunc and anyext. 22def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>; 23def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>; 24 25} // Predicates = [Is64Bit] 26 27 28//===----------------------------------------------------------------------===// 29// 64-bit Shift Instructions. 30//===----------------------------------------------------------------------===// 31// 32// The 32-bit shift instructions are still available. The left shift srl 33// instructions shift all 64 bits, but it only accepts a 5-bit shift amount. 34// 35// The srl instructions only shift the low 32 bits and clear the high 32 bits. 36// Finally, sra shifts the low 32 bits and sign-extends to 64 bits. 37 38let Predicates = [Is64Bit] in { 39 40def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>; 41def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>; 42 43def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>; 44def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>; 45 46defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>; 47defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>; 48defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>; 49 50} // Predicates = [Is64Bit] 51 52 53//===----------------------------------------------------------------------===// 54// 64-bit Immediates. 55//===----------------------------------------------------------------------===// 56// 57// All 32-bit immediates can be materialized with sethi+or, but 64-bit 58// immediates may require more code. There may be a point where it is 59// preferable to use a constant pool load instead, depending on the 60// microarchitecture. 61 62// Single-instruction patterns. 63 64// The ALU instructions want their simm13 operands as i32 immediates. 65def as_i32imm : SDNodeXForm<imm, [{ 66 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32); 67}]>; 68def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; 69def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; 70 71// Double-instruction patterns. 72 73// All unsigned i32 immediates can be handled by sethi+or. 74def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 75def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>, 76 Requires<[Is64Bit]>; 77 78// All negative i33 immediates can be handled by sethi+xor. 79def nimm33 : PatLeaf<(imm), [{ 80 int64_t Imm = N->getSExtValue(); 81 return Imm < 0 && isInt<33>(Imm); 82}]>; 83// Bits 10-31 inverted. Same as assembler's %hix. 84def HIX22 : SDNodeXForm<imm, [{ 85 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); 86 return CurDAG->getTargetConstant(Val, MVT::i32); 87}]>; 88// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. 89def LOX10 : SDNodeXForm<imm, [{ 90 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32); 91}]>; 92def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, 93 Requires<[Is64Bit]>; 94 95// More possible patterns: 96// 97// (sllx sethi, n) 98// (sllx simm13, n) 99// 100// 3 instrs: 101// 102// (xor (sllx sethi), simm13) 103// (sllx (xor sethi, simm13)) 104// 105// 4 instrs: 106// 107// (or sethi, (sllx sethi)) 108// (xnor sethi, (sllx sethi)) 109// 110// 5 instrs: 111// 112// (or (sllx sethi), (or sethi, simm13)) 113// (xnor (sllx sethi), (or sethi, simm13)) 114// (or (sllx sethi), (sllx sethi)) 115// (xnor (sllx sethi), (sllx sethi)) 116// 117// Worst case is 6 instrs: 118// 119// (or (sllx (or sethi, simmm13)), (or sethi, simm13)) 120 121// Bits 42-63, same as assembler's %hh. 122def HH22 : SDNodeXForm<imm, [{ 123 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); 124 return CurDAG->getTargetConstant(Val, MVT::i32); 125}]>; 126// Bits 32-41, same as assembler's %hm. 127def HM10 : SDNodeXForm<imm, [{ 128 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); 129 return CurDAG->getTargetConstant(Val, MVT::i32); 130}]>; 131def : Pat<(i64 imm:$val), 132 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), 133 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>, 134 Requires<[Is64Bit]>; 135 136 137//===----------------------------------------------------------------------===// 138// 64-bit Integer Arithmetic and Logic. 139//===----------------------------------------------------------------------===// 140 141let Predicates = [Is64Bit] in { 142 143// Register-register instructions. 144let isCodeGenOnly = 1 in { 145defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>; 146defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>; 147defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>; 148 149def ANDXNrr : F3_1<2, 0b000101, 150 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 151 "andn $b, $c, $dst", 152 [(set i64:$dst, (and i64:$b, (not i64:$c)))]>; 153def ORXNrr : F3_1<2, 0b000110, 154 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 155 "orn $b, $c, $dst", 156 [(set i64:$dst, (or i64:$b, (not i64:$c)))]>; 157def XNORXrr : F3_1<2, 0b000111, 158 (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c), 159 "xnor $b, $c, $dst", 160 [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>; 161 162defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>; 163defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>; 164 165def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd), 166 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym), 167 "add $rs1, $rs2, $rd, $sym", 168 [(set i64:$rd, 169 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>; 170 171// "LEA" form of add 172def LEAX_ADDri : F3_2<2, 0b000000, 173 (outs I64Regs:$dst), (ins MEMri:$addr), 174 "add ${addr:arith}, $dst", 175 [(set iPTR:$dst, ADDRri:$addr)]>; 176} 177 178def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; 179def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; 180def : Pat<(ctpop i64:$src), (POPCrr $src)>; 181 182} // Predicates = [Is64Bit] 183 184 185//===----------------------------------------------------------------------===// 186// 64-bit Integer Multiply and Divide. 187//===----------------------------------------------------------------------===// 188 189let Predicates = [Is64Bit] in { 190 191def MULXrr : F3_1<2, 0b001001, 192 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 193 "mulx $rs1, $rs2, $rd", 194 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 195def MULXri : F3_2<2, 0b001001, 196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 197 "mulx $rs1, $simm13, $rd", 198 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 199 200// Division can trap. 201let hasSideEffects = 1 in { 202def SDIVXrr : F3_1<2, 0b101101, 203 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 204 "sdivx $rs1, $rs2, $rd", 205 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; 206def SDIVXri : F3_2<2, 0b101101, 207 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 208 "sdivx $rs1, $simm13, $rd", 209 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; 210 211def UDIVXrr : F3_1<2, 0b001101, 212 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 213 "udivx $rs1, $rs2, $rd", 214 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; 215def UDIVXri : F3_2<2, 0b001101, 216 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 217 "udivx $rs1, $simm13, $rd", 218 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; 219} // hasSideEffects = 1 220 221} // Predicates = [Is64Bit] 222 223 224//===----------------------------------------------------------------------===// 225// 64-bit Loads and Stores. 226//===----------------------------------------------------------------------===// 227// 228// All the 32-bit loads and stores are available. The extending loads are sign 229// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits 230// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned 231// Word). 232// 233// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads. 234 235let Predicates = [Is64Bit] in { 236 237// 64-bit loads. 238let DecoderMethod = "DecodeLoadInt" in 239 defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>; 240 241let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in 242 def TLS_LDXrr : F3_1<3, 0b001011, 243 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 244 "ldx [$addr], $dst, $sym", 245 [(set i64:$dst, 246 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 247 248// Extending loads to i64. 249def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 250def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 251def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 252def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 253 254def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 255def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 256def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 257def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 258def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>; 259def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>; 260 261def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 262def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 263def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 264def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 265def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>; 266def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>; 267 268def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 269def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 270def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 271def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 272 273// Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 274let DecoderMethod = "DecodeLoadInt" in 275 defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>; 276 277// 64-bit stores. 278let DecoderMethod = "DecodeStoreInt" in 279 defm STX : Store<"stx", 0b001110, store, I64Regs, i64>; 280 281// Truncating stores from i64 are identical to the i32 stores. 282def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 283def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>; 284def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>; 285def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>; 286def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>; 287def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>; 288 289// store 0, addr -> store %g0, addr 290def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>; 291def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>; 292 293} // Predicates = [Is64Bit] 294 295 296//===----------------------------------------------------------------------===// 297// 64-bit Conditionals. 298//===----------------------------------------------------------------------===// 299 300// 301// Flag-setting instructions like subcc and addcc set both icc and xcc flags. 302// The icc flags correspond to the 32-bit result, and the xcc are for the 303// full 64-bit result. 304// 305// We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for 306// 64-bit compares. See LowerBR_CC. 307 308let Predicates = [Is64Bit] in { 309 310let Uses = [ICC], cc = 0b10 in 311 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>; 312 313// Conditional moves on %xcc. 314let Uses = [ICC], Constraints = "$f = $rd" in { 315let intcc = 1, cc = 0b10 in { 316def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd), 317 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 318 "mov$cond %xcc, $rs2, $rd", 319 [(set i32:$rd, 320 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; 321def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd), 322 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 323 "mov$cond %xcc, $simm11, $rd", 324 [(set i32:$rd, 325 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>; 326} // cc 327 328let intcc = 1, opf_cc = 0b10 in { 329def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 330 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 331 "fmovs$cond %xcc, $rs2, $rd", 332 [(set f32:$rd, 333 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; 334def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 335 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 336 "fmovd$cond %xcc, $rs2, $rd", 337 [(set f64:$rd, 338 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 339def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 340 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 341 "fmovq$cond %xcc, $rs2, $rd", 342 [(set f128:$rd, 343 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>; 344} // opf_cc 345} // Uses, Constraints 346 347// Branch On integer register with Prediction (BPr). 348let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in 349multiclass BranchOnReg<bits<3> cond, string OpcStr> { 350 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 351 !strconcat(OpcStr, " $rs1, $imm16"), []>; 352 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 353 !strconcat(OpcStr, ",a $rs1, $imm16"), []>; 354 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 355 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>; 356 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 357 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>; 358} 359 360multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> { 361 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"), 362 (NAPT I64Regs:$rs1, bprtarget16:$imm16)>; 363 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"), 364 (APT I64Regs:$rs1, bprtarget16:$imm16)>; 365} 366 367defm BPZ : BranchOnReg<0b001, "brz">; 368defm BPLEZ : BranchOnReg<0b010, "brlez">; 369defm BPLZ : BranchOnReg<0b011, "brlz">; 370defm BPNZ : BranchOnReg<0b101, "brnz">; 371defm BPGZ : BranchOnReg<0b110, "brgz">; 372defm BPGEZ : BranchOnReg<0b111, "brgez">; 373 374defm : bpr_alias<"brz", BPZnapt, BPZapt >; 375defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>; 376defm : bpr_alias<"brlz", BPLZnapt, BPLZapt >; 377defm : bpr_alias<"brnz", BPNZnapt, BPNZapt >; 378defm : bpr_alias<"brgz", BPGZnapt, BPGZapt >; 379defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>; 380 381// Move integer register on register condition (MOVr). 382multiclass MOVR< bits<3> rcond, string OpcStr> { 383 def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd), 384 (ins I64Regs:$rs1, IntRegs:$rs2), 385 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 386 387 def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd), 388 (ins I64Regs:$rs1, i64imm:$simm10), 389 !strconcat(OpcStr, " $rs1, $simm10, $rd"), []>; 390} 391 392defm MOVRRZ : MOVR<0b001, "movrz">; 393defm MOVRLEZ : MOVR<0b010, "movrlez">; 394defm MOVRLZ : MOVR<0b011, "movrlz">; 395defm MOVRNZ : MOVR<0b101, "movrnz">; 396defm MOVRGZ : MOVR<0b110, "movrgz">; 397defm MOVRGEZ : MOVR<0b111, "movrgez">; 398 399// Move FP register on integer register condition (FMOVr). 400multiclass FMOVR<bits<3> rcond, string OpcStr> { 401 402 def S : F4_4r<0b110101, 0b00101, rcond, 403 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 404 !strconcat(!strconcat("fmovrs", OpcStr)," $rs1, $rs2, $rd"), 405 []>; 406 def D : F4_4r<0b110101, 0b00110, rcond, 407 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 408 !strconcat(!strconcat("fmovrd", OpcStr)," $rs1, $rs2, $rd"), 409 []>; 410 def Q : F4_4r<0b110101, 0b00111, rcond, 411 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2), 412 !strconcat(!strconcat("fmovrq", OpcStr)," $rs1, $rs2, $rd"), 413 []>, Requires<[HasHardQuad]>; 414} 415 416let Predicates = [HasV9] in { 417 defm FMOVRZ : FMOVR<0b001, "z">; 418 defm FMOVRLEZ : FMOVR<0b010, "lez">; 419 defm FMOVRLZ : FMOVR<0b011, "lz">; 420 defm FMOVRNZ : FMOVR<0b101, "nz">; 421 defm FMOVRGZ : FMOVR<0b110, "gz">; 422 defm FMOVRGEZ : FMOVR<0b111, "gez">; 423} 424 425//===----------------------------------------------------------------------===// 426// 64-bit Floating Point Conversions. 427//===----------------------------------------------------------------------===// 428 429let Predicates = [Is64Bit] in { 430 431def FXTOS : F3_3u<2, 0b110100, 0b010000100, 432 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 433 "fxtos $rs2, $rd", 434 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 435def FXTOD : F3_3u<2, 0b110100, 0b010001000, 436 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 437 "fxtod $rs2, $rd", 438 [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 439def FXTOQ : F3_3u<2, 0b110100, 0b010001100, 440 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 441 "fxtoq $rs2, $rd", 442 [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>, 443 Requires<[HasHardQuad]>; 444 445def FSTOX : F3_3u<2, 0b110100, 0b010000001, 446 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 447 "fstox $rs2, $rd", 448 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>; 449def FDTOX : F3_3u<2, 0b110100, 0b010000010, 450 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 451 "fdtox $rs2, $rd", 452 [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>; 453def FQTOX : F3_3u<2, 0b110100, 0b010000011, 454 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 455 "fqtox $rs2, $rd", 456 [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>, 457 Requires<[HasHardQuad]>; 458 459} // Predicates = [Is64Bit] 460 461def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), 462 (MOVXCCrr $t, $f, imm:$cond)>; 463def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond), 464 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>; 465 466def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond), 467 (MOVICCrr $t, $f, imm:$cond)>; 468def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond), 469 (MOVICCri (as_i32imm $t), $f, imm:$cond)>; 470 471def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond), 472 (MOVFCCrr $t, $f, imm:$cond)>; 473def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond), 474 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>; 475 476} // Predicates = [Is64Bit] 477 478 479// 64 bit SETHI 480let Predicates = [Is64Bit], isCodeGenOnly = 1 in { 481def SETHIXi : F2_1<0b100, 482 (outs IntRegs:$rd), (ins i64imm:$imm22), 483 "sethi $imm22, $rd", 484 [(set i64:$rd, SETHIimm:$imm22)]>; 485} 486 487// ATOMICS. 488let Predicates = [Is64Bit], Constraints = "$swap = $rd" in { 489 def CASXrr: F3_1_asi<3, 0b111110, 0b10000000, 490 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, 491 I64Regs:$swap), 492 "casx [$rs1], $rs2, $rd", 493 [(set i64:$rd, 494 (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>; 495 496} // Predicates = [Is64Bit], Constraints = ... 497 498let Predicates = [Is64Bit] in { 499 500def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>; 501 502// atomic_load_64 addr -> load addr 503def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>; 504def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>; 505 506// atomic_store_64 val, addr -> store val, addr 507def : Pat<(atomic_store ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>; 508def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>; 509 510} // Predicates = [Is64Bit] 511 512let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1, 513 Defs = [ICC] in 514multiclass AtomicRMW<SDPatternOperator op32, SDPatternOperator op64> { 515 516 def _32 : Pseudo<(outs IntRegs:$rd), 517 (ins ptr_rc:$addr, IntRegs:$rs2), "", 518 [(set i32:$rd, (op32 iPTR:$addr, i32:$rs2))]>; 519 520 let Predicates = [Is64Bit] in 521 def _64 : Pseudo<(outs I64Regs:$rd), 522 (ins ptr_rc:$addr, I64Regs:$rs2), "", 523 [(set i64:$rd, (op64 iPTR:$addr, i64:$rs2))]>; 524} 525 526defm ATOMIC_LOAD_ADD : AtomicRMW<atomic_load_add_32, atomic_load_add_64>; 527defm ATOMIC_LOAD_SUB : AtomicRMW<atomic_load_sub_32, atomic_load_sub_64>; 528defm ATOMIC_LOAD_AND : AtomicRMW<atomic_load_and_32, atomic_load_and_64>; 529defm ATOMIC_LOAD_OR : AtomicRMW<atomic_load_or_32, atomic_load_or_64>; 530defm ATOMIC_LOAD_XOR : AtomicRMW<atomic_load_xor_32, atomic_load_xor_64>; 531defm ATOMIC_LOAD_NAND : AtomicRMW<atomic_load_nand_32, atomic_load_nand_64>; 532defm ATOMIC_LOAD_MIN : AtomicRMW<atomic_load_min_32, atomic_load_min_64>; 533defm ATOMIC_LOAD_MAX : AtomicRMW<atomic_load_max_32, atomic_load_max_64>; 534defm ATOMIC_LOAD_UMIN : AtomicRMW<atomic_load_umin_32, atomic_load_umin_64>; 535defm ATOMIC_LOAD_UMAX : AtomicRMW<atomic_load_umax_32, atomic_load_umax_64>; 536 537// There is no 64-bit variant of SWAP, so use a pseudo. 538let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1, 539 Defs = [ICC], Predicates = [Is64Bit] in 540def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd), 541 (ins ptr_rc:$addr, I64Regs:$rs2), "", 542 [(set i64:$rd, 543 (atomic_swap_64 iPTR:$addr, i64:$rs2))]>; 544 545let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in 546 defm TXCC : TRAP<"%xcc">; 547 548// Global addresses, constant pool entries 549let Predicates = [Is64Bit] in { 550 551def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 552def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>; 553def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 554def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>; 555 556// GlobalTLS addresses 557def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 558def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>; 559def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 560 (ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 561def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 562 (XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 563 564// Blockaddress 565def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 566def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>; 567 568// Add reg, lo. This is used when taking the addr of a global/constpool entry. 569def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>; 570def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>; 571def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 572 (ADDXri $r, tblockaddress:$in)>; 573} 574