SparcInstr64Bit.td revision c3ff3f42ee9a9fb755b0eb0718a31d701b93b3e0 
1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains instruction definitions and patterns needed for 64-bit
11// code generation on SPARC v9.
12//
13// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
14// also be used in 32-bit code running on a SPARC v9 CPU.
15//
16//===----------------------------------------------------------------------===//
17
18let Predicates = [Is64Bit] in {
19// The same integer registers are used for i32 and i64 values.
20// When registers hold i32 values, the high bits are don't care.
21// This give us free trunc and anyext.
22def : Pat<(i64 (anyext i32:$val)), (COPY $val)>;
23def : Pat<(i32 (trunc i64:$val)), (COPY $val)>;
24
25} // Predicates = [Is64Bit]
26
27
28//===----------------------------------------------------------------------===//
29// 64-bit Shift Instructions.
30//===----------------------------------------------------------------------===//
31//
32// The 32-bit shift instructions are still available. The left shift srl
33// instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
34//
35// The srl instructions only shift the low 32 bits and clear the high 32 bits.
36// Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
37
38let Predicates = [Is64Bit] in {
39
40def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
42
43defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
44defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
45defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
46
47} // Predicates = [Is64Bit]
48