SparcInstrFormats.td revision 0d8fcd3218ed93e338a2e7b845f358f1c6f74d58 
1//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Format #2 instruction classes in the SparcV8
12//===----------------------------------------------------------------------===//
13
14class F2 : InstV8 {                   // Format 2 instructions
15  bits<3>  op2;
16  bits<22> imm22;
17  let op          = 0;    // op = 0
18  let Inst{24-22} = op2;
19  let Inst{21-0}  = imm22;
20}
21
22// Specific F2 classes: SparcV8 manual, page 44
23//
24class F2_1<bits<3> op2Val, dag ops, string asmstr> : F2 {
25  bits<5>  rd;
26
27  dag OperandList = ops;
28  let AsmString   = asmstr;
29
30  let op2         = op2Val;
31
32  let Inst{29-25} = rd;
33}
34
35class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr> : F2 {
36  bits<4>   cond;
37  bit       annul = 0;     // currently unused
38
39  dag OperandList = ops;
40  let AsmString   = asmstr;
41
42  let cond        = condVal;
43  let op2         = op2Val;
44
45  let Inst{29}    = annul;
46  let Inst{28-25} = cond;
47}
48
49//===----------------------------------------------------------------------===//
50// Format #3 instruction classes in the SparcV8
51//===----------------------------------------------------------------------===//
52
53class F3 : InstV8 {
54  bits<5> rd;
55  bits<6> op3;
56  bits<5> rs1;
57  let op{1} = 1;   // Op = 2 or 3
58  let Inst{29-25} = rd;
59  let Inst{24-19} = op3;
60  let Inst{18-14} = rs1;
61}
62
63// Specific F3 classes: SparcV8 manual, page 44
64//
65class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
66  bits<8> asi = 0; // asi not currently used in SparcV8
67  bits<5> rs2;
68
69  dag OperandList = ops;
70  let AsmString   = asmstr;
71
72  let op         = opVal;
73  let op3        = op3val;
74
75  let Inst{13}   = 0;     // i field = 0
76  let Inst{12-5} = asi;   // address space identifier
77  let Inst{4-0}  = rs2;
78}
79
80class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
81  bits<13> simm13;
82
83  dag OperandList = ops;
84  let AsmString   = asmstr;
85  
86  let op         = opVal;
87  let op3        = op3val;
88
89  let Inst{13}   = 1;     // i field = 1
90  let Inst{12-0} = simm13;
91}
92
93// floating-point
94class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
95           string asmstr> : F3 {
96  bits<5> rs2;
97
98  dag OperandList = ops;
99  let AsmString   = asmstr;
100
101  let op         = opVal;
102  let op3        = op3val;
103
104  let Inst{13-5} = opfval;   // fp opcode
105  let Inst{4-0}  = rs2;
106}
107