SparcInstrFormats.td revision 4d55aca87aeac108980005912d8ea8733d6226e1 
1//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Format #2 instruction classes in the SparcV8
12//===----------------------------------------------------------------------===//
13
14class F2 : InstV8 {                   // Format 2 instructions
15  bits<3>  op2;
16  bits<22> imm22;
17  let op          = 0;    // op = 0
18  let Inst{24-22} = op2;
19  let Inst{21-0}  = imm22;
20}
21
22// Specific F2 classes: SparcV8 manual, page 44
23//
24class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> : F2 {
25  bits<5>  rd;
26
27  dag OperandList = ops;
28  let AsmString   = asmstr;
29  let Pattern = pattern;
30
31  let op2         = op2Val;
32
33  let Inst{29-25} = rd;
34}
35
36class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr, 
37           list<dag> pattern> : F2 {
38  bits<4>   cond;
39  bit       annul = 0;     // currently unused
40
41  dag OperandList = ops;
42  let AsmString   = asmstr;
43  let Pattern = pattern;
44
45  let cond        = condVal;
46  let op2         = op2Val;
47
48  let Inst{29}    = annul;
49  let Inst{28-25} = cond;
50}
51
52//===----------------------------------------------------------------------===//
53// Format #3 instruction classes in the SparcV8
54//===----------------------------------------------------------------------===//
55
56class F3 : InstV8 {
57  bits<5> rd;
58  bits<6> op3;
59  bits<5> rs1;
60  let op{1} = 1;   // Op = 2 or 3
61  let Inst{29-25} = rd;
62  let Inst{24-19} = op3;
63  let Inst{18-14} = rs1;
64}
65
66// Specific F3 classes: SparcV8 manual, page 44
67//
68class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
69           string asmstr, list<dag> pattern> : F3 {
70  bits<8> asi = 0; // asi not currently used in SparcV8
71  bits<5> rs2;
72
73  dag OperandList = ops;
74  let AsmString   = asmstr;
75  let Pattern = pattern;
76
77  let op         = opVal;
78  let op3        = op3val;
79
80  let Inst{13}   = 0;     // i field = 0
81  let Inst{12-5} = asi;   // address space identifier
82  let Inst{4-0}  = rs2;
83}
84
85class F3_2<bits<2> opVal, bits<6> op3val, dag ops, 
86           string asmstr, list<dag> pattern> : F3 {
87  bits<13> simm13;
88
89  dag OperandList = ops;
90  let AsmString   = asmstr;
91  let Pattern = pattern;
92
93  let op         = opVal;
94  let op3        = op3val;
95
96  let Inst{13}   = 1;     // i field = 1
97  let Inst{12-0} = simm13;
98}
99
100// floating-point
101class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
102           string asmstr, list<dag> pattern> : F3 {
103  bits<5> rs2;
104
105  dag OperandList = ops;
106  let AsmString   = asmstr;
107  let Pattern = pattern;
108
109  let op         = opVal;
110  let op3        = op3val;
111
112  let Inst{13-5} = opfval;   // fp opcode
113  let Inst{4-0}  = rs2;
114}
115