SparcInstrFormats.td revision 57dd3bc46049c528858cdd02f76149d9525199fa 
1//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Format #2 instruction classes in the SparcV8
12//===----------------------------------------------------------------------===//
13
14class F2 : InstV8 {                   // Format 2 instructions
15  bits<3>  op2;
16  bits<22> imm22;
17  let op          = 0;    // op = 0
18  let Inst{24-22} = op2;
19  let Inst{21-0}  = imm22;
20}
21
22// Specific F2 classes: SparcV8 manual, page 44
23//
24class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> : F2 {
25  bits<5>  rd;
26
27  dag OperandList = ops;
28  let AsmString   = asmstr;
29  let Pattern = pattern;
30
31  let op2         = op2Val;
32
33  let Inst{29-25} = rd;
34}
35
36class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr> : F2 {
37  bits<4>   cond;
38  bit       annul = 0;     // currently unused
39
40  dag OperandList = ops;
41  let AsmString   = asmstr;
42
43  let cond        = condVal;
44  let op2         = op2Val;
45
46  let Inst{29}    = annul;
47  let Inst{28-25} = cond;
48}
49
50//===----------------------------------------------------------------------===//
51// Format #3 instruction classes in the SparcV8
52//===----------------------------------------------------------------------===//
53
54class F3 : InstV8 {
55  bits<5> rd;
56  bits<6> op3;
57  bits<5> rs1;
58  let op{1} = 1;   // Op = 2 or 3
59  let Inst{29-25} = rd;
60  let Inst{24-19} = op3;
61  let Inst{18-14} = rs1;
62}
63
64// Specific F3 classes: SparcV8 manual, page 44
65//
66class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
67           string asmstr, list<dag> pattern> : F3 {
68  bits<8> asi = 0; // asi not currently used in SparcV8
69  bits<5> rs2;
70
71  dag OperandList = ops;
72  let AsmString   = asmstr;
73  let Pattern = pattern;
74
75  let op         = opVal;
76  let op3        = op3val;
77
78  let Inst{13}   = 0;     // i field = 0
79  let Inst{12-5} = asi;   // address space identifier
80  let Inst{4-0}  = rs2;
81}
82
83class F3_2<bits<2> opVal, bits<6> op3val, dag ops, 
84           string asmstr, list<dag> pattern> : F3 {
85  bits<13> simm13;
86
87  dag OperandList = ops;
88  let AsmString   = asmstr;
89  let Pattern = pattern;
90
91  let op         = opVal;
92  let op3        = op3val;
93
94  let Inst{13}   = 1;     // i field = 1
95  let Inst{12-0} = simm13;
96}
97
98// floating-point
99class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
100           string asmstr> : F3 {
101  bits<5> rs2;
102
103  dag OperandList = ops;
104  let AsmString   = asmstr;
105
106  let op         = opVal;
107  let op3        = op3val;
108
109  let Inst{13-5} = opfval;   // fp opcode
110  let Inst{4-0}  = rs2;
111}
112