SparcInstrFormats.td revision aca36b932958a7e4a27786dd76e37259fbaa67e0 
1//===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10class InstSP<dag ops, string asmstr, list<dag> pattern> : Instruction {
11  field bits<32> Inst;
12
13  let Namespace = "SP";
14
15  bits<2> op;
16  let Inst{31-30} = op;               // Top two bits are the 'op' field
17  
18  dag OperandList = ops;
19  let AsmString   = asmstr;
20  let Pattern = pattern;
21}
22
23//===----------------------------------------------------------------------===//
24// Format #2 instruction classes in the Sparc
25//===----------------------------------------------------------------------===//
26
27// Format 2 instructions
28class F2<dag ops, string asmstr, list<dag> pattern>
29   : InstSP<ops, asmstr, pattern> {
30  bits<3>  op2;
31  bits<22> imm22;
32  let op          = 0;    // op = 0
33  let Inst{24-22} = op2;
34  let Inst{21-0}  = imm22;
35}
36
37// Specific F2 classes: SparcV8 manual, page 44
38//
39class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
40   : F2<ops, asmstr, pattern> {
41  bits<5>  rd;
42
43  let op2         = op2Val;
44
45  let Inst{29-25} = rd;
46}
47
48class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr, 
49           list<dag> pattern> : F2<ops, asmstr, pattern> {
50  bits<4>   cond;
51  bit       annul = 0;     // currently unused
52
53  let cond        = condVal;
54  let op2         = op2Val;
55
56  let Inst{29}    = annul;
57  let Inst{28-25} = cond;
58}
59
60//===----------------------------------------------------------------------===//
61// Format #3 instruction classes in the Sparc
62//===----------------------------------------------------------------------===//
63
64class F3<dag ops, string asmstr, list<dag> pattern>
65    : InstSP<ops, asmstr, pattern> {
66  bits<5> rd;
67  bits<6> op3;
68  bits<5> rs1;
69  let op{1} = 1;   // Op = 2 or 3
70  let Inst{29-25} = rd;
71  let Inst{24-19} = op3;
72  let Inst{18-14} = rs1;
73}
74
75// Specific F3 classes: SparcV8 manual, page 44
76//
77class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
78           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
79  bits<8> asi = 0; // asi not currently used
80  bits<5> rs2;
81
82  let op         = opVal;
83  let op3        = op3val;
84
85  let Inst{13}   = 0;     // i field = 0
86  let Inst{12-5} = asi;   // address space identifier
87  let Inst{4-0}  = rs2;
88}
89
90class F3_2<bits<2> opVal, bits<6> op3val, dag ops, 
91           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
92  bits<13> simm13;
93
94  let op         = opVal;
95  let op3        = op3val;
96
97  let Inst{13}   = 1;     // i field = 1
98  let Inst{12-0} = simm13;
99}
100
101// floating-point
102class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
103           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
104  bits<5> rs2;
105
106  let op         = opVal;
107  let op3        = op3val;
108
109  let Inst{13-5} = opfval;   // fp opcode
110  let Inst{4-0}  = rs2;
111}
112
113
114