SparcInstrInfo.cpp revision 1c9524b6249ab01c71856e69c4f7071236cf54ed
1//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Sparc implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcInstrInfo.h" 15#include "Sparc.h" 16#include "SparcMachineFunctionInfo.h" 17#include "SparcSubtarget.h" 18#include "llvm/ADT/STLExtras.h" 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineMemOperand.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/TargetRegistry.h" 26 27#define GET_INSTRINFO_CTOR 28#include "SparcGenInstrInfo.inc" 29 30using namespace llvm; 31 32SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 33 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 34 RI(ST), Subtarget(ST) { 35} 36 37/// isLoadFromStackSlot - If the specified machine instruction is a direct 38/// load from a stack slot, return the virtual or physical register number of 39/// the destination along with the FrameIndex of the loaded stack slot. If 40/// not, return 0. This predicate must return 0 if the instruction has 41/// any side effects other than loading from the stack slot. 42unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 43 int &FrameIndex) const { 44 if (MI->getOpcode() == SP::LDri || 45 MI->getOpcode() == SP::LDXri || 46 MI->getOpcode() == SP::LDFri || 47 MI->getOpcode() == SP::LDDFri || 48 MI->getOpcode() == SP::LDQFri) { 49 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 50 MI->getOperand(2).getImm() == 0) { 51 FrameIndex = MI->getOperand(1).getIndex(); 52 return MI->getOperand(0).getReg(); 53 } 54 } 55 return 0; 56} 57 58/// isStoreToStackSlot - If the specified machine instruction is a direct 59/// store to a stack slot, return the virtual or physical register number of 60/// the source reg along with the FrameIndex of the loaded stack slot. If 61/// not, return 0. This predicate must return 0 if the instruction has 62/// any side effects other than storing to the stack slot. 63unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 64 int &FrameIndex) const { 65 if (MI->getOpcode() == SP::STri || 66 MI->getOpcode() == SP::STXri || 67 MI->getOpcode() == SP::STFri || 68 MI->getOpcode() == SP::STDFri || 69 MI->getOpcode() == SP::STQFri) { 70 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 71 MI->getOperand(1).getImm() == 0) { 72 FrameIndex = MI->getOperand(0).getIndex(); 73 return MI->getOperand(2).getReg(); 74 } 75 } 76 return 0; 77} 78 79static bool IsIntegerCC(unsigned CC) 80{ 81 return (CC <= SPCC::ICC_VC); 82} 83 84 85static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 86{ 87 switch(CC) { 88 case SPCC::ICC_NE: return SPCC::ICC_E; 89 case SPCC::ICC_E: return SPCC::ICC_NE; 90 case SPCC::ICC_G: return SPCC::ICC_LE; 91 case SPCC::ICC_LE: return SPCC::ICC_G; 92 case SPCC::ICC_GE: return SPCC::ICC_L; 93 case SPCC::ICC_L: return SPCC::ICC_GE; 94 case SPCC::ICC_GU: return SPCC::ICC_LEU; 95 case SPCC::ICC_LEU: return SPCC::ICC_GU; 96 case SPCC::ICC_CC: return SPCC::ICC_CS; 97 case SPCC::ICC_CS: return SPCC::ICC_CC; 98 case SPCC::ICC_POS: return SPCC::ICC_NEG; 99 case SPCC::ICC_NEG: return SPCC::ICC_POS; 100 case SPCC::ICC_VC: return SPCC::ICC_VS; 101 case SPCC::ICC_VS: return SPCC::ICC_VC; 102 103 case SPCC::FCC_U: return SPCC::FCC_O; 104 case SPCC::FCC_O: return SPCC::FCC_U; 105 case SPCC::FCC_G: return SPCC::FCC_ULE; 106 case SPCC::FCC_LE: return SPCC::FCC_UG; 107 case SPCC::FCC_UG: return SPCC::FCC_LE; 108 case SPCC::FCC_ULE: return SPCC::FCC_G; 109 case SPCC::FCC_L: return SPCC::FCC_UGE; 110 case SPCC::FCC_GE: return SPCC::FCC_UL; 111 case SPCC::FCC_UL: return SPCC::FCC_GE; 112 case SPCC::FCC_UGE: return SPCC::FCC_L; 113 case SPCC::FCC_LG: return SPCC::FCC_UE; 114 case SPCC::FCC_UE: return SPCC::FCC_LG; 115 case SPCC::FCC_NE: return SPCC::FCC_E; 116 case SPCC::FCC_E: return SPCC::FCC_NE; 117 } 118 llvm_unreachable("Invalid cond code"); 119} 120 121bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 122 MachineBasicBlock *&TBB, 123 MachineBasicBlock *&FBB, 124 SmallVectorImpl<MachineOperand> &Cond, 125 bool AllowModify) const 126{ 127 128 MachineBasicBlock::iterator I = MBB.end(); 129 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 130 while (I != MBB.begin()) { 131 --I; 132 133 if (I->isDebugValue()) 134 continue; 135 136 // When we see a non-terminator, we are done. 137 if (!isUnpredicatedTerminator(I)) 138 break; 139 140 // Terminator is not a branch. 141 if (!I->isBranch()) 142 return true; 143 144 // Handle Unconditional branches. 145 if (I->getOpcode() == SP::BA) { 146 UnCondBrIter = I; 147 148 if (!AllowModify) { 149 TBB = I->getOperand(0).getMBB(); 150 continue; 151 } 152 153 while (llvm::next(I) != MBB.end()) 154 llvm::next(I)->eraseFromParent(); 155 156 Cond.clear(); 157 FBB = 0; 158 159 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 160 TBB = 0; 161 I->eraseFromParent(); 162 I = MBB.end(); 163 UnCondBrIter = MBB.end(); 164 continue; 165 } 166 167 TBB = I->getOperand(0).getMBB(); 168 continue; 169 } 170 171 unsigned Opcode = I->getOpcode(); 172 if (Opcode != SP::BCOND && Opcode != SP::FBCOND) 173 return true; // Unknown Opcode. 174 175 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); 176 177 if (Cond.empty()) { 178 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 179 if (AllowModify && UnCondBrIter != MBB.end() && 180 MBB.isLayoutSuccessor(TargetBB)) { 181 182 // Transform the code 183 // 184 // brCC L1 185 // ba L2 186 // L1: 187 // .. 188 // L2: 189 // 190 // into 191 // 192 // brnCC L2 193 // L1: 194 // ... 195 // L2: 196 // 197 BranchCode = GetOppositeBranchCondition(BranchCode); 198 MachineBasicBlock::iterator OldInst = I; 199 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) 200 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); 201 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) 202 .addMBB(TargetBB); 203 204 OldInst->eraseFromParent(); 205 UnCondBrIter->eraseFromParent(); 206 207 UnCondBrIter = MBB.end(); 208 I = MBB.end(); 209 continue; 210 } 211 FBB = TBB; 212 TBB = I->getOperand(0).getMBB(); 213 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 214 continue; 215 } 216 // FIXME: Handle subsequent conditional branches. 217 // For now, we can't handle multiple conditional branches. 218 return true; 219 } 220 return false; 221} 222 223unsigned 224SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 225 MachineBasicBlock *FBB, 226 const SmallVectorImpl<MachineOperand> &Cond, 227 DebugLoc DL) const { 228 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 229 assert((Cond.size() == 1 || Cond.size() == 0) && 230 "Sparc branch conditions should have one component!"); 231 232 if (Cond.empty()) { 233 assert(!FBB && "Unconditional branch with multiple successors!"); 234 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 235 return 1; 236 } 237 238 // Conditional branch 239 unsigned CC = Cond[0].getImm(); 240 241 if (IsIntegerCC(CC)) 242 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 243 else 244 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 245 if (!FBB) 246 return 1; 247 248 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); 249 return 2; 250} 251 252unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const 253{ 254 MachineBasicBlock::iterator I = MBB.end(); 255 unsigned Count = 0; 256 while (I != MBB.begin()) { 257 --I; 258 259 if (I->isDebugValue()) 260 continue; 261 262 if (I->getOpcode() != SP::BA 263 && I->getOpcode() != SP::BCOND 264 && I->getOpcode() != SP::FBCOND) 265 break; // Not a branch 266 267 I->eraseFromParent(); 268 I = MBB.end(); 269 ++Count; 270 } 271 return Count; 272} 273 274void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 275 MachineBasicBlock::iterator I, DebugLoc DL, 276 unsigned DestReg, unsigned SrcReg, 277 bool KillSrc) const { 278 unsigned numSubRegs = 0; 279 unsigned movOpc = 0; 280 const unsigned *subRegIdx = 0; 281 282 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; 283 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; 284 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, 285 SP::sub_odd64_then_sub_even, 286 SP::sub_odd64_then_sub_odd }; 287 288 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 289 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 290 .addReg(SrcReg, getKillRegState(KillSrc)); 291 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 292 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 293 .addReg(SrcReg, getKillRegState(KillSrc)); 294 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { 295 if (Subtarget.isV9()) { 296 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) 297 .addReg(SrcReg, getKillRegState(KillSrc)); 298 } else { 299 // Use two FMOVS instructions. 300 subRegIdx = DFP_FP_SubRegsIdx; 301 numSubRegs = 2; 302 movOpc = SP::FMOVS; 303 } 304 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { 305 if (Subtarget.isV9()) { 306 if (Subtarget.hasHardQuad()) { 307 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) 308 .addReg(SrcReg, getKillRegState(KillSrc)); 309 } else { 310 // Use two FMOVD instructions. 311 subRegIdx = QFP_DFP_SubRegsIdx; 312 numSubRegs = 2; 313 movOpc = SP::FMOVD; 314 } 315 } else { 316 // Use four FMOVS instructions. 317 subRegIdx = QFP_FP_SubRegsIdx; 318 numSubRegs = 4; 319 movOpc = SP::FMOVS; 320 } 321 } else 322 llvm_unreachable("Impossible reg-to-reg copy"); 323 324 if (numSubRegs == 0 || subRegIdx == 0 || movOpc == 0) 325 return; 326 327 const TargetRegisterInfo *TRI = &getRegisterInfo(); 328 MachineInstr *MovMI = 0; 329 330 for (unsigned i = 0; i != numSubRegs; ++i) { 331 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 332 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]); 333 assert(Dst && Src && "Bad sub-register"); 334 335 MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src); 336 } 337 // Add implicit super-register defs and kills to the last MovMI. 338 MovMI->addRegisterDefined(DestReg, TRI); 339 if (KillSrc) 340 MovMI->addRegisterKilled(SrcReg, TRI); 341} 342 343void SparcInstrInfo:: 344storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 345 unsigned SrcReg, bool isKill, int FI, 346 const TargetRegisterClass *RC, 347 const TargetRegisterInfo *TRI) const { 348 DebugLoc DL; 349 if (I != MBB.end()) DL = I->getDebugLoc(); 350 351 MachineFunction *MF = MBB.getParent(); 352 const MachineFrameInfo &MFI = *MF->getFrameInfo(); 353 MachineMemOperand *MMO = 354 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 355 MachineMemOperand::MOStore, 356 MFI.getObjectSize(FI), 357 MFI.getObjectAlignment(FI)); 358 359 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 360 if (RC == &SP::I64RegsRegClass) 361 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) 362 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 363 else if (RC == &SP::IntRegsRegClass) 364 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 365 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 366 else if (RC == &SP::FPRegsRegClass) 367 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 368 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 369 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 370 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 371 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 372 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 373 // Use STQFri irrespective of its legality. If STQ is not legal, it will be 374 // lowered into two STDs in eliminateFrameIndex. 375 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) 376 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 377 else 378 llvm_unreachable("Can't store this register to stack slot"); 379} 380 381void SparcInstrInfo:: 382loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 383 unsigned DestReg, int FI, 384 const TargetRegisterClass *RC, 385 const TargetRegisterInfo *TRI) const { 386 DebugLoc DL; 387 if (I != MBB.end()) DL = I->getDebugLoc(); 388 389 MachineFunction *MF = MBB.getParent(); 390 const MachineFrameInfo &MFI = *MF->getFrameInfo(); 391 MachineMemOperand *MMO = 392 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 393 MachineMemOperand::MOLoad, 394 MFI.getObjectSize(FI), 395 MFI.getObjectAlignment(FI)); 396 397 if (RC == &SP::I64RegsRegClass) 398 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) 399 .addMemOperand(MMO); 400 else if (RC == &SP::IntRegsRegClass) 401 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) 402 .addMemOperand(MMO); 403 else if (RC == &SP::FPRegsRegClass) 404 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0) 405 .addMemOperand(MMO); 406 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 407 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0) 408 .addMemOperand(MMO); 409 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 410 // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be 411 // lowered into two LDDs in eliminateFrameIndex. 412 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0) 413 .addMemOperand(MMO); 414 else 415 llvm_unreachable("Can't load this register from stack slot"); 416} 417 418unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const 419{ 420 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); 421 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); 422 if (GlobalBaseReg != 0) 423 return GlobalBaseReg; 424 425 // Insert the set of GlobalBaseReg into the first MBB of the function 426 MachineBasicBlock &FirstMBB = MF->front(); 427 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 428 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 429 430 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 431 432 433 DebugLoc dl; 434 435 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 436 SparcFI->setGlobalBaseReg(GlobalBaseReg); 437 return GlobalBaseReg; 438} 439