SparcInstrInfo.cpp revision 22fee2dff4c43b551aefa44a96ca74fcade6bfac
1//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Sparc implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcInstrInfo.h" 15#include "SparcSubtarget.h" 16#include "Sparc.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/ADT/SmallVector.h" 19#include "llvm/CodeGen/MachineInstrBuilder.h" 20#include "llvm/CodeGen/MachineRegisterInfo.h" 21#include "llvm/Support/ErrorHandling.h" 22#include "SparcMachineFunctionInfo.h" 23 24#define GET_INSTRINFO_MC_DESC 25#include "SparcGenInstrInfo.inc" 26 27using namespace llvm; 28 29SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 30 : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)), 31 RI(ST, *this), Subtarget(ST) { 32} 33 34/// isLoadFromStackSlot - If the specified machine instruction is a direct 35/// load from a stack slot, return the virtual or physical register number of 36/// the destination along with the FrameIndex of the loaded stack slot. If 37/// not, return 0. This predicate must return 0 if the instruction has 38/// any side effects other than loading from the stack slot. 39unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 40 int &FrameIndex) const { 41 if (MI->getOpcode() == SP::LDri || 42 MI->getOpcode() == SP::LDFri || 43 MI->getOpcode() == SP::LDDFri) { 44 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 45 MI->getOperand(2).getImm() == 0) { 46 FrameIndex = MI->getOperand(1).getIndex(); 47 return MI->getOperand(0).getReg(); 48 } 49 } 50 return 0; 51} 52 53/// isStoreToStackSlot - If the specified machine instruction is a direct 54/// store to a stack slot, return the virtual or physical register number of 55/// the source reg along with the FrameIndex of the loaded stack slot. If 56/// not, return 0. This predicate must return 0 if the instruction has 57/// any side effects other than storing to the stack slot. 58unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 59 int &FrameIndex) const { 60 if (MI->getOpcode() == SP::STri || 61 MI->getOpcode() == SP::STFri || 62 MI->getOpcode() == SP::STDFri) { 63 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 64 MI->getOperand(1).getImm() == 0) { 65 FrameIndex = MI->getOperand(0).getIndex(); 66 return MI->getOperand(2).getReg(); 67 } 68 } 69 return 0; 70} 71 72static bool IsIntegerCC(unsigned CC) 73{ 74 return (CC <= SPCC::ICC_VC); 75} 76 77 78static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 79{ 80 switch(CC) { 81 default: llvm_unreachable("Unknown condition code"); 82 case SPCC::ICC_NE: return SPCC::ICC_E; 83 case SPCC::ICC_E: return SPCC::ICC_NE; 84 case SPCC::ICC_G: return SPCC::ICC_LE; 85 case SPCC::ICC_LE: return SPCC::ICC_G; 86 case SPCC::ICC_GE: return SPCC::ICC_L; 87 case SPCC::ICC_L: return SPCC::ICC_GE; 88 case SPCC::ICC_GU: return SPCC::ICC_LEU; 89 case SPCC::ICC_LEU: return SPCC::ICC_GU; 90 case SPCC::ICC_CC: return SPCC::ICC_CS; 91 case SPCC::ICC_CS: return SPCC::ICC_CC; 92 case SPCC::ICC_POS: return SPCC::ICC_NEG; 93 case SPCC::ICC_NEG: return SPCC::ICC_POS; 94 case SPCC::ICC_VC: return SPCC::ICC_VS; 95 case SPCC::ICC_VS: return SPCC::ICC_VC; 96 97 case SPCC::FCC_U: return SPCC::FCC_O; 98 case SPCC::FCC_O: return SPCC::FCC_U; 99 case SPCC::FCC_G: return SPCC::FCC_LE; 100 case SPCC::FCC_LE: return SPCC::FCC_G; 101 case SPCC::FCC_UG: return SPCC::FCC_ULE; 102 case SPCC::FCC_ULE: return SPCC::FCC_UG; 103 case SPCC::FCC_L: return SPCC::FCC_GE; 104 case SPCC::FCC_GE: return SPCC::FCC_L; 105 case SPCC::FCC_UL: return SPCC::FCC_UGE; 106 case SPCC::FCC_UGE: return SPCC::FCC_UL; 107 case SPCC::FCC_LG: return SPCC::FCC_UE; 108 case SPCC::FCC_UE: return SPCC::FCC_LG; 109 case SPCC::FCC_NE: return SPCC::FCC_E; 110 case SPCC::FCC_E: return SPCC::FCC_NE; 111 } 112} 113 114 115bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 116 MachineBasicBlock *&TBB, 117 MachineBasicBlock *&FBB, 118 SmallVectorImpl<MachineOperand> &Cond, 119 bool AllowModify) const 120{ 121 122 MachineBasicBlock::iterator I = MBB.end(); 123 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 124 while (I != MBB.begin()) { 125 --I; 126 127 if (I->isDebugValue()) 128 continue; 129 130 //When we see a non-terminator, we are done 131 if (!isUnpredicatedTerminator(I)) 132 break; 133 134 //Terminator is not a branch 135 if (!I->getDesc().isBranch()) 136 return true; 137 138 //Handle Unconditional branches 139 if (I->getOpcode() == SP::BA) { 140 UnCondBrIter = I; 141 142 if (!AllowModify) { 143 TBB = I->getOperand(0).getMBB(); 144 continue; 145 } 146 147 while (llvm::next(I) != MBB.end()) 148 llvm::next(I)->eraseFromParent(); 149 150 Cond.clear(); 151 FBB = 0; 152 153 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 154 TBB = 0; 155 I->eraseFromParent(); 156 I = MBB.end(); 157 UnCondBrIter = MBB.end(); 158 continue; 159 } 160 161 TBB = I->getOperand(0).getMBB(); 162 continue; 163 } 164 165 unsigned Opcode = I->getOpcode(); 166 if (Opcode != SP::BCOND && Opcode != SP::FBCOND) 167 return true; //Unknown Opcode 168 169 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); 170 171 if (Cond.empty()) { 172 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 173 if (AllowModify && UnCondBrIter != MBB.end() && 174 MBB.isLayoutSuccessor(TargetBB)) { 175 176 //Transform the code 177 // 178 // brCC L1 179 // ba L2 180 // L1: 181 // .. 182 // L2: 183 // 184 // into 185 // 186 // brnCC L2 187 // L1: 188 // ... 189 // L2: 190 // 191 BranchCode = GetOppositeBranchCondition(BranchCode); 192 MachineBasicBlock::iterator OldInst = I; 193 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) 194 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); 195 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) 196 .addMBB(TargetBB); 197 MBB.addSuccessor(TargetBB); 198 OldInst->eraseFromParent(); 199 UnCondBrIter->eraseFromParent(); 200 201 UnCondBrIter = MBB.end(); 202 I = MBB.end(); 203 continue; 204 } 205 FBB = TBB; 206 TBB = I->getOperand(0).getMBB(); 207 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 208 continue; 209 } 210 //FIXME: Handle subsequent conditional branches 211 //For now, we can't handle multiple conditional branches 212 return true; 213 } 214 return false; 215} 216 217unsigned 218SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 219 MachineBasicBlock *FBB, 220 const SmallVectorImpl<MachineOperand> &Cond, 221 DebugLoc DL) const { 222 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 223 assert((Cond.size() == 1 || Cond.size() == 0) && 224 "Sparc branch conditions should have one component!"); 225 226 if (Cond.empty()) { 227 assert(!FBB && "Unconditional branch with multiple successors!"); 228 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 229 return 1; 230 } 231 232 //Conditional branch 233 unsigned CC = Cond[0].getImm(); 234 235 if (IsIntegerCC(CC)) 236 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 237 else 238 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 239 if (!FBB) 240 return 1; 241 242 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); 243 return 2; 244} 245 246unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const 247{ 248 MachineBasicBlock::iterator I = MBB.end(); 249 unsigned Count = 0; 250 while (I != MBB.begin()) { 251 --I; 252 253 if (I->isDebugValue()) 254 continue; 255 256 if (I->getOpcode() != SP::BA 257 && I->getOpcode() != SP::BCOND 258 && I->getOpcode() != SP::FBCOND) 259 break; // Not a branch 260 261 I->eraseFromParent(); 262 I = MBB.end(); 263 ++Count; 264 } 265 return Count; 266} 267 268void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 269 MachineBasicBlock::iterator I, DebugLoc DL, 270 unsigned DestReg, unsigned SrcReg, 271 bool KillSrc) const { 272 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 273 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 274 .addReg(SrcReg, getKillRegState(KillSrc)); 275 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 276 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 277 .addReg(SrcReg, getKillRegState(KillSrc)); 278 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) 279 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg) 280 .addReg(SrcReg, getKillRegState(KillSrc)); 281 else 282 llvm_unreachable("Impossible reg-to-reg copy"); 283} 284 285void SparcInstrInfo:: 286storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 287 unsigned SrcReg, bool isKill, int FI, 288 const TargetRegisterClass *RC, 289 const TargetRegisterInfo *TRI) const { 290 DebugLoc DL; 291 if (I != MBB.end()) DL = I->getDebugLoc(); 292 293 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 294 if (RC == SP::IntRegsRegisterClass) 295 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 296 .addReg(SrcReg, getKillRegState(isKill)); 297 else if (RC == SP::FPRegsRegisterClass) 298 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 299 .addReg(SrcReg, getKillRegState(isKill)); 300 else if (RC == SP::DFPRegsRegisterClass) 301 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 302 .addReg(SrcReg, getKillRegState(isKill)); 303 else 304 llvm_unreachable("Can't store this register to stack slot"); 305} 306 307void SparcInstrInfo:: 308loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 309 unsigned DestReg, int FI, 310 const TargetRegisterClass *RC, 311 const TargetRegisterInfo *TRI) const { 312 DebugLoc DL; 313 if (I != MBB.end()) DL = I->getDebugLoc(); 314 315 if (RC == SP::IntRegsRegisterClass) 316 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); 317 else if (RC == SP::FPRegsRegisterClass) 318 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); 319 else if (RC == SP::DFPRegsRegisterClass) 320 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); 321 else 322 llvm_unreachable("Can't load this register from stack slot"); 323} 324 325unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const 326{ 327 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); 328 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); 329 if (GlobalBaseReg != 0) 330 return GlobalBaseReg; 331 332 // Insert the set of GlobalBaseReg into the first MBB of the function 333 MachineBasicBlock &FirstMBB = MF->front(); 334 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 335 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 336 337 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 338 339 340 DebugLoc dl; 341 342 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 343 SparcFI->setGlobalBaseReg(GlobalBaseReg); 344 return GlobalBaseReg; 345} 346