SparcInstrInfo.cpp revision 718cb665ca6ce2bc4d8e8479f46a45db91b49f86
1//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Sparc implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcInstrInfo.h" 15#include "Sparc.h" 16#include "llvm/ADT/STLExtras.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include "SparcGenInstrInfo.inc" 19using namespace llvm; 20 21SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 22 : TargetInstrInfo(SparcInsts, array_lengthof(SparcInsts)), 23 RI(ST, *this) { 24} 25 26static bool isZeroImm(const MachineOperand &op) { 27 return op.isImmediate() && op.getImmedValue() == 0; 28} 29 30/// Return true if the instruction is a register to register move and 31/// leave the source and dest operands in the passed parameters. 32/// 33bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, 34 unsigned &SrcReg, unsigned &DstReg) const { 35 // We look for 3 kinds of patterns here: 36 // or with G0 or 0 37 // add with G0 or 0 38 // fmovs or FpMOVD (pseudo double move). 39 if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) { 40 if (MI.getOperand(1).getReg() == SP::G0) { 41 DstReg = MI.getOperand(0).getReg(); 42 SrcReg = MI.getOperand(2).getReg(); 43 return true; 44 } else if (MI.getOperand(2).getReg() == SP::G0) { 45 DstReg = MI.getOperand(0).getReg(); 46 SrcReg = MI.getOperand(1).getReg(); 47 return true; 48 } 49 } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) && 50 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) { 51 DstReg = MI.getOperand(0).getReg(); 52 SrcReg = MI.getOperand(1).getReg(); 53 return true; 54 } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD || 55 MI.getOpcode() == SP::FMOVD) { 56 SrcReg = MI.getOperand(1).getReg(); 57 DstReg = MI.getOperand(0).getReg(); 58 return true; 59 } 60 return false; 61} 62 63/// isLoadFromStackSlot - If the specified machine instruction is a direct 64/// load from a stack slot, return the virtual or physical register number of 65/// the destination along with the FrameIndex of the loaded stack slot. If 66/// not, return 0. This predicate must return 0 if the instruction has 67/// any side effects other than loading from the stack slot. 68unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 69 int &FrameIndex) const { 70 if (MI->getOpcode() == SP::LDri || 71 MI->getOpcode() == SP::LDFri || 72 MI->getOpcode() == SP::LDDFri) { 73 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && 74 MI->getOperand(2).getImmedValue() == 0) { 75 FrameIndex = MI->getOperand(1).getFrameIndex(); 76 return MI->getOperand(0).getReg(); 77 } 78 } 79 return 0; 80} 81 82/// isStoreToStackSlot - If the specified machine instruction is a direct 83/// store to a stack slot, return the virtual or physical register number of 84/// the source reg along with the FrameIndex of the loaded stack slot. If 85/// not, return 0. This predicate must return 0 if the instruction has 86/// any side effects other than storing to the stack slot. 87unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI, 88 int &FrameIndex) const { 89 if (MI->getOpcode() == SP::STri || 90 MI->getOpcode() == SP::STFri || 91 MI->getOpcode() == SP::STDFri) { 92 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && 93 MI->getOperand(1).getImmedValue() == 0) { 94 FrameIndex = MI->getOperand(0).getFrameIndex(); 95 return MI->getOperand(2).getReg(); 96 } 97 } 98 return 0; 99} 100 101unsigned 102SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 103 MachineBasicBlock *FBB, 104 const std::vector<MachineOperand> &Cond)const{ 105 // Can only insert uncond branches so far. 106 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); 107 BuildMI(&MBB, get(SP::BA)).addMBB(TBB); 108 return 1; 109} 110