SparcInstrInfo.cpp revision 80b1ae92922202c197078038c4229045cb1e295f 
1//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Sparc implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcInstrInfo.h"
15#include "Sparc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcSubtarget.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "llvm/Support/TargetRegistry.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/ADT/SmallVector.h"
24
25#define GET_INSTRINFO_CTOR
26#include "SparcGenInstrInfo.inc"
27
28using namespace llvm;
29
30SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
31  : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
32    RI(ST, *this), Subtarget(ST) {
33}
34
35/// isLoadFromStackSlot - If the specified machine instruction is a direct
36/// load from a stack slot, return the virtual or physical register number of
37/// the destination along with the FrameIndex of the loaded stack slot.  If
38/// not, return 0.  This predicate must return 0 if the instruction has
39/// any side effects other than loading from the stack slot.
40unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
41                                             int &FrameIndex) const {
42  if (MI->getOpcode() == SP::LDri ||
43      MI->getOpcode() == SP::LDFri ||
44      MI->getOpcode() == SP::LDDFri) {
45    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
46        MI->getOperand(2).getImm() == 0) {
47      FrameIndex = MI->getOperand(1).getIndex();
48      return MI->getOperand(0).getReg();
49    }
50  }
51  return 0;
52}
53
54/// isStoreToStackSlot - If the specified machine instruction is a direct
55/// store to a stack slot, return the virtual or physical register number of
56/// the source reg along with the FrameIndex of the loaded stack slot.  If
57/// not, return 0.  This predicate must return 0 if the instruction has
58/// any side effects other than storing to the stack slot.
59unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
60                                            int &FrameIndex) const {
61  if (MI->getOpcode() == SP::STri ||
62      MI->getOpcode() == SP::STFri ||
63      MI->getOpcode() == SP::STDFri) {
64    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
65        MI->getOperand(1).getImm() == 0) {
66      FrameIndex = MI->getOperand(0).getIndex();
67      return MI->getOperand(2).getReg();
68    }
69  }
70  return 0;
71}
72
73static bool IsIntegerCC(unsigned CC)
74{
75  return  (CC <= SPCC::ICC_VC);
76}
77
78
79static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
80{
81  switch(CC) {
82  default: llvm_unreachable("Unknown condition code");
83  case SPCC::ICC_NE:   return SPCC::ICC_E;
84  case SPCC::ICC_E:    return SPCC::ICC_NE;
85  case SPCC::ICC_G:    return SPCC::ICC_LE;
86  case SPCC::ICC_LE:   return SPCC::ICC_G;
87  case SPCC::ICC_GE:   return SPCC::ICC_L;
88  case SPCC::ICC_L:    return SPCC::ICC_GE;
89  case SPCC::ICC_GU:   return SPCC::ICC_LEU;
90  case SPCC::ICC_LEU:  return SPCC::ICC_GU;
91  case SPCC::ICC_CC:   return SPCC::ICC_CS;
92  case SPCC::ICC_CS:   return SPCC::ICC_CC;
93  case SPCC::ICC_POS:  return SPCC::ICC_NEG;
94  case SPCC::ICC_NEG:  return SPCC::ICC_POS;
95  case SPCC::ICC_VC:   return SPCC::ICC_VS;
96  case SPCC::ICC_VS:   return SPCC::ICC_VC;
97
98  case SPCC::FCC_U:    return SPCC::FCC_O;
99  case SPCC::FCC_O:    return SPCC::FCC_U;
100  case SPCC::FCC_G:    return SPCC::FCC_LE;
101  case SPCC::FCC_LE:   return SPCC::FCC_G;
102  case SPCC::FCC_UG:   return SPCC::FCC_ULE;
103  case SPCC::FCC_ULE:  return SPCC::FCC_UG;
104  case SPCC::FCC_L:    return SPCC::FCC_GE;
105  case SPCC::FCC_GE:   return SPCC::FCC_L;
106  case SPCC::FCC_UL:   return SPCC::FCC_UGE;
107  case SPCC::FCC_UGE:  return SPCC::FCC_UL;
108  case SPCC::FCC_LG:   return SPCC::FCC_UE;
109  case SPCC::FCC_UE:   return SPCC::FCC_LG;
110  case SPCC::FCC_NE:   return SPCC::FCC_E;
111  case SPCC::FCC_E:    return SPCC::FCC_NE;
112  }
113}
114
115
116bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
117                                   MachineBasicBlock *&TBB,
118                                   MachineBasicBlock *&FBB,
119                                   SmallVectorImpl<MachineOperand> &Cond,
120                                   bool AllowModify) const
121{
122
123  MachineBasicBlock::iterator I = MBB.end();
124  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
125  while (I != MBB.begin()) {
126    --I;
127
128    if (I->isDebugValue())
129      continue;
130
131    //When we see a non-terminator, we are done
132    if (!isUnpredicatedTerminator(I))
133      break;
134
135    //Terminator is not a branch
136    if (!I->getDesc().isBranch())
137      return true;
138
139    //Handle Unconditional branches
140    if (I->getOpcode() == SP::BA) {
141      UnCondBrIter = I;
142
143      if (!AllowModify) {
144        TBB = I->getOperand(0).getMBB();
145        continue;
146      }
147
148      while (llvm::next(I) != MBB.end())
149        llvm::next(I)->eraseFromParent();
150
151      Cond.clear();
152      FBB = 0;
153
154      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
155        TBB = 0;
156        I->eraseFromParent();
157        I = MBB.end();
158        UnCondBrIter = MBB.end();
159        continue;
160      }
161
162      TBB = I->getOperand(0).getMBB();
163      continue;
164    }
165
166    unsigned Opcode = I->getOpcode();
167    if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
168      return true; //Unknown Opcode
169
170    SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
171
172    if (Cond.empty()) {
173      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
174      if (AllowModify && UnCondBrIter != MBB.end() &&
175          MBB.isLayoutSuccessor(TargetBB)) {
176
177        //Transform the code
178        //
179        //    brCC L1
180        //    ba L2
181        // L1:
182        //    ..
183        // L2:
184        //
185        // into
186        //
187        //   brnCC L2
188        // L1:
189        //   ...
190        // L2:
191        //
192        BranchCode = GetOppositeBranchCondition(BranchCode);
193        MachineBasicBlock::iterator OldInst = I;
194        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
195          .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
196        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
197          .addMBB(TargetBB);
198
199        OldInst->eraseFromParent();
200        UnCondBrIter->eraseFromParent();
201
202        UnCondBrIter = MBB.end();
203        I = MBB.end();
204        continue;
205      }
206      FBB = TBB;
207      TBB = I->getOperand(0).getMBB();
208      Cond.push_back(MachineOperand::CreateImm(BranchCode));
209      continue;
210    }
211    //FIXME: Handle subsequent conditional branches
212    //For now, we can't handle multiple conditional branches
213    return true;
214  }
215  return false;
216}
217
218unsigned
219SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
220                             MachineBasicBlock *FBB,
221                             const SmallVectorImpl<MachineOperand> &Cond,
222                             DebugLoc DL) const {
223  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
224  assert((Cond.size() == 1 || Cond.size() == 0) &&
225         "Sparc branch conditions should have one component!");
226
227  if (Cond.empty()) {
228    assert(!FBB && "Unconditional branch with multiple successors!");
229    BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
230    return 1;
231  }
232
233  //Conditional branch
234  unsigned CC = Cond[0].getImm();
235
236  if (IsIntegerCC(CC))
237    BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
238  else
239    BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
240  if (!FBB)
241    return 1;
242
243  BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
244  return 2;
245}
246
247unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
248{
249  MachineBasicBlock::iterator I = MBB.end();
250  unsigned Count = 0;
251  while (I != MBB.begin()) {
252    --I;
253
254    if (I->isDebugValue())
255      continue;
256
257    if (I->getOpcode() != SP::BA
258        && I->getOpcode() != SP::BCOND
259        && I->getOpcode() != SP::FBCOND)
260      break; // Not a branch
261
262    I->eraseFromParent();
263    I = MBB.end();
264    ++Count;
265  }
266  return Count;
267}
268
269void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
270                                 MachineBasicBlock::iterator I, DebugLoc DL,
271                                 unsigned DestReg, unsigned SrcReg,
272                                 bool KillSrc) const {
273  if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
274    BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
275      .addReg(SrcReg, getKillRegState(KillSrc));
276  else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
277    BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
278      .addReg(SrcReg, getKillRegState(KillSrc));
279  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
280    BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
281      .addReg(SrcReg, getKillRegState(KillSrc));
282  else
283    llvm_unreachable("Impossible reg-to-reg copy");
284}
285
286void SparcInstrInfo::
287storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
288                    unsigned SrcReg, bool isKill, int FI,
289                    const TargetRegisterClass *RC,
290                    const TargetRegisterInfo *TRI) const {
291  DebugLoc DL;
292  if (I != MBB.end()) DL = I->getDebugLoc();
293
294  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
295  if (RC == SP::IntRegsRegisterClass)
296    BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
297      .addReg(SrcReg, getKillRegState(isKill));
298  else if (RC == SP::FPRegsRegisterClass)
299    BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
300      .addReg(SrcReg,  getKillRegState(isKill));
301  else if (RC == SP::DFPRegsRegisterClass)
302    BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
303      .addReg(SrcReg,  getKillRegState(isKill));
304  else
305    llvm_unreachable("Can't store this register to stack slot");
306}
307
308void SparcInstrInfo::
309loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
310                     unsigned DestReg, int FI,
311                     const TargetRegisterClass *RC,
312                     const TargetRegisterInfo *TRI) const {
313  DebugLoc DL;
314  if (I != MBB.end()) DL = I->getDebugLoc();
315
316  if (RC == SP::IntRegsRegisterClass)
317    BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
318  else if (RC == SP::FPRegsRegisterClass)
319    BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
320  else if (RC == SP::DFPRegsRegisterClass)
321    BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
322  else
323    llvm_unreachable("Can't load this register from stack slot");
324}
325
326unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
327{
328  SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
329  unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
330  if (GlobalBaseReg != 0)
331    return GlobalBaseReg;
332
333  // Insert the set of GlobalBaseReg into the first MBB of the function
334  MachineBasicBlock &FirstMBB = MF->front();
335  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
336  MachineRegisterInfo &RegInfo = MF->getRegInfo();
337
338  GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
339
340
341  DebugLoc dl;
342
343  BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
344  SparcFI->setGlobalBaseReg(GlobalBaseReg);
345  return GlobalBaseReg;
346}
347